Download Using Intelligent Mixed Signal FPGAs for Hardware

Using Intelligent Mixed Signal FPGAs for Hardware Platform Management
As systems become more complex, managing their internal functions becomes more
demanding to maintain “five nines” or better reliability. Now devices that integrate
processor, peripherals, FPGA and analog circuits can greatly ease the task of providing
comprehensive system management.
by Mark Overgaard, Pigeon Point Systems
Sophisticated systems that are designed to be highly dependable usually includes some
sort of platform management function that monitors and manages the health of the
hardware, including, for instance, its temperature and power consumption aspects. This
management function may conform to a standardized or proprietary framework that
enables coordinated management of a collection of boards or boxes; alternatively, it may
be ad hoc – designed to meet the needs of a particular piece of hardware.
This function, whether standards-based or ad hoc, can be effectively implemented using
an intelligent mixed-signal FPGA, which combines a microcontroller, an analog
subsystem and a traditional field programmable gate array to provide a single device
capable of addressing the needs of this application.
One widely implemented hardware platform management framework is defined by the
PICMG xTCA specifications. Recent articles in RTC Magazine (including two in 2009)
provide background on this framework. LAN-attached xTCA Management Controllers:
How to Build and Use Them, in the October issue, focuses on techniques and benefits for
connecting xTCA controllers to an in-shelf LAN. Using I2C for “Behind-the-Scenes”
Management, in the June issue, covers some of the many ways in which the InterIntegrated Circuit (I2C) bus can be used for auxiliary management functions. The scope
of this article goes beyond xTCA to address other hardware platform management
frameworks, as well as ad hoc approaches.
What is an Intelligent Mixed Signal FPGA?
As previewed above, this category of device augments a traditional FPGA with a
microcontroller subsystem (MSS) that includes a central processing unit (CPU) and a
suitable complement of peripherals. The MSS is complemented with an analog subsystem
that supports multiple analog inputs, either generic or specialized, and provisions for
configuring and orchestrating the collection of analog data. Platform management
firmware runs on the CPU and uses peripherals either within the MSS or implemented in
the FPGA fabric to implement digital management interfaces. The analog subsystem
interfaces to the wide range of analog inputs and outputs that can be relevant to hardware
platform management, such as voltage and current measurements for power rails, chassis,
board and die temperatures, and the like.
Figure 1 is a block diagram for an example intelligent mixed signal FPGA, Actel’s
SmartFusion device. Consistent with the definition above, this device includes an FPGA
fabric (purple), plus a microcontroller subsystem based on an ARM Cortex-M3 processor
(blue) and an analog subsystem (yellow).
Examples of Hardware Platform Management Frameworks
Such a device is capable of being configured and programmed to support a number of
example frameworks. As shown from left to right in Figure 2, these include:
A.
AdvancedTCA (ATCA) and AdvancedMC (AMC), which defines a three level
hierarchy below the System Manager: 1) shelf (or chassis), 2) ATCA board or AMC
carrier board and 3) AMC module. Each of these levels is managed by a controller
type with specific responsibilities: Shelf Manager, IPM Controller (IPMC, with a
Carrier IPMC variant handling subsidiary modules) and Module Management
Controller (MMC), respectively.
B.
MicroTCA (µTCA) and AdvancedMC, also with a three level hierarchy: 1) shelf, 2)
µTCA carrier and 3) AMC module, with corresponding controller types, including
Carrier Manager and MicroTCA Carrier Management Controller (MCMC) for the
middle level and the new Enhanced MMC (EMMC) in the bottom level, respectively.
C.
D.
VITA 46.11, a two-level hierarchy that addresses VITA’s VPX and OpenVPX
architectures: 1) chassis and 2) plug-in module, with corresponding Chassis Manager
and IPMC controller types, respectively. The VITA 46.11 standard, now in
development, aims to adapt and extend the ATCA management framework to fit the
needs of the VPX community.
Data Center Manageability Interface (DCMI), which defines one level below the
overall management software in which each server box or blade is represented
directly by a Baseboard Management Controller (BMC). DCMI aims to provide a
manageability interface optimized for large data centers (perhaps supporting internet
services with hundreds or thousands of servers). A given data center might have a
single preferred set of overall management software, but implement multiple server
types from different vendors, all conforming to a unified framework based on DCMI.
An intelligent mixed signal FPGA could play a primary or secondary role in each of the
management controller blocks below the System Manager layer in these frameworks. In
Figure 2, the three-color “Venn diagram” symbols in each block, consistent with Figure 1
as well, are made up of colors, each of which represents one of the three key FPGA
elements—FPGA fabric, microcontroller and analog subsystem. Furthermore, all the
above frameworks are based on IPMI, the Intelligent Platform Management Interface,
which provides a hardware independent architecture for doing platform management.
IPMI is widely used in the PC and server space and has been adopted as a management
foundation layer for open modular architectures such as xTCA and VPX.
For the three multi-level frameworks (A, B and C on the left), Figure 2 shows a (typically
optional) direct connection to an in-box Ethernet represented by the red line. Such a
connection can enable LAN-level communication with connected controllers, facilitating
such useful services as LAN-based access to serial ports on managed boards, upgrades to
the firmware and FPGA fabric, tracing of IPMB traffic, and so on.
Any of the frameworks in Figure 2 can be chosen by companies who are designing
proprietary platforms that do not aim to comply with any standardized form factor, but
who wish to leverage one of the standardized management architectures. Some such
companies may choose to define and develop an entirely proprietary management
architecture.
The bottom line, however, is that the fundamental functions of hardware platform
management tend to be similar across a wide range of implementations, whether multichassis or single box, standardized or proprietary, framework-based or ad hoc, IPMIinfluenced or not. How do these functions map to the capabilities of an intelligent mixed
signal FPGA, and which of them especially benefit from capabilities of such an FPGA?
Mapping Key Controller Functions to an Intelligent Mixed Signal FPGA
Traditionally, management controllers are based on microcontroller devices. A number
of management controller functions can especially benefit from combining an analog
subsystem and an FPGA fabric with the microcontroller core. One key theme is that this
model can allow integrating critical functionality of the managed board that would
otherwise require separate devices, with corresponding reductions in bill of material costs
and board footprint requirements.
Management controllers often need multiple I2C ports, including for the in-the-box
management buses such as the I2C-based dual redundant Intelligent Platform
Management Bus (IPMB) defined by xTCA. In addition to framework-defined uses, such
ports can access on-board I2C peripherals like digital temperature sensors. For boards
that can host managed mezzanine modules, like AdvancedMC carrier boards,
implementing a distinct I2C bus for the local IPMB connection with each module site can
yield performance and reliability benefits. An FPGA fabric in the management controller
can be populated with additional I2C IP blocks as necessary to meet the needs in this area
of a particular board.
IPMI-based management controllers often need to communicate with one or more onboard main processors. A key IPMI-defined implementation for that communication is a
register interface that is often implemented via a Low Pin Count (LPC) bus connection
between the main processor and the management controller. In fact, managementfocused microcontrollers often include a direct implementation of this IPMI register
interface. With an FPGA fabric in the management controller, this function can be added
via an IP block. Furthermore, various LPC peripherals such as serial ports can also be
added in the FPGA fabric, absorbing functions that would otherwise require separate
devices on the board.
An FPGA in a management controller can also absorb arbitrary auxiliary logic on the
board, possibly eliminating one or more Complex Programmable Logic Devices (CPLDs)
or discrete logic. If any of this logic (say, power enables or other signals affecting the
main part of the managed board) involves signals that need to be persistent across
watchdog resets of the microcontroller, they can be implemented in the FPGA fabric and
configured so that soft resets of the microcontroller subsystem do not affect them. xTCA
management controllers are required to be protected by watchdogs, which typically do a
soft reset of the controller when they expire.
Another use for auxiliary logic could be the sequencing of on-board power rails. With an
FPGA and an analog subsystem coupled to the FPGA, more sophisticated power rail
management can be integrated into the management controller. For instance, the FPGA
logic can connect with triggers from the analog subsystem that signal that a given power
rail has reached its required voltage threshold during a power-up sequence or has fallen
below its minimum level in a fault-detection scenario. These triggers can result in
FPGA-implemented hardware responses or interrupts to request firmware involvement.
Meanwhile, in addition to orchestrating on-board activities such as power rail sequencing,
the management controller can provide visibility to upper layers of management for
analog and digital sensors, such as temperatures, voltages and currents (including for
monitored power rails), digital signals such as switch states and summary status signals
like Power Good.
Table 1 summarizes these key areas of functionality, highlighting the extent of
involvement in each of them for the microcontroller, analog and FPGA subsystems of an
intelligent mixed signal FPGA.
Example Management Controller Based on Intelligent Mixed Signal FPGA
What would a specific management controller built to this model look like? Figure 3
shows a block diagram for an AdvancedTCA IPMC or Carrier IPMC reference design
that is delivered in the corresponding Pigeon Point Board Management Reference (BMR)
solution kits for xTCA. Figure 3 includes numbered examples of several of the key
functional areas described in the last section, including:
1. This section provides for additional logic, including an I2C port, for each site on
the board that can host an AdvancedMC module.
2. This set of GPIO interfaces is latched across Cortex-M3 watchdog resets, so that
power rail enables and other key signals are not affected.
3. The analog section monitors a wide range of sensors, including voltage and
current for various power rails, plus temperature sensors. This subsystem in the
SmartFusion device does all threshold checking itself; the Cortex-M3 only gets
involved when a threshold has been crossed.
4. Here, a CoreLPC block in the FPGA fabric implements, via an LPC bus, the
IPMI-defined register interface for communicating with the main processor
(referenced as the payload, in this diagram).
In addition, area 5 in Figure 3 shows a way to implement the LAN attachments captured
in Figure 2: either the supplementary connections in the frameworks ATCA, µTCA and
VITA 46.11 frameworks or the primary connection in a DCMI framework. The
SmartFusion-based reference design shown in Figure 3 is now being incorporated in the
ATCA board designs of numerous leading ATCA, AMC and VPX board and module
developers.
Pigeon Point Systems, Scotts Valley, CA (831) 438-1565. [www.pigeonpoint.com]