Download Circuit Implementation of a Theoretical Model of Trap Centres in

Circuit Implementation of a Theoretical Model of
Trap Centres in GaAs and GaN Devices
James G. Rathmella and Anthony E. Parkerb
a School
b Department
of Electrical Engineering, The University of Sydney, Australia 2006;
of Electronic Engineering, Macquarie University, Sydney, Australia 2109
ABSTRACT
A novel and simple circuit implementation of trap centres in GaAs and GaN HEMTs, MESFETs and HFETs is presented.
When included in transistor models it explains the potential-dependent time constants seen in the circuit manifestations of
charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time- and harmonic-domain
simulations. The trap-centre model is based on Shockley-Read-Hall (SRH)1 statistics of the trapping process. It also
accommodates carrier injection from other important device effects, such as impact ionization and light sensitivity.
In the model, the ionization charge of the trap centre is represented by the charge in a capacitor. The potential across the
capacitor is proportional to the potential across the region of the trap centre in the semiconductor. It is positive or negative
depending on the polarity of the ionization charge—electrons or holes. When included in a transistor model, this potential
is added to the gate potential that controls the drain-current description.
The capacitor is charged or discharged by two opposing currents that are functions of the ionization potential and
temperature: one models charge emission; and the other, which is also controlled by an external potential and injected
current, models charge capture. The external potential is typically a linear function of a transistor’s terminal potentials.
The injection current can model charge generated by light or by holes from impact ionization.
The four parameters for the model are simply the signed potential of the trap centre when fully ionized, the time
constant for charge emission at a specific temperature, the injection-current sensitivity, and the activation energy of the
emission process. The latter is used to predict the temperature dependence of the emission rate. The capture rate is
determined within the model by an exponential function of the external potential that controls capture. Thus the model
elegantly predicts asymmetry between trap charging and discharging rates. The model accounts for variation in emission
and capture rates with temperature, which is shown to vary significantly over typical transistor operating ranges.
Keywords: Charge trapping, microwave FET, semiconductor charge-carrier processes, semiconductor device measurements, semiconductor device modeling
1. INTRODUCTION
Charge trapping, which is associated with transient manifestations of gate lag and drain overshoot, is a problem in
compound-semiconductor FETs. This occurs in both MESFET and HEMT short-channel FETs, in both GaAs and GaN
technologies. It is generally more pronounced in GaN,2 where the observed current collapse is attributed to surface and
substrate trapping. Figure 1 shows the pulsed-I/V characteristics for typical GaAs devices, from a cold bias and for pulse
times of from 1μs to 0.1s (near dc). Three effects are evident here: self-heating in the droop at high power, the gate lag of
a yet-to-be identified trapping phenomenon, and, in the case of the pHEMT, the effect of impact ionization manifest as the
kink above a drain potential of 2 or 3 V.
How significant a problem trapping is depends on the use to which these devices are put. For small-signal, narrow-band
signals of a frequency very-much greater than the time constants of trapping, it is not significant except for a slight shift
in bias. However, the trapping time constants increase dramatically with drain potential, so they can affect signals in the
microwave region at high drain potentials.3
Further author information: (Send correspondence to J.G.R.)
J.G.R.: E-mail: [email protected], Telephone: +61-2-9351-2981, Fax: +61-2-9351-3847
A.E.P.: E-mail: [email protected]
350
300
1e-6
1e-5
1e-4
1e-3
1e-2
1e-1
1e-0
300
Drain Current (mA)
Drain Current (mA)
350
1e-5
1e-4
1e-3
1e-2
1e-1
1e-0
400
250
200
150
100
250
200
150
100
50
50
0
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
0
2
Drain-Source Potential (V )
4
6
8
10
Drain-Source Potential (V )
(a)
(b)
Figure 1: I/V characteristics showing the dynamic nature of GaAs devices measured at various pulse times, for a) a pHEMT
and b) a MESFET. Evident, to varying degrees, are the thermal, impact ionization and charge-trapping effects.
In many applications, devices are used under broadband, large-signal conditions. This can mean that the difference
frequencies in these large-bandwidth signals fall in the region of the microsecond time constants of trapping.4, 5 Thus, the
charging and discharging of traps are invoked by the envelop of these signals. Additionally, devices are often intermittently
switched, in which the device cycles from one bias condition to another. This change in bias condition will also change the
trapping state.
Trapping is generally thought to be due to deep-level electron or hole states in the substrate and/or the surface regions.6–9
Also, there is a trade-off between impact ionization and the extent to which surface states are significant.10 Previous models
of trapping have either not dealt with large-signal behaviour,11 have fixed trap time constants,12 or are complicated.13 An
accurate and robust model is required to fully describe behaviour from DC to RF.14 Such a model can be implemented as
a feedback network that is separate from the effects of self-heating15 and perhaps impact ionization16 within the transistor
model. This arrangement will be able to model both small-signal and large-signal behaviour.17
This paper reports an implementation of the Shockley-Read-Hall (SRH)1 model of recombination of holes and electrons
in solid-state electronics. Section 2 derives a simple yet elegant model for a charge-trapping centre, using a number of
simplifying assumptions and a set of definitions listed in Appendix A. Section 3 applies this model to a FET, yielding a
simple yet effective circuit model that can be used in time- and harmonic-domain simulators, including the extension of
this model to include the effects of impact ionization, while Section 4 applies these models to a real device. From this,
Section 5 draws some conclusions for FET modelling.
2. SRH MODEL
Charge trapping in semiconductors occurs in energy states within the band gap. The processes involved are governed by
Fermi-Dirac statistics and the charge densities at various points in the band gap can be simply defined for holes p in the
valence band and electrons n in the conduction band (using the definitions in Appendix A);
EV − F I
F I − EC
p = NV exp
, and n = NC exp
.
(1)
−T
−T
k
k
Of interest is the charge stored in the trap. The trap is either an acceptor state A, or a donor state D. We wish to
derive expressions for the charge in either trap. The density of ionized donor-level states (holes) and the density of ionized
acceptor-level states (electrons) are defined by;
pD =
1 + gD
ND
,
D
exp FT−k−E
T
and
nA =
1+
1
gA
NA
.
T
exp EA−k−F
T
(2)
2.1 Rates of Charge Capture and Emission
There are four competing processes for transferring charge from the trap level to the valence and conduction bands (see
Sec. 2 of Ref. 1). These are electron capture and emission, and hole capture and emission.
Electron capture consists of an electron dropping from a conduction-band level to the trap level. This is a reduction of
electron energy. The rate of electron capture cn is the product of the capture cross-section and the thermal velocity of the
electrons: cn = σn vn . The rate of electron-density increase due to electron capture by the trap is the product of the capture
rate, the density of electrons (in the conduction band) available for capture, and the density of trap sites not occupied by an
electron. These are:
⎧
for a donor trap
⎨ pD
Rcn = cn n
(3)
⎩
for an acceptor trap.
NA − nA
Electron emission, on the other hand, is the promotion of electrons from the trap level to the higher energy of the
conduction band. In thermal equilibrium, the rate of electron emission en is balanced by the rate of electron capture. The
ratio of emission to capture for this is the fraction of electrons with sufficient thermal energy to jump between the trap and
conduction-band levels (see Eq. 2.9 of Ref. 1). Thus,
⎧
C
for a donor trap
exp ED−k−E
⎨
T
en
=
(4)
⎩
cn
C
exp EA−k−E
for
an
acceptor
trap.
T
The rate of electron-density reduction due to electron emission by the trap is then the product of the emission rate, the
density of states that can accept the electron, and the density of trap sites occupied by an electron:
⎧
C
(ND − pD ) for a donor trap
⎨ exp ED−k−E
T
Ren = cn NC
(5)
⎩
C
n
for
an
acceptor
trap.
exp EA−k−E
A
T
Hole capture consists of a hole moving from a valence-band level to the trap level. This is a reduction of hole energy.
The rate of hole capture cp is the product of the capture cross-section and the thermal velocity of the holes: cp = σp vp .
The rate of hole-density increase due to hole capture by the trap is the product of the capture rate, the density of holes (in
the valence band) available for capture, and the density of trap sites not occupied by a hole. These are:
⎧
for a donor trap
⎨ ND − p D
Rcp = cp p
(6)
⎩
for an acceptor trap.
nA
Hole emission, on the other hand, is the promotion of holes from the trap level to the higher energy of the valence
band. In thermal equilibrium, the rate of hole emission ep is also balanced by the rate of hole capture:
⎧
D
exp EV−k−E
for a donor trap
⎨
T
ep
=
(7)
⎩
cp
A
for
an
acceptor
trap.
exp EV−k−E
T
The rate of hole-density reduction due to hole emission by the trap is the product of the emission rate, the density of
trap sites occupied by a hole, and the density of states that can accept the hole:
⎧
D
pD
for a donor trap
⎨ exp EV−k−E
T
Rep = cp NV
(8)
⎩
A
(N
−
n
)
for
an
acceptor
trap.
exp EV−k−E
A
A
T
The net rate of charge accumulation in a trap is then the sum of the rates of the capture and emission processes.
For a donor trap, EC − ED < ED − EV , so Rcp Rcn and Rep Ren . This implies that the donor level functions
as an electron trap (see Eq. 2.18 of Ref 18). The rate of hole accumulation in a donor trap (ionization of the trap) is then:
d pD
dt
=
Rcp − Rep + Ren − Rcn
≈
Ren − Rcn
(9)
ED − EC
= cn (ND − pD ) NC exp
− cn n pD
−T
k
ED − EC
F I − EC
= cn NC (ND − pD ) exp
exp
−
p
D
−T
−T
k
k
F I − ED
= ωoD (ND − pD ) − pD exp
−T
k
where
ωoD = cn NC exp
ED − EC
−T
k
.
(10)
For an acceptor trap, EC − EA > EA − EV , so Rcp Rcn and Rep Ren . This implies that the acceptor level
functions as an hole trap. The rate of electron accumulation in the acceptor trap (ionization of the trap) is then:
d nA
dt
=
Rep − Rcp + Rcn − Ren
≈
Rep − Rcp
(11)
EV − EA
= cp (NA − nA ) NV exp
− cp p nA
−T
k
EV − EA
EV − F I
= cp NV (NA − nA ) exp
exp
−
n
A
−T
−T
k
k
EA − F I
= ωoA (NA − nA ) − nA exp
−T
k
where
ωoA = cp NV exp
EV − EA
−T
k
.
(12)
2.2 Trap Charge and Temperature Dependence
√
Over typical operating temperatures, the thermal velocities vp,n are proportional to T and the conduction- and valanceband densities NC,V are proportional to T 3/2 (See Ch. 2 of Ref. 19). Thus ωoA and ωoD are of the form
Eact
ωo = BT 2 exp −
,
(13)
kT
for constant B and activation energy Eact .
A trap capacity per-unit-volume can be defined in terms of a trap potential and the trap’s ionization density as follows:
q pD
=
q nA
= −CA vT A .
CD vT D ,
(14)
The currents into a unit volume of traps then follow as, substituting Eq. (14) into Eqs. (9) and (11):
F I − ED
q ND
d pD
= ωoD CD
iD = q
− vT D − vT D exp
, and
−T
dt
CD
k
EA − F I
−q NA
d nA
= ωoA CA
− vT A − vT A exp
.
iA = −q
−T
dt
CA
k
(15)
(16)
The dynamics of the trap can be described by a current source driving a capacitor with voltage vT across it. Drawing
upon the definition of the electron volt in equating a trap controlling-potential vI and the trap energy, expressed in eV, the
current into the capacitor would be iT given by:
v I
iT = ωo C (Vo − vT ) − vT exp −
(17)
kT
where
Vo =
ωo =
⎧
⎨
⎩
q ND
C
for a donor trap
−q NA
C
for an acceptor trap,
(18)
⎧
C
⎨ cn NC exp ED−k−E
T
⎩
cp NV exp
EV −EA −
kT
for a donor trap
(19)
for an acceptor trap,
and
vI =
⎧
⎨ F I − ED
for a donor trap
⎩
for an acceptor trap.
(20)
EA − F I
The characteristic frequency for this system is given by the inverse of the product of the capacitance and the dynamic
resistance of the trap:
v 1 d
I
.
(21)
ω=−
iT = ωo 1 + exp −
C dvT
kT
3. CIRCUIT MODEL OF TRAPPING
A circuit model of the emission and capture processes in a trap centre is shown in Fig. 2(a). The charge in the capacitor
CT is analogous to the ionized charge in the trap. The value of CT could be chosen to account for the physical dimensions
of the trap centre, but is better set to give currents and potentials that suit the circuit simulator. In the latter context, the
charge in the trap model is:
(22)
qT = CT vT
where the trap potential is vT < 0 for a hole trap (acceptor case in Eq. (14)) or vT > 0 for an electron trap (donor case).
The polarity of trap ionization is consistent with the polarity of vT .
The current iC flowing into the capacitor is analogous to capture of charge by the trap. This is expressed in terms of
the capture rate and an external control potential as follows:
v I
(23)
iC = ωo CT vT exp −
kT
where ωo is the characteristic frequency of charge capture given by Eq. (13), and vI is the driving potential for the trap
analogous to relative position of the quasi-fermi-level with respect to the energy of the trap level. The polarity of iC is
consistent with the polarity of the trap potential vT . Also, a physical requirement is that Vo < vT < 0 for a hole trap or
0 < vT < Vo for an electron trap.
log(ω)
vI
iC
iE
CT
vT
−
ωo [1 + exp(vI /k
T )]
ωo
(a)
vI
(b)
Figure 2: Circuit model of a trap centre (a) and the characteristic frequency of the trap centre (b).
The current iE flowing out of the capacitor is analogous to emission of charge by the trap. This is expressed in terms
of the emission rate as follows:
(24)
iE = ωo CT (Vo − vT )
where Vo is the capacitor potential that corresponds to the fully-ionized trap state.
Under steady-state conditions, the capture and emission currents are equal, so a relationship between the control potential and the trap potential is obtained from Eq. (23) and (24):
vT =
Vo
.
1 + exp −kvTI
(25)
3.1 Empirical Behavior
The time constant of the trap-centre model in Fig. 2(a) is the product of the capacitance and dynamic resistances of the
current sources. The characteristic frequency for the trap centre is given by Eq. (21). This is illustrated in Fig. 2(b).
The steady-state trap potential is given by Eq. (25) and is shown in Fig. 3. The donor trap has a positive potential
when ionized and acts as an electron trap. That is, it captures electrons from the conduction band. The acceptor trap has
a negative potential when ionized and acts as a hole trap. That is, it captures holes from the valence band. The potential
of either trap is constrained between zero, or the neutral-charge condition, and the fully-ionized state set by Vo , given by
Eq. (18).
3.2 Application to FETs
Field-effect transistors can be affected by several trap processes. These are donor or acceptor traps in either the surface,
interface or substrate regions. The traps can be considered to be adding to the gate-source potential vGS of the device.
Because the trap circuit of Fig. 2(a) is a low-pass filter, the trap potential vT does not respond instantly to input changes in
vI . This is the origin of gate lag in short-channel FETs.
For a FET, the drain-source current iDS is a function of the terminal potentials. In the presence of a trap centre, this is
now a function of the trap potential as well:
iDS = f (vGS + vT , vGD ).
(26)
Referring to Fig. 3(b), for the case of an acceptor/hole trap, when the transistor is biased off, below pinch-off, the trap is
considered to be near its fully-ionized state, Vo . Upon a step-change in terminal potentials to an on-state, the trap would
be considered to be moving towards a neutral-charge condition. However, in the trap model, because the trap potential vT
vT
Vo =
qND
CT
vT
Turn-on Lag
v I = EA − F I
vI = F I − ED
Turn-on Lag
A
Vo = − qN
CT
(a) Electron Trap
(b) Hole Trap
Figure 3: Variation of the steady-state trap potential with the driving potential, vI for (a) a donor- and (b) an acceptor-trap
centre. Arrows indicate the change in trap potential that occurs when a transistor is turned on.
cannot change instantly, a component of iDS would lag the causal change in terminal potentials, at a time determined by
the characteristic frequency of the trap ω.
Figure 4 shows trap current iT = iE − iC as a function of trap potential vT , for both types of traps. From Eq. (17),
and Eqs. (23) and (24), the emission current is inversely proportional to vT and moves between iE = 0 when Vo = vT and
iE = ωo CT Vo when vT = 0. The capture current is proportional to vT and changes in response to vI . The total current at
any time is then the sum of these and, at equilibrium, must be zero.
Referring to Fig. 4(a), for an acceptor/hole trap, we consider a transistor switching between off and on and off again.
For the transistor at equilibrium and biased in an off state, point a, near Vo , we consider a step-change in terminal potentials
from vI (t1 ) to vI (t2 ). Because vT cannot change instantly, we move to point b, representing a large increase in capture
current. From here we quickly move to point c as the capacitor voltage vT changes to an equilibrium again with capture
and emission currents equal. For a step change in terminal potentials in the other direction, from on-state to off-state, we
would follow the path c → d → a. Here, we would have a decrease in capture current and a slow return to equilibrium,
dictated by the dynamic conductance (slope) of the current curve. This shows the origins of the different times involved
with gate lag and drain droop with a FET. A similar situation applies to the donor/electron trap.
3.3 Charge Injection
Figure 5(a) shows these currents plotted individually, in the case of an acceptor trap. The equilibrium position must be
when the lines for emission iE and capture iC currents intersect. A step change in vI will give a step change in iC (Eq. (23))
but not iE (Eq. (24)) as vT cannot change instantly. Both currents will then change over time to become equal.
The number of holes p and electrons n available for interaction with the traps is proportional (Eq. 1) to the densities
of states NV and NC . Additional change in local charge due to drift in the region of these traps would result in changes
to NV and NC and hence p and n, respectively. Figure 5(b) shows what would happen to the various currents under these
conditions.
Impact ionization16 is one such phenomena that results in a current of holes in the trap region (a current from the drain
to the gate). From Eqs. (17)–(19), this would result in a change in the capture current for an acceptor trap. This could be
accommodated in a simulation by making the term for capture current proportional to a component of drain current related
to the impact-ionization rate.
iT = iE − iC
−ωa CT Va
d
Va
iT = iE − iC
−ωa CT Va
a
vI (t1 )
vI ↓
Va
iE
b
(a)
Vd
vI ↓
Acceptor iT (vI )
vI (t2 )
iT (vI ) Donor
vI ↑
vT
c
vT
iE
vI ↑
Acceptor (Hole Trap)
−ωd CT Vd
Donor (Electron Trap)
(b)
Figure 4: Total trap current iT = iE − iC as a function of trap voltage vT . This shows the dynamic nature of vT with
respect to step changes in vI (a), and for the general case (b).
3.4 Control by Terminal Potentials
Each of the four dynamic trap processes (donor or acceptor, surface or substrate) exhibit specific frequency and bias
dependencies that can be used to identify them. A behavioral description of the relationship between terminal potentials
and the trap-control potential is:
(27)
vI = α.vGS + γ.vGD − φ
where α, γ and φ are fitting parameters.
In general, any combination or number of traps can be implemented to suit particular devices and processes. The sum
of the ionization potential of these traps is added to the gate potential of a static drain-current element.
Consider a hole trap in the substrate; α > 0, which ionizes the trap to a more negative potential as the transistor is
pinched off by a negative gate potential, and γ > 0, which reduces the ionization as the drain potential is increased. This
models the effect of electron injection toward the substrate reducing the ionization of the hole trap. This ionization of the
trap when the transistor is pinched off is at the emission rate. When the transistor is turned on, there is a delay or gate lag
while the trap captures holes at a capture rate that exponentially increases with vI and also with temperature. The dynamic
for this, which is observed in pulse measurements, is that the gate lag is slower at lower drain potentials and that the time
required in the off state is independent of bias.
As a second example, consider an electron trap at the surface; α < 0, which ionizes the trap to a more positive potential
as the gate potential increases, and γ > 0, which reduces the ionization as the drain potential is increased. This models
the effect of holes injected into the surface increasing the ionization of the electron trap. The trap is also ionized by hole
current from impact ionization that generates the kink in the drain-current characteristics. This is included as an injection
current feeding the trap-centre model. When the transistor is turned on at high drain potential, there is a gate lag while
the injection current ionizes the traps at the emission rate. When the drain potential is subsequently reduced, the trap will
capture holes at a rate that exponentially increases with vI and that also depends on temperature. The dynamic for this is
that the formation of the kink in the characteristics is slower at lower drain potentials.
vT (vI )
iE , iC
iE , iC
Vo
Vo
iC
iC
ωo CT Vo
ωo CT Vo
n Inj.
iE
iC for increasing vI
p Inj.
(a)
iE
(b)
Figure 5: Graphical representation of the solution to Eq. (25) for an acceptor trap. Increasing vI increases the capture rate
(a). Injection of charge (b) gives an increase in hole-capture rate if holes are injected, or an increase in election-emission
rate if election are injected.
4. DISCUSSION
Figure 6(a) shows a simulation of the effect of temperature on trap characteristic frequency, something that can only be
indirectly inferred in an actual device. This frequency is seen to varies by several orders of magnitude over a practical
temperature range. Thus, the inclusion of temperature in the trap centre model will more-closely model gate lag for
high-power devices.
Figure 6(b) shows measured and simulated drain-current transients for the pHEMT of Fig. 1(a). This shows the pulse
profile of drain current for vDS =1.5 (bottom set), 2.0, 2.5, 3.0 and 3.5 V (top set) and a gate potential vGS =0.0 V, versus
log(time) after a step away from an initial bias. Before the step, the drain-bias potential varies between VDS =0.0 to 3.5 V
and the gate-bias potential is VGS = –3.0 V. The extent of trap charge prior to stepping varies with drain bias, as evidenced
by the greater gate lag. The time constant of the gate lag also varies with target drain potential—being faster for greater
potential. The simulation is able to capture these various potential-related effects.
Trapping, self-heating and, to some extent impact ionization, are evident in all devices and should be considered for all
but small-signal and small-bandwidth requirements. Heating is significant in large devices.
For impact ionization there is a strong drain-bias dependence and a weak gate-bias dependence. FETs exhibit impact
ionization although for low-breakdown HEMTs and MESFETs it usually occurs at or above breakdown. A kink in the DC
(>10ms time frame) characteristics indicates the presence of impact ionization and is associated with an increase in gate
current due to additional holes from the channel. At drain biases below that of the kink, impact ionization will have little
effect. At higher biases there is a significant improvement to linearity, but this is abruptly band-limited to the characteristic
frequency of the trapping mechanism associated with impact ionization. The latter can be at very-high frequencies at high
bias, however.
Generally, all FETs exhibit trapping according to the extent of surface and substrate deep-level traps. For the trapping
seen here, there is a strong gate-bias dependence and a weak drain-bias dependence. This is generally attributed in the
literature6–9 to substrate traps. This is seen in GaAs HEMTs and implanted MESFETs.13 Another type of trap exhibits
both a strong drain-bias dependence as well as a strong gate-bias dependence and is thought to be due to surface traps.
This type of trap is encountered in GaN devices2 and GaAs epitaxial MESFETs. There is thought to be a trade-off between
the number of surface traps and impact ionization. Although the charge/discharge of an electron trap could be thought of
as the discharge/charge of a hole trap, these traps are generally thought to be hole traps.9 The single time constant of trap
discharging (emission) rather than the variable time constant of capture would be the determining factor.18
The model developed here should apply equally-well to surface traps, using drain-gate potential to drive the model
network as well as the gate-source potential. Temperature would play an important role in determining trap charging and
discharging rates, and the extra holes present with impact ionization would increase these rates. These are important for a
fuller model.
360
Drain Current (mA)
12
log(ω/2πC)
10
8
6
T (o C)
4
-20
20
60
100
140
180
2
0
-1
-0.5
0
vi /Eact (V /eV )
340
320
300
280
260
240
220
200
0.5
1
-6
-5
-4
-3
-2
-1
log(time)
(a)
(b)
Figure 6: Simulation (a) of f =ω/2πC (Eq. 21) for Eact =0.5 eV and fo =103 Hz @ Ta =20o C. Graph (b) shows measured
(points) and simulated (lines) drain-current transients for the pHEMT of Fig. 1(a).
5. CONCLUSION
A novel yet simple model for substrate electron trapping has been proposed together with an extraction procedure for the
parameters involved. This models the dispersion due to trapping distinct from the dispersion due to self-heating and impact
ionization. When combined with other model networks to handle self-heating and impact ionization, the resulting complete
model will be able to handle large-signal and small-signal behaviour over frequencies from DC to RF.
An important area of future investigation is the analysis and incorporation of impact-ionization effects, so that an
isodynamic current can be determined. Note that impact ionization will exhibit a frequency dependence, so a similar
analysis and modeling procedure may prove appropriate. The approach to the characterization of trapping and modeling
presented here is based on simple physical concepts and observed effects. Therefore, it has broad application to other
devices and material systems. It should also be readily extendable to surface traps.
Acknowledgements
Manuscript prepared November 13, 2007. This work was supported by the Australian Research Council.
APPENDIX A: DEFINITIONS
EA Effective energy of the acceptor level [eV]
NA Density of acceptor-trap states [cm−3 ]
EC Energy level of the bottom of the conduction band [eV]
NC Conduction-band effective density of states [cm−3 ]
ED Effective energy of the donor level [eV]
ND Density of donor-trap states [cm−3 ]
EV Energy level of the top of the valence band [eV]
NV Valence-band effective density of states [cm−3 ]
FI Quasi-Fermi-level for holes and electrons [eV]
p Density of holes in the valence band [cm−3 ]
FT Quasi-Fermi-level for the traps [eV]
gA Ground-state degeneracy of the acceptor level (gA = 4)
gD Ground-state degeneracy of the donor level (gD = 2)
k Boltzmann’s constant [J/K]
−
−
k Boltzmann’s constant (k
= k/q) [eV/K]
n Density of electrons in the conduction band [cm−3 ]
nA Density of ionized acceptor level states (electrons) [cm−3 ]
pD Density of ionized donor-level states (holes) [cm−3 ]
q electron charge [C]
σn Capture cross-section of electrons [cm2 ]
σp Capture cross-section of holes [cm2 ]
T Temperature [K]
vn Thermal velocity of electrons [cm/s]
vp Thermal velocity of holes [cm/s]
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