Download Abstract - The University of Texas at El Paso

Designing a 960 MHz LNA and Mixer with
0.5µm CMOS process technology Using ADS
EE 5390
Zhigang Cao
Yuhua Liu
Project Supervisor
Dr. Tim S. Yao
The University of Texas at El Paso
Abstract
This project is to design a CMOS circuit that satisfies the functional requirement
of LNA and MIXER at 960MHz. The goal of these two parts is to design a small
standard analog function which can then be part of a larger project such as a transceiver
design. The whole project will be designed using a 0.5µm CMOS process technology.
Introduction
The first stage of this project is to design a low noise amplifier (LNA), whose
main function is to provide enough gain to overcome the noise of subsequent stages, such
as a mixer. LNA should provide this gain while adding as little noise as possible since
normally the overall noise figure of a receiver is dominated by the first stage of the
design. Also a LNA should accommodate large signals without distortion, and frequently
must also present a specific impedance of 50Ω to the input source. In addition,
a LNA should provide low power consumption since the power dissipation is a key in
design especially in portable systems.
A mixer converts a signal from one frequency ωRF to another frequency ωIF with a
certain gain. It receives the RF signal directly from the LNA, or from a filter –depending
on the receiver architecture, and performs frequency translation by multiplying it with
that of a local oscillator (LO) and their respective harmonics. This multiplication yields
two signals in the frequency spectrum at ωRF + and – ωIF. Typically, many RF signals
may exist, but only one is desired. This means that one of the main concerns in a mixer is
linearity of the RF input to prevent intermodulations between various input signals. Other
issues of importance are frequency response, power dissipation and noise.
Analysis of Design
1. LNA Design:
Design requirement
The specifications required for the LNA design were the following:
 Frequency range: 940~980 MHz
 Input impedance Zin: |Zin| = 50 ohm ± 10%, < Zin = 0 ± 2.5 degree
 Voltage gain: AV > 20 dB
 Noise Figure: NF with 50 ohm input matching < 3 dB
 P1dB > -20 dBm
 IIP3 > -10 dBm
 Total current < 5 mA
The design of an LNA is full of trade-offs between optimum gain, low noise figure,
optimum input impedance matching, high linearity and low power consumption. The
design of the LNA seems very simple and easy because there are relatively few
components, but these trade-offs complicate the design. In fact, getting a optimum design
result of LNA which meets all the requirement is quite a tough job.
Design Procedure
1. Choosing Circuit Topology:
As we know, the common source circuit is the best suited for obtaining the bulk
of the gain required in an amplifier due to its advantage of high input resistance and
relative high voltage gain it can get.
The common gate circuits have open circuit voltage gains almost equal to that of
the common-source circuits. Its input resistance, however is much smaller and their
output resistance much larger than the corresponding values for the common source
amplifiers. These two properties make the common gate circuits suitable as a current
buffer. The most important thing is : the absence of the miller effect in common gate
circuit makes the high frequency response of this kind of circuits far superior to that of
the common source amplifiers.
So combining these two kinds of circuits together, we will get the cascode
amplifier which takes both the advantages of common source circuit and common gate
circuit. It provides the high input resistance, large transconductance achieved in a
common source amplifier with the superior high frequency response of the common gate
circuit. In our LNA design, we will choose the cascode structure as the topology of our
LNA core circuit. The circuit is shown below.
Figure1. The topology of the core circuit of LNA
2. Choosing Power supply
Since we are using 0.5µm CMOS process technology to manufacture the circuit,
according to the general rules of the 0.5µm process requirement, we choose the 3.3V as
the power supply.
3. Choosing Biasing circuit
There are two ways to bias the MOSFET, one way is to connect the gate of the
MOSFET to a certain voltage source, this can be implemented by using the voltage
divider. Another way is to use the current steering circuit to bias the MOSFET. In this
project, we choose the first method.
Figure2. The Bias circuit for MOSFET1
Biasing circuit for MOSFET1 is showing in Fig.2, we choose a NMOS and
PMOS combination circuit as a voltage divider. Note here we use the NMOS and PMOS
to build the voltage divider to avoid the body effect since the body of PMOS are
connected to the VDD and the body of NMOS are connected to the ground. We made both
PMOS and NMOS working in saturation mode by setting Vgd = 0V. After that, we need
W
W
to design the ( L )3 and ( L )4 to get the output resistance of the MOSFET as the value at
which we expected them to work.
1
W
ID = 2 μn Cox ( L )3 (VGS3 - Vtn )2
1
W
ID = 2 μp Cox ( L )4 (VSG4 + Vtp )2
VGS3 +VSG4 = VDD
VGS3 = Vbias
And we know
W
RDS3=1/[μn Cox ( L )3 (VGS3 -Vtn )]
W
RDS4=1/[μp Cox ( L )4 (VSG4 +Vtp )]
We also know the current
1
ID= R + R
VDD
DS3
DS4
This is the current which the biasing circuit draws from the power. Since we need
to minimize the power of whole LNA, we need to set RDS3 + RDS4 big enough to
minimize the power consumption.
Now we can get the whole topology of our LNA design as the Fig.3
Figture 3. The topology of whole circuit
4.Choosing other parameters
1) Because in our project we choose a very small AC signal (around 1 µV ) as the
simulated antenna output signal to LNA. So we must choose Biasing circuit to bias the
MOSFET1 in a correct quiescent position. The topology choice of biasing circuit and
W
the calculation method of the ( L ) value of the MOSFET is already discussed in the above
analysis. Considering the general situation for NMOS, we choose the initial Vbias as
W
W
0.7V firstly. According to the this value, we can calculate the value ( L )3 and ( L )4
2) We need to use one coupling capacitance C2 in our circuit to couple the AC
signal onto the DC biasing voltage. Since the AC signal is around 960MHz, we wish to
choose the coupling capacitance as bigger as better. But in fact, due to the limitation of
the manufacturing process, usually the capacitance in IC can’t be too big. Here we choose
the value as 6 pF.
3) Designing the Ls using the real part matching condition
4) Designing the L1 using the NF specification
2
1
Noise Figure (NF)
= 1 + 3 g Q2R
m
S
2 1
= 1+3
L1
1+Ls
W
5) Designing Cgs and Hence ( L )1
W
W
for simplicity , we set ( L )1 = ( L )2
6) Using the gain equation to find out C1 and Ld
Ld
1
Voltage Gain Av
= L 1- ω 2 L C
S
c
d 1
7) Check the power total current , voltage gain , noise figure
2. Mixer Design:
Design requirement
The specifications required for the Mixer design were the following:
 RFinput: VRF = 0.001 sin(2*pi*fRFt) V ; fRF = 960 MHz
 LO (positive node): VLO+ = 2+0.2 sin(2*pi*fLOt) V ; fLO = 950 MHz
 LO (negative node): VLO- = 2-0.2 sin(2*pi*fLOt) V ; fLO = 950 MHz
Design Procedure
1. Choosing Circuit Topology:
Mixers are used for frequency conversion and are critical components in modern
radio frequency (RF) systems. A mixer converts RF power at one frequency into power at
another frequency to make signal processing easier and also inexpensive.
Figure 4. Circuit symbol for a mixer
The ideal mixer, represented by figure 4, is a device which multiplies two input
signals. If the inputs are sinusoids, the ideal mixer output is the sum and difference
frequencies given by
Typically, either the sum, or the difference, frequency is removed with a filter after the
mixer.
Several RF mixer topologies can be realized in integrated circuits. Since balanced
mixer designs are more desirable in today’s integrated receiver designs because of its
lower spurious outputs, higher common-mode noise rejection and higher port-to-port
Isolation. So generally we will adopt the balanced type mixers. Typical balanced mixer
topologies are single-balanced mixer(SBM), double balanced or Gilbert cell mixer(DBM),
MICROMIXER, and common gate-common source (CG-CS) or common base-common
emitter (CB-CE) mixer, respectively. In our project, considering the signal coming from
the LNA is a single ended signal, we choose the single balanced active mixer as the
circuit topology of our design.
Figure 5. The circuit topology of the mixer design
2. Choosing the MOSFET parameters and the biasing circuits
For single balanced mixers, signals are taken from both branches, RF feedthrough
from both branches cancel one another. That means in one stage only one of MOSFET2
and MOSFET3 is working in saturation mode, and another one is cut off. At another
stage, both two of these MOSFET will change its work mode. MOSFET1 will always
W
work in saturation mode. So we should carefully choose the ( L ) of every MOSFET and
biasing circuit to make the MOSFET work in the expected mode. The biasing circuit will
use the same structure which we had used in the LNA design , voltage divider.
The RF input varies the drain current of M1, which is biased in the saturation
region. The LO input causes transistors M2, and M3 to act as switches, since both are
biased in the linear region, and small changes in the input voltage (VGS) causes large
changes in current which can be interpreted as on-off cycles.
Simulation Results
1.
LNA
We can see the voltage gain >26dB
We can see the total current =3.82 mA<5mA
We can see the noise figure <3dB
2.
MIXER
We can see the Mixer conversion gain =20Lg(0.002/0.001)=6dB
Amplitude of LO leakage at the IF output is 0.657V, DC offset at the IF output is 2.3e-5.
Amplitude of LO leakage at the RF input is 2e-7V
Conclusion
In this project, we finish the schematic design of LNA and mixer working at
center frequency of 960MHz, then we use the ADS software to simulate our design, most
of the requirement is met.