Download Process Technologies for High-Speed IC Design

Process Technologies for High-Speed IC Design
Dr. Gopal Raghavan, CTO
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Overview
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Technology choices
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Applications
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Reliability
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Inphi Proprietary / Page 6
Technology Choices
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FET technologies
– Silicon
"
CMOS 0.13 µm gate lengths
– Gallium arsenide (GaAs)
"
!
Psedomorphic high electron mobility transistor (pHEMT)
Bipolar technologies
– Indium phosphide (InP)
"
"
"
1.0 µm emitter width
Double heterojunction bipolar transistor (DHBT)
Single heterojunction bipolar transistor (SHBT)
– Silicon germanium (SiGe)
"
"
0.13 µm emitter width
DHBT
– Gallium arsenide (GaAs)
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Inphi Proprietary / Page 7
2.0 µm emitter width
DHBT
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Why Multiple Technologies ?
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Different applications need varying
–
–
–
–
–
–
!
Voltage swing
Power dissipation
Integration / complexity
Speed
Noise levels
Cost
Many of these parameters trade off against
each other
– e.g. high voltage implies lower speed for a given
structure / material
!
Different technologies optimized for
different applications
Inphi Proprietary / Page 8
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FET Technology
Si nMOS
GaAs pHEMT
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Inphi Proprietary / Page 9
Bipolar Technology
Low emitter, base resistance
Planar process = high yield
Passivated surfaces
Low emitter, base resistance
Low yield
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Inphi Proprietary / Page 10
Bipolar Technology (con’t.)
n AlGaAs
n InGaP
p GaAs
p GaAs
n GaAs
n GaAs
n AlInAs
p GaInAs
n GaInAs
n Si
n InP
p SiGe
p GaInAs
n Si
n InP
Si Based
GaAs Based
S
H
B
T
D
H
B
T
InP Based
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Inphi Proprietary / Page 11
InP Technology for High-Speed ICs
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Higher electron velocity in InP
– Thicker base and collector layers compared to
Si, SiGe, and GaAs
"
"
"
Lower capacitance
Lower current density for peak performance
Lower Vbe
ELECTRON VELOCITY
3
Better breakdown
Jc (A/cm2)
100
InP
10
780 mV
220 mV
1
0.1
Si
BJT
GaAs
HBT
0.01
0.0 0.4 0.8 1.2 1.6 2.0
VBE (V)
Inphi Proprietary / Page 12
V (107 CM/S)
"
GaInAs
GaAs
2
1
0
InP
Si
0
5
10
E (kV/cm) electric field
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InP Technology for
High-Speed ICs (con’t.)
!
!
!
!
!
Gold interconnect
Semi-insulating substrate
Low-k dielectric
Backside vias available
Currently 1 µm feature size
– Easily scaled to smaller geometries
– Inexpensive
– Limited number of process steps
!
Limited integration
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Inphi Proprietary / Page 13
High-Speed Circuit Examples
10 Gbps CMOS
1:4 Demux + 4:1 Mux
Back-to-Back
~300 mW
Inphi Proprietary / Page 14
96 GHz InP
Static Divide-by-2
~150 mW
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InP High-Speed Circuit Examples
1:4 Demux
Operation at 80.6 Gbps
Beat Test
13 GHz D flip-flop
~0.3 ps jitter rms
~10 ps rise/fall time
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Inphi Proprietary / Page 15
Complexity / Speed Tradeoff
Transistors
100M
CMOS
10K
SiGe
1K
100
InP
pHEMT
10 GHz
Inphi Proprietary / Page 16
100 GHz
Speed
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Voltage Swing / Speed Tradeoff
!
!
!
!
InP has higher electron velocity and breakdown voltage
than silicon
For same speed, tcoll (Si) < tcoll (InP)
InP devices have higher breakdown for same speed
Alternatively, InP devices are faster for same breakdown
ELECTRON VELOCITY
V (107 CM/S)
3
GaInAs
GaAs
2
1
0
InP
Si
0
5
10
E (kV/cm) Electric Field
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Inphi Proprietary / Page 17
Breakdown Voltage / Speed Tradeoff
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Inphi Proprietary / Page 18
Cost Tradeoffs
$200
SiGe 1
$160
$120
Cost
SiGe 2
pHEMT
$80
$40
InP HBT
$0
1000
10000
100000
1000000
No. of Die (Volume)
Mask cost limited
Inphi Proprietary / Page 19
Yield / wafer size limited
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Device Requirements for
Optical Mach-Zehnder Drivers
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High voltage swing (~7 V p-p, 12.5 Gbps)
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High breakdown voltage ( > 8 V)
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High speed (ft > 100 Ghz)
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Technology choices
– GaAs pHEMT
– GaAs bipolar
– InP DHBT (Inphi choice)
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Inphi Proprietary / Page 20
Technology Comparison
GaAs
pHEMT
GaAs HBT
InP DHBT
Device Speed /
Performance
2
1
4
Power
Dissipation
5
1
4
Die Size
2
4
5
Reliability
4
3
4
External
Components
1
4
4
Gain
1
5
5
1-5 scale, 5 = best
Inphi Proprietary / Page 21
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Reliability
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Process reliability varies from CMOS
(extremely mature) to InP DHBT
(relatively new)
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Foundry evaluation should include
detailed reliability evaluation
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Mature foundry should have reliability
data on actives and passives and design
rules for reliability
!
Much of this information is proprietary
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Inphi Proprietary / Page 22
Conclusions
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Numerous choices for high-speed
process technologies
!
Choose the optimal process for a
particular application
!
In general, the newer the process,
the more time required to get it into
production
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Inphi Proprietary / Page 23
Presenter Biographies
Dr. Gopal Raghavan, CTO. Dr. Gopal Raghavan has over 20 years of
experience in high-speed circuit design and device modeling. From 1982 to
1994, Dr. Raghavan was a senior engineer with Intel Corporation engaged in
CMOS circuit design and process development. Prior to founding Inphi, Dr.
Raghavan was a principal engineer at Conexant designing integrated circuits for
10 Gbps SONET applications. Dr. Raghavan has won several awards, including
the Hughes Hyland Patent Award (1998) and the Ross Tucker Award from
TMS/IEEE (1993). He holds 10 patents and has published more than 30
technical publications. Dr. Raghavan holds M.S. and Ph.D. degrees in electrical
engineering from Stanford University as well as a B. Tech degree in electrical
engineering from the Indian Institute of Technology.
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Inphi Proprietary / Page 61