Download II. General presentation of Voice over IP

An Open Hardware based System on Chip
Architecture for Voice over Internet
N. Izeboudjen, K. Kaci, M. Bengherabi, S. Titri, F. Louiz, L. Sahli, D. Lazib, *N. Idirene
Centre de Développement des Technologies Avancées
Lotissement 20 Août 1956, Baba Hassan, Alger
[email protected]
* Université de Bourgogne, Laboratoire LE2I, UMR-CNRS 5158,
Aile Sciences de l'Ingénieur, BP 4787021078 DIJON Cedex, France
Abstract__ In this paper, we present a System on Chip (SoC)
gateway architecture for Voice over Internet (VoIP). To achieve
our goal, we have adopted the Opencores design concept. The
architecture is mainly based on the OR1200 processor , a debug
unit for debugging purpose, a Direct Memory Access (DMA), a
memory controller two external Flash and SDRAM memories, an
Universal Asynchronous Receiver Transmitter (UART), an
Audio codec for Voice coding a standard MAC/Ethernet and an
internal boot memory. The cores are connected through the
WISHBONE bus interface. The benefit of using the Opencores/
Openhardware methodology is flexibility, reuse and accessibility
of the cores at free cost. The design is done using full
synthesizable Verilog language. The first preliminary results
show that the whole SoC can be implemented in the field
programmable gate array (FPGA) –XC2V1000 circuit which can
integrates up to 1Million of logic gates.
Keywords: SoC, VoIP, Opencores, WISHBONE, OR1200
I.
Most important solutions taking into account the QoS and the
capacity of the gateway were based on DSP circuits. Recently,
and with the advance of the microelectronic technology, it is
possible to integrate a whole system into a single FPGA
circuit [2-4]. Thus, a new field which integrate VOIP
solutions’ into System on chip (SoC) based FPGA circuits is
emerging. In this paper, we propose SoC architecture for
VoIP application.
The originality of our approach is the adoption of the
Opencore design concept [5] for the VOIP implementation.
The benefit of using such a methodology is flexibility; reuse
and accessibility of the IP cores (intellectual property), rapid
SoC prototyping and the entire core component are available
at free cost. This can also reduces the whole VOIP cost.
Section II, gives a general presentation of VoIP. Section III,
deals with the Proposed VoIP architecture. In Section IV, the
primary synthesis and implementation results are given and
finally a conclusion.
INTRODU CTION
Today, with the explosion of the internet and its IP network
protocol, communication traffic is mainly dominated by data
traffic, unlike in the past it was dominated by telephony driven
voice. This phenomenon has lead to the emergence of voice
over data (VOIP) equipment that can carry voice, data and
also video on a single network.
The idea behind VOIP is to use the IP network for voice
services as an alternative to the public switched
telecommunication network (PSTN). The advantages over
traditional telephony include:
 Lower costs per call, especially for long distance
calls
 Lower infrastructure cost compared to the PSTN.
According to Probe Research the market for VOIP equipment
will increase from $1.2 billion in 2000 to $10 billion in 2005
[1]. Each specialised paper that appears shows that VOIP will
have an important place in the telephony market, especially in
enterprise and public domain areas. The main challenges in
designing a VOIP application are the quality of service (QoS)
and the capacity of the gateways. Factors affecting the QoS
are line noise, echo, the voice coder used, the talker overlap
and the Jitter factor. The capacity of the gateway is related to
the number of lines that can be supported in an enterprise
environment.
II. GENERAL PRESENTATION OF VOICE OVER IP
Voice over IP had its starts in February 1995 when a
manufacturer started marketing software that enabled a
conventional computer equipped with a sound card,
microphone and loudspeaker to phone another PC via the
internet. Initially, the voice quality achieved was
unsatisfactory but the principle behind it drew a great attention
of public, thus the first area of application for VoIP: PC-to-PC
was established. Subsequent to this introduction a number of
manufacturers concentrated on developing similar software
and consequently raised the question of compatibility among
different
systems.
In
1996,
the
International
Telecommunication Union (ITU-T) responded by developing
the H.323 standard. Afterwards, the focus was the possibility
of placing long distance calls using voice over IP known as
toll bypass; however this required setting up a connection
between the telephone network (PSTN) and the data network,
a task performed by so called Gateways [6]. The result has
been additional application for VoIP including:
 PC-to-phone,
 Phone-to-PC and, when two gateways are used,
 Phone- to - phone communication.
This last option was the catalyst in the establishment of a new
provider group named ITSP (Internet Telephone Service
Provider) that permits telephony over IP within the provider
network using prepaid cards. To date, VoIP refers to the
ability to transfer data and voice and also video on the single
network. Figure 1 illustrates the basic operating principle of
VoIP.
A/D
Converter
IP Network
LAN, WAN
De-compression
Echo
suppression
IP
UDP
Compression
G.7xx
RTP
G.7xx
D/A
Converter
Figure 1. Operating principle of VoIP
 The human voice initially generates an analog signal.
This signal is converted into a bit stream by an
Analog/Digital (A/D) converter. And then submitted to a
multiple compression process. There are various
techniques to do this. The most popular ones are
standardized in the ITU-T G-series. The most commonly
used codecs in VOIP systems are: G.711 PCM [7], G.726
ADPCM [7], G.728 LD-CELP [8], and G. 729/G.729a
CS-ACELP [9-10]. PCM and ADPCM belong to the
family of so called waveform codec. These codecs simply
analyze the input signal without any knowledge of the
source. Most of these codecs work in time domain, like
PCM. These codecs offer high quality speech at a low
computational complexity. But if we try to get the bit rate
below 16 kbps the quality decreases tremendously. To get
the bit rate really down another approach is necessary.
Source coders need to know the characteristics about the
input being coded. Out of these characteristics a model of
the source is made. When an input is encoded the source
coder tries to extract the exact parameters of this model
from the input. Then these parameters and a two state
excitation is transmitted. These codecs can simply
transport the pure informational content of a speech
sample and not the voice itself. Their big advantage is that
they operate with bit rates as low as 2.4 kbit/s. Hybrid
codecs try to combine the advantages of waveform
codecs, which is good quality, with the advantages of the
source codecs that is low bit rate. To get the best
excitation signal all possible waveforms are tested and the
one with the least error is then chosen. This involves a
very high computational complexity for every analysis
frame. The low bit rate codecs usually involve a high
computational complexity and a delay and the waveform
codecs have the advantage of low delay and excellent
quality. In Table 1 there is an overview of the quality of
the different codecs according to the Mean Opinion
Score. This score is derived from a large number of
listeners who rated the quality of the played sample with a
score from excellent (5) to bad (1). It should be
understood that the various coding methods vary in the
levels of complexity, delay characteristics and
quality. The following table shows the relevant
characteristics of the most common coding algorithms.
The evaluation of speech quality is of critical importance
in any VOIP application, mainly because quality is a key
determinant of customer satisfaction. Traditionally, the
only way to measure the perception of quality of a speech
signal was through the use of subjective testing, i.e., a
group of qualified listeners are asked to score the speech
they just heard according to a scale from 1 to 5. The most
reliable method of speech quality assessment but it is
highly unsuitable for online monitoring applications and
is also very expensive and time consuming. Due to these
reasons, models were developed to identify audible
distortions through an objective process based on human
perception. Objective methods can be implemented by
computer programs and can be used in real time
monitoring of speech quality. Algorithms for objective
measurement of speech quality assessment have been
implemented and the International Telecommunications
Union has promulgated ITU-T P.862 standard, also
known as Perceptual Evaluation of Speech Quality
(PESQ), as its state of-the-art algorithm.

The Voice frames are integrated into a voice packet.
First RTP (Real time protocol) packet with a 12
address byte header is created. Then an 8-byte UDP
packet with the source and destination address is
added. Finally, a 20 byte IP header containing source
and destination gateway IP address is added.
The packet is sent through the internet where routers
ands switches examine the destination address
When the destination receives the packet, the packet
goes through the reverse process for playback.


Table1. Characteristics of the most coding algorithms
Coding algorithm
G.711 PCM
Bandwith
(Kbps)
Algorithmic
Delay (ms)
Complexity
(MIPS)
MOS
64
0.125
0
4..3
G.726
ADPCM
16-40
0.125
6..5
2.04.3
G.728
LD-CELP
16
0.625
37.5
4.1
G.729 CSACELP
8
10
17
3.4
III. THE PROPOSED VOIP ARCHITECTURE
Figure 5 shows the proposed gateway architecture which is
mainly based on the OR1200 processor MASTER, a debug
unit for debugging purpose, a Direct Memory Access (DMA),
a memory controller that controls an external Flash and
SDRAM memory, an Universal Asynchronous Receiver
Transmitter (UART), an Audio codec for Voice coding, a
standard Ethernet that transmit voice packets over The internet
and an internal boot memory. All the cores are connected
through the WISHBONE bus interface. In the following an
architecture description of each IP core of the VOIP gateway
is addressed.
timer, a programmable interrupt controller and a power
management support.
JTAG
ROM
Boot
DMA
Debug
OR1200
Interface
32 bit RISC
WISHBONE Bus System & Arbiter
Memory
Controller
UART
AUDIO
16550
Codec
Console interface
FLASH
Audio serial
interface
10/100
Ethernet
MAC/PHY
Physique interface
SDRAM
Figure 3. The VoIP gateway architecture
As shown in Figure 4, the WISHBONE bus interface uses a
Architecture
MASTER/SLAVE
architecture. Some signals are specific to
the master core, others to the slave one and there are common
signals shared between the master and the slave. The
MASTER interface could be on a microprocessor IP core, and
the SLAVE interface could be on a serial I/O port. In this
architecture the WISHBONE uses the shared bus
interconnection schema, thus a MASTER initiates a bus cycle
to a target SLAVE. The target SLAVE then participates in one
or more bus cycles with the MASTER. An arbiter (not shown
in the Figure) determines when a MASTER may gain access
to the shared bus. The main advantage to this technique is that
shared interconnection systems are relatively compact.
Generally, it requires fewer logic gates and routing resources
than other configurations (cross bar switch).
Figure 5. OR1200 Architecture
The DMA core provides transfer between two WISHBONE
interfaces. Transfer can also be performed on the same
WISHBONE interface.
Figure 6 illustrates the core
architecture overview. It consists of 3 main blocks: Two
WISHBONE interfaces, a DMA engine and pass through
logic. The DMA engine is up a 31 canal that supports transfer
between two interfaces as well as transfer on the same
interface. The Pass through block performs the bridging
operation between two WISHBONE interfaces.
WISHBONE 0
DMA Engine
Pass- through
WISHBONE 1
Figure 6. The DMA core architecture
Figure 4. WISHBONE interconnect schema
The OR1200 (Figure 5) core is a 32-bit scalar RISC with
Harvard micro-architecture, 5 stage integer pipeline, virtual
memory support (MMU). It includes debug unit for real-time
debugging easing software development, a high resolution tick
The memory controller supports a variety of memory devices;
flexible timing and predefined system start up from a Flash or
ROM memory. Figure 7 illustrates the overall architecture of
the core. It consists of a 32 bit bus WISHBONE interface, a
power-on configuration, a refresh controller, an open bank and
row tracking, an address MUX and Counter, a data latch
packet and parity, a memory timing controller a memory
interface and a configuration and status register. The poweron block latches the value of the memory data bus during
reset. The value read, determines initial configuration of the
Memory Controller. The refresh controller block is
responsible for generating refresh cycle requests for the
attached SDRAMS. The open bank and row tracking block
remembers which bank and which row within a bank is
already open. This feature allows for very fast access to
already open rows within a bank
and row. The address MUX and counter bank block is
responsible for generation of proper addresses. The data latch
packet and parity block is responsible for the data bus
connections between the Memory bus and the WISHBONE
bus. The memory timing controller is responsible for memory
timing and control. It performs the appropriate cycles to
access various memories. The Memory Interface block
provides simple synchronization for IOs. All outputs and
inputs are registered at the rising edge of the Memory Clock.
The Memory Controller utilizes two clocks: the main
wishbone clock; and the memory clock. For optimal
operations, the memory clock must be derived from the
WISHBONE clock by dividing the WISHBONE clock by two
and phase synchronizing it to the WISHBONE clock. The
configuration and status block holds all the registers in the
Memory Controller and decode the chip select signal.
connects the Ethernet core to the RISC and to external
memory.
Figure 8. MAC/ Ethernet architecture
The UART is very similar to the standard 16550 UART chip.
Figure 9 shows the bloc diagram of the UART. It consists of a
Tx unit, an Rx unit, an interrupt bloc, a modem logic bloc and
a WISHBONE interface bloc. The Tx unit converts the
parallel data into serial form to transmit them to the host. The
data from the OR1200 processor or the DMA core interface
are stored in buffer registers, converted into a serial form at
the shift register and transmitted. The Rx unit process the
serial data received from SRX-I. The WISHBONE interface
can be 32 bits or 8 bit bus (selectable).
Divisor
Latch Registers
Baud
Generator
Line Status
Register
Line Control
Register
Figure 7. Memory controller architecture
The Ethernet core is a 10/100 Media Access Controller MAC).
It is designed to run according the IEEE 802.3 specification tat
defines the 10 Mbps and 100Mbps Ethernet respectively.
Figure 8 shows the general architecture of the IP core. It
consists of several building blocks: a Tx module an RX
module, a control module, a management block and a
WISHBONE interface. The TX and RX modules provide full
transmit and receive functionality. CRC generators are
incorporated in both modules for error detection purposes. The
control module provides full duplex flow control, according to
the IEEE 802.3u standard. Flow control is achieved by
transferring the PAUSE control frames between the
communicating stations. The management module provides
the standard IEEE 802.3 Media Independent Interface (MII)
that defines the connection between the PHY and the link
layers. Using this interface, the device connected can force
PHY to run at 10 Mbps versus 100 Mbps or configure it to run
at full versus half duplex mode. The WISHBONE interface
W
I
S
H
B
O
N
E
Receive
r FIFO
Receive
r Shift
registar
SRX_I
Transmi
t FIFO
Transmi
t Shift
registar
STX_O
FiFo Control
Register
Interrupt ID
Register
Interrupt Enable
Register
Modem Status
Register
Interrup
t
Logic
INT_O
RTS_O
Modem
Signal
Logic
CTS_I
Modem Control
Register
Figure 9. The core UART
The Audio Codecarchitecture
core digitizes the analog voice from the
headset, group data into packets and then transmits it across
the network (See section II). We consider, the G.711 PCM,
G.726 ADPCM, G.728 LD-CELP, and G. 729/G.729a CSACELP. The programs codes for the different Codecs are
available free from the ITU-T. They can be easily adapted to
our application. This module is being implemented in software
under the Linux exploitation system.
performances in Internet Network area: Local Area Network
(LAN) or Wide Area Network (WAN).
IV. SYNTHESIS AND IMPLEMENTATION RESULTS
Although most of the HDL cores codes are available freely for
simulation and synthesis from Opencores, the most difficult
task in designing SoC hardware is how to write an HDL code
that integrates all the SoC components codes and how these
components communicate each with other through the
WISHBONE interface bus. To do this, the first step is to
define the MASTER from the SLAVE components in the
architecture. The OR1200 processor is the MASTER for all
components. The memory controller is configured as slave
compared to the OR1200 and a MASTER to the SDRAM and
Flash memory. The UART is configured as a slave to the
OR1200. The DMA is used for direct access and in some
cases to liberate the OR1200 when it is busy so it is
configured as a MASTER.
At this time, we have integrated the OR1200 processor, the
debug unit, the Memory controller and the 16550 UART core.
We synthesized the architecture using the Leonardo Spectrum
[11] professional synthesis tool from Mentor Graphics. The
whole Architecture is mapped into the XC2V1000fg465
FPGA circuit. Table 2 shows the resulting synthesis results.
Mainly, the SoC occupies 74% of the FPGA surface and 41%
of inputs/output.
Table 2. Synthesis results
Design Information
area -pr b -k 4 -c 100 -tx off -o VoIP_map.ncd VoIP.ngd
VoIP.pcf
Target Device : x2v1000
Target Package : fg456
Target Speed : -4
Design Summary
-------------Number of occupied Slices:
3,812 out of 5,120 74%
Total Number 4 input LUTs:
6,544 out of 10,240 63%
Number used for Dual Port RAMs: 32
Number of bonded IOBs:
136 out of 324 41%
IOB Flip Flops:
116
Number of Block RAMs: 12 out of 40 30%
Number of MULT18X18s: 4 out of 40 10%
Number of GCLKs:
4 out of 16 25%
Number of DCMs:
1 out of
8 12%
After synthesis, we use the ISE 6.1 place and root tools [12]
for implementation. Figure 10 shows the layout of the circuit.
V. CONCLUSION
The first primary results show that the whole VOIP gateway
architecture can be mapped into an FPGA circuit. There is still
much effort to do. The next step is to integrate the
MAC/Ethernet and the DMA cores into the FPGA. Following
to this we have to consider a platform for different Codec
algorithms selection and then to test the VoIP gateway
Figure10. Final FPGA Layout
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[2] Jim Benek, “ Add Internet Connectivity with SPARTANII PGA
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[3] A. Tavonlaris and all, “Accelerating VoIP applications using
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[4] Moors, Roland, “Voice over IP standards and technics”
www.comconsul-akademie.de
[5] Opencores project site http://www.opencores.com
[6] ITU-T Software Tool Library 2000 user’s manual Geneva,
December 2000.
[7] J.H. Chen, “High Quality 16 kb/s Speech Coding with a One
Way Delay less than 2 ms”, Proc. IEEE Int. Conf. on Acoust . Speech
Signal Processing, Apr. 1990, pp. 453-456.
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using conjugate structure algebraic code excited linear prediction
(CS-ACELP), Mar. 1996.
[9] R. Salami, C. Laflamme, J-P. Adoul, A. kataoka, S. Hayashi, T.
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[11] Mentor graphics manual ,http://www.mentorgraphics.com
[12] ISE 6.1 user manual , www.xilinx.com