Download KV5x High Speed ADC Design Reference Manual

Freescale Semiconductor, Inc.
Design Reference Manual
Document Number: DRM168
Rev. 0, 03/2016
KV5x High-Speed ADC Design Reference
Manual
1. Introduction
This document provides the necessary design
considerations and recommendations to obtain the best
possible performance from the high-speed ADC
(HSADC) on the KV5x devices. It is not intended to be
a “rule-book” or to define concrete requirements when
designing and laying out the board design. It is meant to
help the board or system designers understand what is
important for this particular ADC (the 12-bit high-speed
ADC) on KV5x and provide recommendations to design
a board for maximum ADC performance. Ignoring these
recommendations completely could result in poor ADC
performance, including excessive missing codes.
The HSADC is a 12-bit Successive Approximation
Register ADC (SAR ADC) that operates at a rate of up
to 5 MSPs. Achieving this sampling and conversion rate
requires a relatively high clock frequency. As designed,
the total conversion time for one conversion is a
minimum of 14 ADC clock cycles, but a minimum of
15 ADC clock cycles is recommended for performance
reasons. Assuming 15 ADC clock cycles per
conversion, to achieve 5 MSPs, a clock speed of 75
MHz is required. At this relatively high clock
frequency, noise can easily be injected into the system,
if the circuits are not designed properly. This document
identifies what is important when designing an ADC
input circuitry.
© 2016 Freescale Semiconductor, Inc. All rights reserved.
Contents
1.
2.
3.
4.
5.
6.
7.
8.
Introduction........................................................................ 1
HSADC Design and Considerations .................................. 2
Layout Guidelines .............................................................. 2
General Guidelines............................................................. 2
4.1.
Component placement ............................................ 2
4.2.
Signal routing.......................................................... 3
Power Supply Guidelines (VDDA and VREF) .................. 5
Input Signal Circuit ............................................................ 8
Conclusion ......................................................................... 9
Revision History ................................................................ 9
General Guidelines
2. HSADC Design and Considerations
Before understanding what is important in the circuit design, the users should understand the design of
the ADC. A SAR ADC works by comparing the sampled signal with the output of a reference DAC
(either single-ended or differential DAC depending on the mode of the converter). The output of the
DAC is varied until the reference voltage is equal to the sampled signal. During this process, the
sampled charge is changed by known amounts until the voltage on the input DAC matches that on the
reference DAC. Therefore, transistors switch different capacitor banks in and out of the circuit as the
sampled charge is changed.
The key requirements to maximize the performance of the HSADC on KV5x are as follows:
•
For most ADCs, the supply voltage (VDDA for KV5x) must be stable, which may require proper
filtering, and sourced from a low output impedance supply.
•
The reference voltage, to which the sampled signal is compared to, must be stable. This requires
proper filtering and a low impedance source.
•
The sampled signal must be properly filtered so that any noises from the outside circuits of the
board or external environment do not affect the measurements.
If neglected, these three items may significantly affect the dynamic or linear performance of the
HSADC.
3. Layout Guidelines
When designing any board, the designer must use solid engineering knowledge to decide which
guidelines to use and where or how to use the available guidelines. No set of guidelines is applicable to
all possible use cases.
4. General Guidelines
Some general guidelines for the board layout are not specific to KV5x, but are particularly important.
When designing a circuit, the designer must visualize the signal current paths and locate antennas and
crosstalk paths and minimize them. Component placement and signal routing determines the success of
the circuit design.
4.1. Component placement
Well designed boards follow this layout process:
1. Place connectors and special hardware.
Connectors should be along one edge of the PCB when possible and digital circuits should not be
between connectors. Be cautious when using this guideline as sometimes it may be better to put
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General Guidelines
connectors on more than one edge, if that significantly cleans up the routing and allows
separation of digital and analog circuits. In addition, use common sense when placing
components.
2. Place the drivers and filters for higher speed I/O to connectors as close as possible.
3. Place the low-speed I/O and power components.
4. Place the analog circuits and isolate them from the digital circuitry.
5. Place the other PCB interface circuits, including debug headers.
6. Place the digital circuits.
Figure 1. Compliments of Rick Hartley, Consultant
4.2. Signal routing
If the components are well placed, signal routing is relatively easy. When routing the signals, make sure
that each signal has a proper return path. This is where visualizing the signal current paths and
minimizing the effect of antennas and crosstalk paths becomes relevant.
Imagine three signal traces routed side-by-side with no return path near them. The magnetic field of
these traces would look like the following figure.
KV5x High-Speed ADC Design Reference Manual, Rev. 0, 03/2016
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General Guidelines
Figure 2. Magnetic field of three signal traces
The intersecting magnetic fields indicate that there is crosstalk between the signals. A better formed
signal routing is as shown in the following figure.
Figure 3. Better formed signal routing
In Figure 3, the middle trace is a ground trace, which is a return path. This routing configuration is
sometimes referred to as a “routed triplet”. The magnetic fields do not intersect. This indicates that there
is no crosstalk between the signals. A good rule of thumb to prevent crosstalk is that a signal should be
one dielectric away from its return path.
A ground plane can have the same effect of reducing crosstalk as a routed triplet. It is important to note
that some crosstalk may still be present depending on the distance between the traces and the
frequencies that are transmitted through the traces, but the closer the ground plane is to the traces, the
stronger the electric field is to the ground instead of the traces next to it. The following figure illustrates
this effect.
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Power Supply Guidelines (VDDA and VREF)
Figure 4. Effect between the ground plane distance and the electric field
Remember that a signal should be one dielectric away from its return.
5. Power Supply Guidelines (VDDA and VREF)
The guidelines for VDDA and VREF are grouped together because their needs are very similar. They
are both DC sources that need to be kept stable and the AC impedance between the board connector and
the pins of the MCU should be kept low. Managing the AC impedance ensures that the voltage at the pin
of the MCU is as close to the desired voltage as possible and is less susceptible to noise injection from
outside sources. To achieve these goals, consider the following:
•
Use a ground plane.
The use of a ground plane helps control the return paths of the signals on the circuit board.
Almost every set of circuit design guidelines recommends the use of a ground plane. When
laying out the ground plane, consider these recommendations:
o Do not split Analog Ground (AGND) and Digital Ground (GND).
There should only be one ground for both AGND and GND. It is still recommended to
“localize” the grounds. In other words, the digital circuits should be kept separated from
the analog circuits as much as possible.
KV5x High-Speed ADC Design Reference Manual, Rev. 0, 03/2016
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Power Supply Guidelines (VDDA and VREF)
Figure 5. Do not split AGND and GND
Two ground planes can be on two different layers, for example, a ground plane on layer 2
and a ground plane on layer 5. However, these planes should be tied together with vias.
They should also follow the best stitching practices to make sure that the charge on these
planes is as evenly distributed as possible.
o Do not split the plane.
The ground plane should be one contiguous plane. Breaks in the plane are discouraged,
because they only create the possibility of increasing the length of the return path
(increasing the impedance to ground) and creating what is essentially a loop antenna. For
a more in-depth discussion on this subject, see EDN article: Successful PCB grounding
with mixed-signal chips – Part2: Design to minimize signal-path crosstalk, September 10,
2012.
Figure 6. Do not split the plane
Multiple PCB layers can be a ground layer. When doing this, you must properly “stitch”
these layers together. Failing to properly stitch these layers together is effectively
creating the situation shown in Figure 6.
o Use a mini-plane under the MCU.
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Power Supply Guidelines (VDDA and VREF)
The use of a mini-plane under LQFP packages is also recommended. This layout
technique is not possible with BGA packages.
Figure 7. Use a mini-plane under the MCU
•
Use bulk capacitors and bypass capacitors close to the MCU pins.
Bypass capacitors are the reservoir for the instantaneous switching current required by the MCU
and filter out noise at the pins of the MCU. The capacitors should be physically close to the pins.
The further away they are, the less effective they are. The bulk capacitors act as a reservoir for
the downstream bypass capacitors. Not using bulk capacitors could result in undesired voltage
drops on the supply pins and decreased HSADC performance.
Amount of capacitance is dependent on the length of the traces to the power supplies and the
geometry of the board. Therefore, it is not possible to give a good quantifiable suggestion.
However, the longer the trace length to the power supply, the more the bypass capacitors are
relied on and therefore, requiring more capacitance at the pin. Therefore, choose the largest
nominal capacitance available in a given package size.
•
Use filter capacitors at the power supply entry point to the board.
The use of capacitors at the board’s power entry points helps to filter out external noise. If the
noise is introduced from an external source from the beginning, it is very difficult to filter it out
later in the circuit.
•
Minimize the impedance from the power source to the MCU.
A good general rule is to minimize the impedance from the power sources to the MCU. The
VREF supply should not be overlooked in this process as this supply can be sensitive to noise
and the injection of noise or ringing in this supply can be the cause of missing codes or other
performance defects. The best way to minimize the impedance is to minimize the trace length
from the power supply to the MCU supply pins.
If VREFH is not the same voltage as VDDA, source it from a precision regulator (make sure to
follow the design regulations of your chosen regulator) and still use the bypass capacitors as
close to the pin as possible (for VDDA as well).
KV5x High-Speed ADC Design Reference Manual, Rev. 0, 03/2016
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Input Signal Circuit
6. Input Signal Circuit
It is very difficult to create a generic guideline for an input circuit that works effectively in every
situation. It is recommended to properly filter and condition your input circuitry and/or use buffer
circuitry. A good buffer circuit should minimize the impedance seen by the MCU pins. A low
impedance instrumentation amplifier is a good buffer to use for high resolution and high performance
HSADC operation. When choosing and designing a buffer circuit, ensure to consider the AC impedance
and minimize the length to the MCU.
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Revision History
7. Conclusion
When designing a circuit board for optimal HSADC performance, consider the following
recommendations:
•
Stable and properly filtered supply voltages sourced from low impedance supplies
•
Stable and properly filtered reference voltage
•
Input signal filtering or buffering
•
Keep analog signal routing and circuits away from digital signals and circuits
Neglecting these items may result in poor ADC performance, including excessive missing codes.
To achieve these items, it is recommended to use the proper ground planes, bulk and bypass capacitors,
implement proper signal routing (remember to visualize the return path circuits and minimize the effects
of antennas and crosstalk paths), and implement a buffer or filtering circuit that meets the needs of the
signals to be sampled.
8. Revision History
Table 1. Revision history
Revision number
Date
Substantive changes
0
03/2016
Initial release
KV5x High-Speed ADC Design Reference Manual, Rev. 0, 03/2016
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© 2016 Freescale Semiconductor, Inc.
Document Number: DRM168
Rev. 0
03/2016