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國 立 交 通 大 學 電機與控制工程學系 碩士論文 交換電容式積分器 之運算放大器增益補償的設計 Design of an Op-Amp Gain Compensator for Switched-Capacitor Integrators 研 究 生 : 許皓淵 指導教授 : 鄭木火 博士 中華民國九十七年七月 交換電容式積分器 之運算放大器增益補償的設計 Design of an Op-Amp Gain Compensator for Switched-Capacitor Integrators 研 究 生 : 許皓淵 指導教授 : 鄭木火 博士 Student : Hao-Yuan Hsu Advisor : Dr. Mu-Huo Cheng 國立交通大學 電機與控制工程學系 碩士論文 A Thesis Submitted to Department of Electrical and Control Engineering College of Electrical Engineering National Chiao Tung University in Partial Fulfillment of the Requirements for the Degree of Master in Electrical and Control Engineering July 2008 Hsinchu, Taiwan, Republic of China 中華民國九十七年七月 交換電容式積分器 之運算放大器增益補償的設計 研究生: 許皓淵 指導教授: 鄭木火 博士 國立交通大學電機與控制工程學系 摘要 在類比系統中, 切換電容積分器為具有重要功能的電路。 切換電容積分器包含一運算放大 器。 運算放大器的非理想特性, 例如有限增益, 有限頻寬以及輸入偏移將會降低積分器的效能。 舉例來說, 運算放大器之有限增益將會使離散時間積分器的極點偏離理想位置 z=1, 造成有限 的直流增益及相位誤差。 這個影響顯著地降低了三角積分調變器之 MASH 架構的性能, 因為 對雜訊修整濾波器而言直流值上不再有一零點。 一直接的方法為設計運算放大器有非常大的增 益, 但是以現在的技術要達到高增益是非常複雜以及幾乎不可能。 在本論文中我們專注於有限 增益運算放大器對切換電容積分器的影響, 並且設計一可以降低因運算放大器有限增益所造成 在積分器之轉移函數上誤差的新型切換電容積分器。 因此, 這經過設計的積分器可以等效增加 運算放大器的增益, 以及改善其在應用上的效能。 此新架構是以相關雙取樣的方法及利用回授運算放大器被提出。 我們首先推導其轉移函數 並使用 MATLAB 計算因運算放大器有限增益造成的誤差。 其性能將與現有的電路做比較。 接 著, 我們使用 TSMC 0.35 微米互補式金氧半的製程來設計, 以及 HSPICE 來模擬電路在數個頻 率之頻率響應。 預先模擬與佈局後模擬的結果接近相同, 並且與原始設計規格相符。 最後畫出電 路佈局, 晶片大小大約是240 × 235µm2 。 關鍵詞: 相關雙取樣, 交換電容式積分器, 有限增益 i Design of an Op-Amp Gain Compensator for Switched-Capacitor Integrators Student: Hao-Yuan Hsu Advisor: Dr. Mu-Huo Cheng Institute of Electrical and Control Engineering National Chiao-Tung University Abstract The Switched Capacitor(SC) integrator is an important functional circuit block in the analog systems. A SC integrator contains an operational amplifier. The non-idealities of the operational amplifier, such as the finite gain, the finite bandwidth, and the input offset will degrade the performance of the integrator. For example, the finite-gain of the operational amplifier will make the pole of discrete-time integrator deviate from the ideal position z = 1 yielding a DC finite gain and phase error in the SC integrator. This effect degrades significantly the performance of delta sigma modulators via the MASH structure, because the noise-shaping filter has no longer a zero at DC. One direct approach is to design an op-amp with extremely high gain, but it is complicated and nearly impossible via the present technology. In this thesis, we focus on the effect of finite-gain op-amp in SC integrators, and design a new SC integrator circuit which can reduce the error in the integrator transfer characteristic due to the finite-gain of the op-amp. Hence, the designed integrator enhances equivalently the op-amp finite gain, and improves the performance in applications. The new topology is proposed using the feedback op-amp and the correlated double sampling (CDS) technique. We first derive the transfer function and use MATLAB to evaluate the errors arisen from the effect of finite-gain in op-amp. The performances of proposed circuit and other existing circuits are compared. Then, we design the circuit using TSMC 0.35µm CMOS technology, and simulate the circuit frequency responses at several frequencies via HSPICE. The pre-sim or post-sim simulation results are approximately identical, and conform to the original design specifications. Finally, the layout is drawn and the chip size is about 240 × 235µm2. Keywords: CDS, SC Integrator, Finite-Gain ii 誌謝 在這短暫的兩年研究所生活, 我要特別感謝鄭木火教授, 由於老師的指導, 使得此論文能順 利完成。 老師在治學態度上的嚴謹細心, 使我在學識上獲益良多。 因此, 在本論文付梓之際, 對 於辛勤傳道並耐心授業的老師致上最誠摯的謝意。 在口試期間, 承蒙口試委員蘇朝琴教授、 莊正教授以及方維倫教授撥冗指導並提供許多寶 貴意見, 使此論文能更臻於完善, 在此也誠摯地感謝你們的辛勞。 同時, 我要感謝 Lab914 同仁們。 感謝已畢業的學長衍禎與嘉華的提攜與照顧。 實驗室一起 學習的夥伴宏楊、 嘉明、 志全、 立中與英哲, 在課業上的砥礪互勉以及生活中的鼓勵和幫忙, 都 成為我求學生涯中最好的助力。 也感謝學弟啟仁、 明華與建男, 因為你們的幫忙, 讓我能更專心 於研究上。 最後, 我要特別感謝我的家人, 尤其是我的父母親, 因為你們長久以來的支持和包容體諒, 使我能順利完成學業。 僅以此小小的成果, 呈現給我的親朋好友, 並感謝所有曾幫助過我的人。 iii Contents ABSTRACT IN CHINESE i ABSTRACT IN ENGLISH ii 誌謝 iii Contents iv List of Figures vi List of Tables x 1 Introduction 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 An Overview of Integrator 5 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Switch Capacitor Integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 Continuous time Integrator . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.2 Switched Capacitor Integrator . . . . . . . . . . . . . . . . . . . . . . 8 2.2.3 Non-ideal Effects of Switched Capacitor Integrator . . . . . . . . . . . 11 2.3 Double-Sampled Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 The Gain-Compensated SC Integrators 3.1 3.2 20 SC Integrator With No Compensation . . . . . . . . . . . . . . . . . . . . . . 20 3.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.2 Conventional SC Integrator . . . . . . . . . . . . . . . . . . . . . . . . 20 Existed Gain-Compensated Integrators . . . . . . . . . . . . . . . . . . . . . . 24 3.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2.2 Single-Sampled Gain-Compensated Integrator . . . . . . . . . . . . . 25 iv 3.2.3 Double-Sampled Gain-Compensated Integrator . . . . . . . . . . . . . 3.2.4 The Modification of A Double-Sampled Gain-Compensated SC Inte- 32 grators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3 A New Single-Sampled Gain-Compensated SC Integrator . . . . . . . . . . . . 45 3.4 Simulation And Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.4.1 Operational Amplifier And Common Mode Feedback . . . . . . . . . . 51 3.4.2 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.4.3 Simulations Of A New Single-End Gain-Compensated Integrator . . . 60 4 Conclusion 67 bibliography 68 v List of Figures 1.1 Block diagram of delta-sigma modulator with a 1-1 MASH structure . . . . . . 2 1.2 SNR variations with amplitude for a 1-1 MASH structure . . . . . . . . . . . . 4 1.3 SNR variations with amplitude for a 1-1 MASH structure and a comparison between conventional and gain-compensated integrator . . . . . . . . . . . . . 4 2.1 CT non-inverting integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 CT inverting integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Magnitude and phase response for CT integrator . . . . . . . . . . . . . . . . . 7 2.4 Magnitude and phase response for inverting CT integrator when A(0) and UGB are finite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 7 (a) Switched capacitor resistor (b) and the equivalent circuit (c) and the clock signal with the equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 (a) Negative and (b) positive switched capacitor circuit . . . . . . . . . . . . . 9 2.7 (a) Inverting and (b) non-inverting SC integrator that are insensitive to parasitic capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.8 Magnitude response of CT and DT non-inverting integrator . . . . . . . . . . . 10 2.9 Phase response of CT and DT non-inverting integrator . . . . . . . . . . . . . 10 2.10 Small-signal models of (a) sampling (b) integrating non-inverting SC integrator [2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.11 SC integrator during integration phase . . . . . . . . . . . . . . . . . . . . . . 12 2.12 Feedback model consisting of a feedforward term d(s), a feedback term β(s), an amplifier AOL (s), and an input scaler γ(s) [8] . . . . . . . . . . . . . . . . 13 2.13 Equivalent circuits for (a) γ(s) (b) β(s) for an ideal SC integrator [8] . . . . . . 13 2.14 Op-amp with offset voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.15 Inverting SC integrator with offset error . . . . . . . . . . . . . . . . . . . . . 15 2.16 SC integrator with offset error at (a) sampling phase (b) integration phase . . . 15 2.17 Simple configuration using an NMOS switch to show charge injection [1] . . . 16 vi 2.18 Double-sampled SC integrator . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.19 A first-order double-sampled delta sigma modulator [7] . . . . . . . . . . . . . 18 2.20 A first-order double-sampled modulator using additive-error switching [7] . . . 18 3.1 (a) Non-inverting and (b) Inverting SC integrator . . . . . . . . . . . . . . . . 20 3.2 Non-inverting SC integrator during (a) φ1 and (b) φ2 . . . . . . . . . . . . . . 21 3.3 Inverting SC integrator during (a) φ1 and (b) φ2 . . . . . . . . . . . . . . . . . 21 3.4 Non-inverting double-sampled SC integrator . . . . . . . . . . . . . . . . . . . 22 3.5 Non-inverting double-sampled SC integrator during (a) φ1 and (b) φ2 . . . . . . 23 3.6 Non-inverting double-sampled SC integrator with two integration capacitors . . 23 3.7 Non-inverting double-sampled SC integrator with two integration capacitors during (a) φ1 and (b) φ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 Gain-compensated SC integrator with limit in input [12] . . . . . . . . . . . . 25 3.9 The SC integrator during (a) phase2 and (b) phase1 . . . . . . . . . . . . . . . 26 3.10 Gain-compensated SC integrator with no limitation for input signal [13] . . . . 27 3.11 The SC integrator during phase (a) φ1 and (b) φ2 . . . . . . . . . . . . . . . . 28 3.12 The frequency response of the macro model op-amp with 40dB magnitude . . . 30 3.13 The output voltage of the SC integrator with no gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=40dB . . . . . . . . . . . . 30 3.14 The output voltage of the SC integrator with gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=40dB . . . . . . . . . . . . . . . . 31 3.15 The output voltage of the SC integrator with no gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=80dB . . . . . . . . . . . . 31 3.16 Double-sampled and gain-compensated SC integrator with no limit to input [14] 32 3.17 Double-sampled and gain-compensated SC integrator with no limit to input during phase (a) φ1 and (b) φ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.18 Magnitude errors of the integrator for Cs = Cf , fin = 10kHz, and fs = 10MHz 35 3.19 The vary double-sampled and gain-compensated SC with no limit to input . . . 36 3.20 The vary double-sampled and gain-compensated SC with no limit to input during (a) φ1 and φ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21 The comparison of gain errors between paper proposed and we proposed for κCa = Cb = Cs = κCs′ = Cs′′ = Cf = Cf′ , fin = 10kHz, and fs = 10MHz . . vii 38 3.22 The output voltage for a non-inverting SC integrator with no compensation shown in Fig. 3.6, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.23 The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.6, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . . . . 40 3.24 The output voltage for a SC integrator that paper proposed shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . . . . 3.25 The transferred charge on the integration capacitor Cf , Cf′ 41 shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . . . . 41 3.26 The output voltage for a SC integrator shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . . . . . . . . . . . . 42 3.27 The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB . . . . . 42 3.28 The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=20dB . . . . 43 3.29 The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=20dB . . . . . . . . 43 3.30 A new single-sampled gain-compensated SC integrator . . . . . . . . . . . . . 45 3.31 A single-sampled gain-compensated SC integrator during (a) phase1 (b) phase2 46 3.32 A simple feedback system . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.33 The output voltage for a SC integrator shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=40dB, and Af = 80dB . . . . . . . . . . . . 49 3.34 Magnitude errors of the integrator for Cs = Cf = Cc1 = Cc2 , fin = 10kHz, and fs = 10MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.35 Magnitude of pole errors for conventional circuit and new gain-compensated topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.36 A fully differential folded-cascode operational amplifier with common-mode feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.37 A wide-swing constant transconductance bias circuit . . . . . . . . . . . . . . 54 3.38 The frequency response of the fully differential folded-cascode amplifier (a) 50dB magnitude (b) 88◦ phase margin . . . . . . . . . . . . . . . . . . . . . . 56 3.39 Simulation of bias output voltage . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.40 Single-end folded-cascode op-amp with output buffer . . . . . . . . . . . . . . 57 viii 3.41 The frequency response of a single-end folded-cascode op-amp (a) 60dB magnitude (b) 84◦ phase margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.42 Definition of speed in a sampling circuit for NMOS switch . . . . . . . . . . . 59 3.43 Definition of speed in a sampling circuit for Transmission gate . . . . . . . . . 60 3.44 Comparison of on-resistance of switch . . . . . . . . . . . . . . . . . . . . . . 60 3.45 The output voltage for a SC integrator with no compensation shown in Fig. 3.1(a), fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=50dB . . . . . . . . 61 3.46 The FFT of the output voltage for a SC integrator with no compensation shown in Fig. 3.1(a), fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=50dB . 61 3.47 The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . 62 3.48 The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.49 The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 20kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . 63 3.50 The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 20kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.51 The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 30kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . 64 3.52 The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 30kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.53 The post simulation for a SC integrator that we proposed, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . . . . . . . . . . . . 65 3.54 The magnification for a SC integrator that we proposed by varying the input frequency shown in Fig. 3.30, with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.55 Layout photo of the new gain-compensated switched capacitor integrator . . . . 66 ix List of Tables 3.1 Simulated summary of the fully differential folded-cascode amplifier . . . . . . x 57 Chapter 1 Introduction 1.1 Background Integrators are used in many analog systems, such as over-sampled analog-to-digital converters, filters, and so on [1]. Perhaps the most popular approach for realizing analog signal processing in MOS integrated circuits is through the use of Switched-Capacitor (SC) circuits, because they can get accurate frequency response. The filter coefficients are determined by capacitance ratio which can be set quite precisely in an integrated circuit. A SC circuit is realized with the use of some basic building blocks, such as op-amp, capacitors, switches, and non-overlapping clock. The basic principles of a SC integrator can be well understood with an ideal op-amp. However, some important non-idealities of the op-amp in practical SC circuits are DC gain, unit-gain frequency, phase margin, slew rate, and dc offset [3]. The DC gain of amplifiers in a MOS technology intended for SC circuits is typically on the order of 40dB to 80dB. Low gain affects the coefficient of the discrete time transfer function of the SC filters. The unit-gain frequency and phase margin of an op-amp gives an indication of the small signal settling behavior of an op-amp. A general rule of the thumb is the clock frequency should be at least five times lower than the unit-frequency assuming phase margin is greater than 70 degrees [4]. The trade off between gain and bandwidth makes high speed and high accuracy circuits not easy be designed. Chapter 2 reviews an overview and modeling of the integrators for both discrete time and continuous time. The non-idealities of the SC integrators, and a double sampling technique that used to improve the sampling rate are also introduced. Chapter 3 demonstrates the design, theory, implementations and simulations of the gain-compensated SC integrators. A way called CDS technique can significantly enhance the op-amp finite gain and reduce the input offset 1 voltage. It is very attractive when used for the delta sigma modulators with MASH structure to reduce the pole error. Finally, we proposed a new topology that have effectively high op-amp finite gain. 1.2 Motivation Q1 ( z ) X(z) (1 - V 1 ) z -1 1 - (1 - d1 ) z -1 Y1 (z) z -1 Y(z) Q2 ( z ) (1 - V 2 ) z -1 1 - (1 - d 2 ) z -1 Y2 (z) 1 - z -1 Figure 1.1: Block diagram of delta-sigma modulator with a 1-1 MASH structure The cascaded (MASH) structure provides the high order noise shaping combined with the robust stability of the first order system. The overall performance, in general, is largely determined by the characteristics of the analog components, specially the integrator. The actual integrator transfer function differs from the ideal case due to the nonzero switch resistance, finite DC gain, finite bandwidth of op-amp, and so on. In general, the integrator transfer function can be written as [4] H(z) = (1 − ζ)z −1 Vout (z) = Vin (z) 1 − (1 − δ)z −1 (1.1) Where ζ and δ are the gain error and pole error, respectively. The effects of the gain error and the pole error can be derived by the analysis of typical delta-sigma modulators with a 1-1 MASH structure shown in Fig. 1.1. Analysis of Fig. 1.1, assume the errors ζi and δi (i=1 and 2) are small. The z-domain output of first, second, and the overall of the modulator is given by Y1 (z) ≈ (1 − ζ1 )z −1 X(z) + [1 − (1 − δ1 )z −1 ]Q1 (z) (1.2) Y2 (z) ≈ (1 − ζ2 )z −1 Q1 (z) + [1 − (1 − δ2 )z −1 ]Q2 (z) (1.3) 2 Y (z) = Y1 (z) · z −1 + Y2 (z) · (1 − z −1 ) = (1 − ζ1 )z −2 X(z) + [δ1 z −2 + ζ2 z −1 (1 − z −1 )]Q1 (z) + [(1 − z −1 )2 + δ2 z −1 (1 − z −1 )]Q2 (z) (1.4) The second and the third term of Eq.(1.4) are quantization noise due to the pole error and gain error. In the second term, the noise of first integrator due to the pole error δ1 is unshaped. However, the pole error of second modulator and both of the gain error was shaped to high frequency, because a zero at DC. It makes the first integrator be a dominant factor that influence the performance of MASH structure. Assuming a conventional SC integrator, the capacitor mismatch of the sampling capacitor Cs and integration capacitor Cf cause the gain error was 0.01. The finite gain A of op-amp is 40dB, then the transfer function can described as Cs −1 z 1.01z −1 Vout (z) Cf = = Vin (z) 1.02 − 1.01z −1 (1 + A2 ) − (1 + A1 )z −1 (1.5) The ideal transfer function, can be described as Vout (z) z −1 = Vin (z) 1 − z −1 (1.6) The entire analog, clock and digital control circuits for the modulators has been implemented in software by Matlab and Simulink. Taking the transfer function of Eq.(1.5) and substitute it into the block diagram shown in Fig. 1.1. The SNR obtained by varying the signal amplitude shown in Fig. 1.2, and depict the quantization noise cannot be shaped when the non-ideal integrator at first stage. However, if the non-ideal integrator at second stage, it will not decrease the performance of the whole system. From Fig. 1.2 and the derivation of Eq.(1.4), we can find that non-ideality due to op-amp finite gain for the SC integrator at first stage in MASH structure dominate the performance. One direct approach to reduce the error is to design a high gain op-amp. Taking the transfer function of Eq. (1.5), and assume A is 60dB. From the simulation result shown in Fig. 1.3, we can find that the SC integrator with high gain at first stage really reduce the errors. In order to solve the pole error that caused by op-amp finite gain, we try to find some way that can enhance the op-amp gain, and don’t need to change the op-amp itself. A way called Correlated Double Sampling (CDS) technique can used for the SC integrator. It sampled the error at one half phase, then compensated it at next half phase, and makes the op-amp finite gain effectively enhanced. In this thesis, we will show how the compensated SC integrator work. Finally, a new topology is proposed. 3 90 Nnoideal integrator @ first stage 80 Nonideal integrator @ second stage Ideal integrator 70 SNR (dB) 60 50 40 30 20 10 0 −100 −90 −80 −70 −60 −50 −40 Signal Amplitude (dB) −30 −20 −10 0 Figure 1.2: SNR variations with amplitude for a 1-1 MASH structure 90 Integrator with no compensation @ first stage 80 Integrator with gain compensated @ first stage 70 SNR (dB) 60 50 40 30 20 10 0 −100 −90 −80 −70 −60 −50 −40 Signal Amplitude (dB) −30 −20 −10 0 Figure 1.3: SNR variations with amplitude for a 1-1 MASH structure and a comparison between conventional and gain-compensated integrator 4 Chapter 2 An Overview of Integrator 2.1 Introduction This chapter discuss the difference between Discrete Time(DT) and Continuous Time(CT) integrators, and the non-idealities of the real integrators, then a double sampling technique that used to increase the sampling rate also introduced. There are several non-idealities of a op-amp, such as finite gain, finite bandwidth, settling time, offset voltage, and so on, which all need to be concerned when design a SC integrator. The transfer function of the integrators used in the systems must be closed to an ideal function, 1/(1 − z −1 ). The chapter will debate the trade off between both the specifications, and review some basic concepts of the SC integrators. 2.2 Switch Capacitor Integrator 2.2.1 Continuous time Integrator CT integrator as shown in Fig. 2.1 and Fig. 2.2 are non-inverting and inverting topology. The ideal transfer function of the two topology can given by [3] 1 −jωI −j Vout (jω) = = = Vin (jω) jωR1 C1 ω ωτI (2.1) Vout (jω) −1 jωI j = = = Vin (jω) jωR1 C1 ω ωτI (2.2) where ωI = integrator frequency τI = integrator time constant Both of the two ideal integrator have magnitude and phase response shown in Fig. 2.3. The magnitude response is the same but phase response is different by 180◦ . From Eq. (2.1) and Eq. (2.2) can find it has a pole at zero in frequency domain. 5 Vin R1 C1 R Vout R Figure 2.1: CT non-inverting integrator Vin R1 C1 Vout Figure 2.2: CT inverting integrator Here we add the influence of finite gain and finite unit-gain-bandwidth (UGB) to CT inverting op-amp show in Fig. 2.2, and the closed-loop transfer function can be described as A(s)(s/ωI ) A(s)sR1 C1 Vout (s) −1 −ωI (s/ωI )+1 1 C1 =( ) 1+sR ) =( A(s)sR C 1 1 Vin (s) sR1 C1 1 + s 1 + A(s)(s/ωI ) 1+sR1 C1 (2.3) (s/ωI )+1 Assume that A(s) of op-amp can be described as A(s) = A(0) s 1 + ω3dB (2.4) At low frequencies (s → 0), A(s) is approximately A(0) and (2.3) becomes Vout = −A(0) Vin At high frequencies (s → ∞), A(s) is approximately U GB , s (2.5) and (2.3) becomes Vout UGB ωI = −( )( ) Vin s s (2.6) Eq. (2.2) (2.5) and (2.6) describe the different frequency transfer function of Eq. (2.3). In order to discriminate the frequency region of the non-ideal integrator due to op-amp finite gain and bandwidth. We can simply assume Eq. (2.2) equal to Eq. (2.5) and Eq. (2.6), and can get ωI A(0) (2.7) ωx2 = UGB (2.8) ωx1 = 6 |Vout(s)/Vin(s)| 100 dB 50 0 −50 −100 1 10 2 3 10 4 10 5 10 6 10 7 10 8 10 10 Arg[Vout(s)/Vin(s)] 2 1 rad/s Noninverting Inverting 0 −1 −2 1 10 2 3 10 4 10 5 10 6 10 7 10 10 8 10 log Figure 2.3: Magnitude and phase response for CT integrator |Vout(s)/Vin(s)| 50 Magnitude dB 0 -50 X1 X3 X2 -100 -150 1 10 2 10 3 4 10 5 10 6 10 7 10 10 8 10 Arg[Vout(s)/Vin(s)] 4 Phase rad/s 3 X4 X5 2 1 0 1 10 2 10 3 10 4 5 10 10 6 7 10 10 8 10 log Figure 2.4: Magnitude and phase response for inverting CT integrator when A(0) and UGB are finite Here we assume the integrator frequency ωI is 10kHz, unit-gain-bandwidth UGB is 10MHz, and op-amp gain is 40dB. The resulting magnitude and phase response of inverting integrator show how the gain and pole effect the ideal integrator. From the simulation result shown in Fig. 2.4, where X1 = ωx1 is due to op-amp finite gain, X2 = ωx2 is due to op-amp finite bandwidth, and X3 = ωI is the integrator frequency. The idealness of the integrator is determine whether the phase is nearly ±90◦ . From the phase response of Fig. 2.4 can get the operational frequency range of CT integrator at the interval between X4 and X5 , the CT integrator will approximate ideal behavior, where X4 = 10ωI A(0) and X5 = U GB 10 [3]. As we can see, a real integrator was limited by the two parameters, gain and bandwidth of op-amp. 7 2.2.2 Switched Capacitor Integrator Consider the circuit shown in Fig. 2.5. The dynamic circuit is useful in simulating a large value of resistor, generally > 1MΩ which not occupy much area in layout [1]. The clock signals φ1 and φ2 form two phase of non-overlapping clock signal. v1 F1 F2 S1 S2 R sc v 2 Û v1 v2 C (a) (b) F1 Û F2 Û v1 v2 C C T (c) Figure 2.5: (a) Switched capacitor resistor (b) and the equivalent circuit (c) and the clock signal with the equivalent circuit When φ1 is high, the S1 is on and the capacitor C is charged to V1 The charge q1 stored on the capacitor during this interval is q1 = CV1 (2.9) When S2 is on, the charge stored on the capacitor is q2 = CV2 (2.10) If V1 and V2 are not equal, then a charge equal to the difference between q1 and q2 is transferred during the interval of clock. The average current is given by Iavg = V1 − V2 C(V1 − V2 ) = T Rsc (2.11) The resistance of the switched capacitor circuit is given by Rsc = 1 T = C Cfclk 8 (2.12) C V1 F1 F2 F 2 F1 C V2 V1 F1 F1 V2 F2 F2 (a) (b) Figure 2.6: (a) Negative and (b) positive switched capacitor circuit Cs Vin F1 F2 Cf Cs Vout Vin F1 F1 F2 F2 Cf Vout F2 F1 (b) (a) Figure 2.7: (a) Inverting and (b) non-inverting SC integrator that are insensitive to parasitic capacitors Where fclk is the clock frequency and Rsc is the equivalent resistance. Because the SC resistor of Fig. 2.5 is sensitive to parasitic capacitors, it finds little use. Consider the circuit of Fig. 2.6 (a) negative and (b) positive switched capacitor resistor that are insensitive to the capacitor parasitics [6], and using the switched capacitor resistor to replace the R1 of Fig. 2.2. The non-inverting and inverting SC integrator are shown in Fig. 2.7. The ideal transfer function of non-inverting integrator can be described as H(z) = Cs z −1 Cs 1 Vout (z) =( ) =( ) −1 Vin (z) Cf 1 − z Cf z − 1 (2.13) To get the frequency response, replace z by ejωT and get H(ejωT ) = Vout (ejωT ) Cs 1 Cs e−jωT /2 = ( ) = ( ) Vin (ejωT ) Cf ejωT − 1 Cf ejωT /2 − e−jωT /2 (2.14) Replacing ejωT /2 − e−jωT /2 , Eq.(2.14) becomes H(ejωT ) = ( Cs e−jωT /2 Cs ωT /2 ) =( )( )(e−jωT /2 ) Cf j2 sin(ωT /2) jωT Cf sin(ωT /2) (2.15) Where the integrator frequency can be expressed as ωI = Cs Cf T 9 (2.16) |Vout(w)/Vin(w)| 12 SC integrator CT integrator 10 Magnitude (dB) 8 6 4 Wi 2 0 0 0.1 0.2 0.3 0.4 0.5 W/W’s 0.6 0.7 0.8 0.9 1 Figure 2.8: Magnitude response of CT and DT non-inverting integrator Arg[Vout(w)/Vin(w)] 4 SC integrator CT integrator 3 Phase (rad/s) 2 1 0 Wi −1 −2 −3 −4 0 0.1 0.2 0.3 0.4 0.5 W/W’s 0.6 0.7 0.8 0.9 1 Figure 2.9: Phase response of CT and DT non-inverting integrator The integrator frequency, ωI , of the SC integrator can be well defined, because it is proportional to the ratio of capacitors. The second and third terms in Eq. (2.15) represent the magnitude and phase error respectively. Here, we assume the CT integrator frequency ωI is equal to 0.2 ωs′ , where ωs′ is five times the sampling frequency ωs of a SC integrator, and ω is the input frequency. The comparison between ideal CT and DT integrators shown in Fig. 2.8 and Fig. 2.9 are magnitude and phase frequency response. The magnitudes of the CT and DT integrators are closed to each other when input frequency is smaller than ωI , but the phase is equal only when ω = 0. We can find when the input signal compare to the sampling frequency is low, like delta sigma modulator. The DT integrator would work like a CT integrator. In many applications, a non-inverting and an inverting SC integrators are in series in a feedback loop [3]. Then, the phase errors of each integrator will be canceled. 10 2.2.3 Non-ideal Effects of Switched Capacitor Integrator The non-ideal behavior of the SC integrators include charge injection, finite gain, settling time, slew rate of amplifier and so on. In this section, we will consider some primary nonidealities of the SC integrators. Finite Gain of Amplifier Vx Vin Cs Cf Cp Vout Vin Cl -AVx Cs Vx Cf Cp (a) Vout Cl -AVx (b) Figure 2.10: Small-signal models of (a) sampling (b) integrating non-inverting SC integrator [2] Fig. 2.10 shows the small-signal linear model of Fig. 2.7 (b). The transfer function of the integrator can be calculated and expressed as [2] H(z) = ( r2 z −1 Cs ) Cf 1 − rr21 z −1 (2.17) Where r1 and r2 are the closed-loop static errors. They can be expressed r1 = f1 A 1 + f1 A (2.18) r2 = f2 A 1 + f2 A (2.19) Where f1 and f2 are the DC feedback factors during both sampling and integration phase. They can be expressed Cf Cf + Cp (2.20) Cf Cf + Cs + Cp (2.21) f1 = f2 = Where Cs is the sampling capacitor, Cf is the integration capacitor, and Cp is the parasitic capacitor of op-amp. As can be seen from Eq.(2.17), the gain and pole errors of the integrator transfer function depend on the gain of the amplifier and the dc feedback factors. 11 Slew Rate of Amplifier The SC integrators like Fig. 2.7 are less sensitive to slew-rate limits than amplifiers. This is because the feedback capacitor, Cf , holds the output voltage of the op-amp constant when no capacitors are being connected to the inverting inputs of the op-amp. Slew-rate limitations occur only when the output of op-amp is changing due to the change of charge on Cf during the interval of integration phase. To avoid this limitation, it is necessary that the following inequality be satisfied[3] T ∆vout (max) < SR 2 (2.22) Where ∆vout (max) is the maximum output swing of the integrator, T is the integration time. Setting time of amplifier -Vin Cs Cf Vout Cp Figure 2.11: SC integrator during integration phase The realization of high-speed and high-accuracy SC integrators are critical for analog signal processing applications, such as data converters. A key component is the settling time of op-amp. The non-inverting integrator of Fig. 2.7(b) sampled the input voltage by Cs during φ1 , and then transferred to Cf during φ2 . During the integration phase φ2 , the op-amp output must settle to desire level of accuracy within the allotted time. Fig. 2.11 shows the configuration of SC integrator during the integration phase, assuming ideal switches. To develop a generalized analysis for SC integrator during the integration phase, the circuit in Fig. 2.11 is mapped into the general model [8] shown in Fig. 2.12. The closed loop is given by ACL (s) = γ(s)AOL (s) + d(s) 1 + AOL (s)β(s) 12 (2.23) d(s) -Vin γ(s) -A(s) S S Vout β(s) Figure 2.12: Feedback model consisting of a feedforward term d(s), a feedback term β(s), an amplifier AOL (s), and an input scaler γ(s) [8] -Vin Cf V- Cs Cp Cf Cs Vout Cp V- (a) (b) Figure 2.13: Equivalent circuits for (a) γ(s) (b) β(s) for an ideal SC integrator [8] The amplifier transfer function A(s) can be expressed as AOL (s) = A(0) s 1 + ω3dB (2.24) Where γ(s) is the transfer function from the integrator input to the input terminals of the op-amp is simply a capacitive network. It is determine by the equivalent circuit shown in Fig.2.13(a), and can be expressed γ= Cs Cs + Cf + Cp (2.25) Where β(s) is the feedback transfer function. It is computed from the equivalent circuit shown in Fig.2.13(b), and can be expressed β= Cf Cs + Cf + Cp (2.26) The contribution of Vin to Vout is determined by the feedforward transfer function, d(s). The SC integrator, d(s) contributes an RHP zero at ωz = gm /Cf [8], where gm is the transconductance of op-amp. The effect of the RHP zero is to cause a small initial step in the output that is opposite in direction to the response to the input step. 13 For the SC integrator, the feedforward term, d(s), is much smaller than the first term in Eq.(2.23) and can be neglected. During the integration phase, the closed-loop gain of the inverting SC integrator can be described as ACL (s) ≃ AOL γ 1 + AOL β (2.27) Combine Eq.(2.24) and Eq.(2.27), and assuming 1 ≫ 1/[βAOL (0)], we can get ACL (s) ≃ γ β (2.28) f 1 + j fU GB β Where f3dB · AOL (0) = fU GB is the unit-gain frequency, the step response of a single-pole system with time constant, τ , can be expressed as τ= 1 (2.29) 2πfU GB β For a step input to the op-amp, the output voltage is given by Vout = Voutf inal (1 − e−t/τ ) (2.30) For the output voltage of the op-amp to settle less than 1% of its final value, Voutf inal , requires 5τ [1]. A rule-of-thumb estimate for the settling time is simply 1/(fU GB · β). Offset of Amplifier Op-amp with offset VV+ Vout Vos Offset free op-amp Figure 2.14: Op-amp with offset voltage The source of offset may arise from the physical design of the differential amplifier or process variations. Circuit thresholds, mismatch of device sizes, are all source of offset error. Many different techniques for calibrating differential amplifier offset error have been proposed. 14 Cf V in F1 Cs F2 V- Vout Vos Figure 2.15: Inverting SC integrator with offset error Cf VCs Cf Vout V in Cs V- Vos Vout Vos (a) (b) Figure 2.16: SC integrator with offset error at (a) sampling phase (b) integration phase One analog technique involves careful physical layout to minimize the basic offset error, or the use of a switch capacitor circuit to correct offset error shown in Fig. 2.14. Another digital technique is to cancel the offset at the output of amplifier [5]. Here we discuss a topical way that used to cancel the offset voltage with switched capacitor topology. An inverting SC integrator shown in Fig. 2.15 is used to discuss. When Φ2 on, the integrator start to sample the offset voltage with the capacitor Cs shows in Fig. 2.16 (a). Then, next phase Φ1 on, it integrate the input voltage shown in Fig. 2.16 (b). At the same time the voltage that storage on Cs during previous phase Φ2 , will cancel the offset voltage. The offset voltage will not be integrated to the output for one cycle clock period. Charge Injection Charge injection can be simple displayed in Fig. 2.17. When the MOSFET switch is on, and Vds is small, the charge under the gate oxide resulting from the inverted channel is Qch . When the MOSFET turn off, this charge is injected to the capacitor and Vin . However the charge is less effect when the switch turn on, because the input voltage is connected to C through the 15 F vin Charge Injection C Figure 2.17: Simple configuration using an NMOS switch to show charge injection [1] channel resistance makes the error unimportant. Charge injection is itself a complex one. It has been shown that if the clock signal turns off fast, the channel charge is distributes fairly equally between the adjacent nodes. Thus, half of the channel charge is distributed onto C [1], and if it is assumed that clock swings between VDD and ground, the charge that appear at the output of C can be approximated as p p ′ Cox W L(V DD − Vin − [VT HN 0 + γ( |2Vf p | + Vin − |2Vf p |)]) ∆Vc = − 2C (2.31) Where ′ Cox = Oxide capacitance per area Vf p = Electrostatic potential of p-type substrate VT HN = NMOS threshold voltage Eq.(2.31) shows the problem associate with charge injection. The change in voltage across C is nonlinear where respect to Vin due to the threshold voltage. Thus, it can be said that if the charge injection is signal-dependent, harmonic distortion appear, such as sampled-data systems. In this section we have discussed some non-ideal effects that primary occur at switched capacitor topology. There are still many other effects, such as clock jitter, capacitive feedthrough, thermal noise, and so on, still need to be concerned. One of the important non-ideal effects is op-amp finite gain and will still be discussed in next chapter. 2.3 Double-Sampled Technique A conventional single-sampled SC integrator is shown in Fig. 2.7. It consists of op-amp, one sampling capacitor Cs , one integrating capacitor Cf , and several switches that are controlled by a two-phase nonoverlapping clock. With this approach, the output is updated only during φ2 , and the maximum sampling rate is limited to 1/(2τ ), where τ is the op-amp settling time. From Eq.(2.29) can find the minimum settling time. 16 Vin Cs1 F 1 F 2 F Cf Vout F 2 1 Cs2 F 2F F 1 F 2 1 Figure 2.18: Double-sampled SC integrator To increase the sampling rate without reducing the op-amp settling time, a double sampling technique can be used [7, 9] shown in Fig. 2.18. During φ1 , Cs1 sampled the input voltage and Cs2 transferred the charge that have been stored at previous half phase to Cf . During φ2 , both two capacitors also do the same thing. Therefore, the output is updated during both two half phase. The maximum sampling rate is limited to 1/τ , where τ is the settling time of op-amp. The sampling rate is twice of the single-sampled SC integrators. The double sampling SC integrator uses two capacitors Cs1 and Cs2 to sample the input voltage. Each sampling capacitor samples the input by multiplying its capacitor by Vin . If Cs1 6= Cs2, the charge that transferred to Cf will be different. But the errors due to the mismatch of capacitors Cs1 and Cs2 will be modulated to half of the sampling frequency, which can be filtered easily. Here we will show how it work. When φ1 on, Cf was integrated by Cs2 , and it can be expressed as Vout (n − 1) = Vout (n − 2) + 3 Cs2 Vi (n − ) Cf 2 (2.32) When φ2 on, Cf was integrated by Cs1 , and can be expressed Vout (n) = Vout (n − 1) + Cs1 1 Vi (n − ) Cf 2 (2.33) Assume that Cs1 = C̄s + ∆Cs /2 and Cs2 = C̄s − ∆Cs /2, then the input-output relationship can be written as [7] Vout (n) = Vout (n − 1) + C̄s (−1)n ∆Cs Vi (n − 1) + Vi (n − 1) Cf 2Cf (2.34) The last term of Eq.(2.34) is the product of the input and (−1)n , which is the modulation of the input by a sampled cosine at frequency fs /2, because (−1)n = cos(2π((fs /2)nT )) .Therefore, the errors can filtered to high frequency. 17 Cs1 Vin F F 1 F F Cs2 2 F 2 D Q F 2 1 F F 1 Vout Cf 1 2 out out Vr -Vr Figure 2.19: A first-order double-sampled delta sigma modulator [7] Cf Cs1 V in F 1 F2 D Q F F2 1 Vout Cs2 F F 2 F F 1 1 2 C r1 Y r C r2 Y Y Z Z Y V FSM Y Z Z Z Figure 2.20: A first-order double-sampled modulator using additive-error switching [7] Although a double sampling SC integrator is very attractive to have twice sampling rate, and have no problem on sampling capacitors mismatch for input voltage. However, when consider the application for delta sigma modulator shown in Fig. 2.19, the errors that from the output quantizer will mixe to the baseband. Because the modulator works like a filter, and will shape the noise from baseband to high frequency. When there is a mismatch between Cs1 and Cs2. From Eq.(2.34), the noise that have already shaped to high frequency now will be mixed to baseband. There are many way [7, 9, 10] have been proposed to solve this problem. Fig. 2.20 shows a first order double-sampled delta sigma modulator with a finite state machine(FSM) [7]. Compare to the conventional modulator show in Fig. 2.19, the different of them are quantizer and FSM. The key point here is that the quantizer voltage Vr shows in Fig. 2.20 not switching. There is a constant voltage Vr at the op-amp input, it means that quantization noise will not mixed to the baseband. The FSM used here is to control phase Z and Y , which not only provide positive or negative feedback voltage Vr , but also make the function of Eq.(2.34) work. The algorithm that form by FSM is not complex and can be constructed by digital circuit. The double sampling way that used to improve the sampling rate is very attractive. 18 2.4 Summary In this chapter we have discussed the difference between CT and DT integrators. Both of them will be similar when the input frequency of the DT integrators relative to the sampling frequency is low. The phenomenon makes the topology that operate at high frequency very attractive, such as delta sigma modulators. The non-idealities of the SC integrators and the trade off between both of them are also discussed. One of the non-idealities is the op-amp finite gain, if it has infinite value, the SC integrator will work like an ideal integrator 1/(1 − z −1 ). The op-amp finite gain makes the pole of discrete-time integrator deviate from the ideal position z = 1 yielding a DC finite gain in the SC integrator. There are some trade off between those non-ideal parameters when design a circuit, how to choose the specification depends on the applications. A double-sampled technique that used to increase the sampling rate makes it easier to design the bandwidth of op-amp, because there is a trade off between high gain and high bandwidth of op-amp. However, the offset voltage may not canceled during one of half phase. In next chapter, a SC integrator that has effective high gain will be introduced, It uses a CDS technique to sample the errors due to op-amp finite gain, then compensates it at next half phase. 19 Chapter 3 The Gain-Compensated SC Integrators 3.1 SC Integrator With No Compensation 3.1.1 Introduction This chapter discuss the SC integrators with no compensation first, then a CDS technique that used to compensate the errors due to op-amp finite gain will be introduced. The sampling frequency of the SC integrators is limited by the op-amp settling time. A circuit combine the CDS technique with double sampling frequency is very attractive. However, there is a trade off between op-amp offset voltage and sampling frequency. The comparison between doublesampled and single-sampled technique can makes it more clear. Finally, we proposed a new single-sampled gain-compensated SC integrator, the simulation results and math derivation are all conform to the original design specifications. 3.1.2 Conventional SC Integrator Cf Cs Φ1 Φ2 Φ2 Φ1 Φ1 Φ2 Vout Φ1 Φ2 Vin Φ1 Cs Cs Φ1 V- A Vin Φ2 Cf Φ2 Φ2 Φ1 V- A Φ2 Cs Φ1 Cf Cf (a) (b) Figure 3.1: (a) Non-inverting and (b) Inverting SC integrator 20 Vout Cf Cf Cs A Vin Cs V- A Vout Cs Cs Vout Cf Cf (b) (a) Figure 3.2: Non-inverting SC integrator during (a) φ1 and (b) φ2 Cf Cf Cs V- A Cs Vout Vin V- A Vout Cs Cs Cf Cf (b) (a) Figure 3.3: Inverting SC integrator during (a) φ1 and (b) φ2 The topology shown in Fig. 3.1 (a) is a non-inverting SC integrators, and it can be analyzed with two consecutive half phase shown in Fig. 3.2. When φ2 on, the charge conservation at node V − can be expressed as 3 3 1 − Cs [Vi (n − 1)] − Cf [ Vout (n − ) + Vout (n − )] A 2 2 (3.1) 1 1 1 1 1 = − Cs [ Vout (n − )] − Cf [ Vout (n − ) + Vout (n − )] A 2 A 2 2 Taking the z-transform, and assume the capacitors Cs = Cf , the overall transfer function can be expressed −1 Vout (z) z2 = 2 Vi (z) (1 + A ) − (1 + A1 )z −1 (3.2) The inverting SC integrator shown in Fig.3.1 (b), also can be analyzed with two consecutive half phase shown in Fig. 3.3. When φ1 on, the charge conservation at node V − can be expressed as 3 3 1 − Cf [ Vout (n − ) + Vout (n − )] A 2 2 1 1 1 1 1 1 = − Cs [ Vout (n − ) + Vi (n − )] − Cf [ Vout (n − ) + Vout (n − )] A 2 2 A 2 2 21 (3.3) Taking the z-transform, and assume the capacitors Cs = Cf , the overall transfer function can be expressed as −1 Vout (z) = 2 Vi (z) (1 + A ) − (1 + A1 )z −1 (3.4) From Eq.(3.2) and Eq.(3.4), can find that the non-inverting and inverting SC integrator have the same pole error, which is proportional to 1/A. The difference of them only a half of delay and phase shift by 1800 . The transfer function also can derive from Eq.(2.17), which combine the parasitical capacitor for more detail. C¢s F 1 F F 2 F 2 Cs F 2 F 1 F F 1 2 Vin F 1 F 2 1 2 F Cs 2 F F F F Cf 1 1 F - V A Vout 1 Cf 2 C¢s Figure 3.4: Non-inverting double-sampled SC integrator The SC integrator with double-sampled technique, which used to double the sampling rate is shown in Fig. 3.4. The non-inverting SC integrator can be analyzed with two consecutive half phase shown in Fig. 3.5. When φ2 on, the charge conservation at node V − can be expressed as 1 − Cs′ [Vi (n − 1)] − Cf [ Vout (n − 1) + Vout (n − 1)] A 1 1 1 1 ′ 1 = − Cs [ Vout (n − )] − Cf [ Vout (n − ) + Vout (n − )] A 2 A 2 2 (3.5) Taking the z-transform, and assume the capacitors Cs = Cs′ = Cf , the overall transfer function can be expressed −1 z2 Vout (z) = −1 Vi (z) (1 + A2 ) − (1 + A1 )z 2 22 (3.6) C¢s Cs Cf Cs C¢s - V - V A Vin Cf Vout A Vin Vout C¢s Cs C¢s Cs Cf Cf (a) (b) Figure 3.5: Non-inverting double-sampled SC integrator during (a) φ1 and (b) φ2 F C¢s F 1 F F 2 F F 2 2 F F 1 F 1 F 2 2 1 F Cf A 2 F Cs 2 F F 1 F 1 - V Vin F C¢f 1 Cs F 2 Vout 1 1 F 2 F C¢s F 1 2 Cf C¢f Figure 3.6: Non-inverting double-sampled SC integrator with two integration capacitors C¢s Cs C¢s - V Vin - A V C¢f Vout Vin C¢f Cs C¢s C¢f Cs Cf A Cs Vout Cf C¢s Cf Cf C¢f (b) (a) Figure 3.7: Non-inverting double-sampled SC integrator with two integration capacitors during (a) φ1 and (b) φ2 23 Another double-sampled SC integrator used two integration capacitors shown in Fig. 3.6 also can be analyzed with two consecutive half phase shown in Fig. 3.7. When φ2 on, the charge conservation at node V − can be expressed as 3 3 1 − Cs′ [Vi (n − 1)] − Cf′ [ Vout (n − ) + Vout (n − )] A 2 2 1 1 1 ′ 1 ′ 1 = − Cs [ Vout (n − )] − Cf [ Vout (n − ) + Vout (n − )] A 2 A 2 2 (3.7) Taking the z-transform, and assume the capacitors Cs = Cs′ = Cf = Cf′ , the overall transfer function can be expressed −1 z2 Vout (z) = H(z) = Vi (z) (1 + A2 ) − (1 + A1 )z −1 (3.8) The DC magnitude at z = 1 can be expressed |H(z)|z=1 = A (3.9) The circuit shown in Fig.3.6 use two integration capacitors Cf , Cf′ , and two sampling capacitors Cs , Cs′ to integrate the input voltage. It has two paths to transfer the charge alternately, and each path works like the circuit shown in Fig.3.1 (a) do. From the transfer function of the SC integrator that discussed above shown in Eq.(3.2) and Eq.(3.8), can find they are same. The only difference is Fig.3.6 integrated input voltage during both half phase. Compare to the another double-sampled SC integrator shown in Fig. 3.4, which use only one integration capacitor. The charge always transfer to the capacitor Cf during both half phase, the Eq.(3.6) show a half of delay term. It is a key point when design a gain-compensated SC integrator. Because the topology of Fig.3.4 that use only one integrating capacitor will accumulate input voltage and gain error for two consecutive half phase. It will make the gain-compensated SC integrator cannot be realized, the reason will discussed more detail in next section. As we can see, the pole error of SC integrator with no compensation is proportion to 1/A. In order to reduce the non-ideal effects, the way called gain-compensated technique will be introduced next. 3.2 Existed Gain-Compensated Integrators 3.2.1 Introduction A topology of SC integrator with gain compensation is proposed. It employs the same input as in the integrating phase during the calibration cycle to compensate for the integrating pole error due to the finite gain of op-amp. The SC integrator error can be classified by its 24 gain and pole errors. Capacitor mismatch causes the gain error while the finite op-amp gain causes the gain and pole errors. It is difficult to design an op-amp with both high gain and wide bandwidth, therefore the combination of gain-compensated and double-sampled technique will be attractive. In this section we will discuss a single-sampled gain-compensated technique first, then a double-sampled technique will be introduced. At last, a new single-sampled gaincompensated circuit is proposed. 3.2.2 Single-Sampled Gain-Compensated Integrator F Vin F 2 Cs V F 1 2 Cf - Vout F 2 F 1 F 1 F 2 C¢f C¢s F 2 Figure 3.8: Gain-compensated SC integrator with limit in input [12] A topology of SC integrator with gain compensation shows in Fig. 3.8 is proposed [12]. The output is valid during phase2, and produce an output during phase1 equal to the output during phase2. By maintaining an approximately constant output voltage from phase1 to phase2, V − = −Vout /A remains nearly constant during phase1 and phase2 as desired. The circuit works well under the assumption that Vin is approximately constant. First, we analysis how the circuit work, and discuss the limitation of Vin . Then another topology that used to improve this topology will be introduced. Finally, make a comparison between of them. The topology that have effective high gain can be described as follow. The circuit can be analyzed with three half consecutive phase, form (n-3/2) to (n-1/2). First, we assume the circuit start at φ2 (n-3/2) shown in Fig. 3.9(a). During this phase, the circuit not only integrated the input voltage but also mix the error voltage that due to op-amp finite gain. The charge storage in the capacitors Cs Cf and Cf′ , include the mixed error charge. The mixed error charge that due to the op-amp finite gain is Vout (n − 3/2)/A. Next, the circuit 25 Cf Vin Cs C¢s V C¢f - Vout A Vin C¢s V Cs C¢f - Vout A Cf (a) (b) Figure 3.9: The SC integrator during (a) phase2 and (b) phase1 switch to φ1 (n-1) shown in Fig. 3.9(b). The capacitor Cs′ = 2Cs are used to cancel the input voltage that dump by Cs at previous phase, also integrated the input voltage to output. There will be a problem here for input voltage limitation, and it will be discussed next. During this phase, the voltage Vin (n − 1) and Vout (n − 3/2)/A was integrated to the capacitor Cf′ , where the second term Vout (n − 3/2)/A was dumped by the capacitor Cs . The capacitor Cf′ now storage the previous and this moment input voltage and previous gain error. Then the capacitor Cs will storage the voltage Vout (n − 3/2)/A2 and Vout (n − 1)/A on it. At third phase, the circuit switch to φ2 (n − 1/2), the voltage storage on Cs with Vout (n − 1)/A will be canceled by Vout (n − 1/2)/A, and only the term of Vout (n − 3/2)/A2 preserve. The circuit works like to predict the error voltage and cancel it at next phase. This is how it have effective squared gain. Here shows the charge conservation at op-amp inverted input. First, when φ1 high, and φ2 low, the charge conservation at node V − can be described as 3 3 3 1 − Cs [ Vout (n − ) + Vin (n − )] − Cf′ [Vout (n − )] A 2 2 2 1 1 1 = − Cs [ Vout (n − 1)] − Cs′ [ Vout (n − 1) + Vin (n − 1)] − Cf′ [ Vout (n − 1) + Vout (n − 1)] A A A (3.10) Second, when φ2 high, and φ1 low, the charge conservation at node V − can be described as 1 1 3 3 − Cs [ Vout (n − 1)] − Cf [ Vout (n − ) + Vout (n − )] A A 2 2 1 1 1 1 1 1 = − Cs [ Vout (n − ) + Vin (n − )] − Cf [ Vout (n − ) + Vout (n − )] A 2 2 A 2 2 (3.11) Combining Eq.(3.10) and Eq.(3.11) assuming that 2Cs = Cs′ , and taking the z-transform, the overall transfer function can be expressed −1 (1 + A4 )z 2 + A1 z −1 Vout (z) = H(z) = −3 −1 Vin (z) [(1 + A4 )(1 + A1 ) + A1 (1 + A1 )]z 2 − [(1 + A4 )(1 + A2 )]z 2 26 (3.12) The DC magnitude at z=1 can be expressed |H(z)|z=1 = 5A + A2 3 (3.13) To show the disadvantage of ”slow moving” of input show in Fig. 3.8, we first assume ideal switch and ideal op-amp here. The circuit can be analyzed over three consecutive half clock cycles shown in Fig. 3.9. On the last half cycle, phase2, Vin is integrated onto Cf through Cs to produce Vout (n), and can be expressed as Vout (n) = Vout (n − 1) − Cs Vin (n) Cf (3.14) On phase1 at time (n − 1/2), Cs dumps its charge Cs · Vin (n − 1) to Cf′ , also Cs′ = 2Cs inject a charge −2Cs · Vin (n − 1/2) to Cf′ . The total charge that transferred from Cs′ and Cs can be express Qtotal = QCs (n − 1) + QCs′ (n − 1/2) (3.15) = Cs · Vin (n − 1) − 2Cs · Vin (n − 1/2) From Eq.(3.15) can find that Vin (n − 1) ≈ Vin (n − 1/2) is needed, and they are the reason why the input must be slow moving, it means that input must be approximately constant. To solve this disadvantage, another topology have been proposed [13] shown in Fig. 3.10. Fig.3.11 shows the circuit during φ1 and φ2 . It is assumed that the discrete time during φ1 is (n-1/2) and that during φ2 it is n. Thus, the discrete times associate with the previous φ1 and φ2 are (n-3/2) and (n-1), respectively. The charge conversion equation at node V − can be described in three half cycle. F1 Vin F1 Cs V F2 F2 Cf - A Vout F1 C¢f F1 C¢s F2 F 1 Figure 3.10: Gain-compensated SC integrator with no limitation for input signal [13] 27 Cf Cs Vin V C¢f - C¢s Vout A Cs V - C¢s C¢f A Vout Cf (a) (b) Figure 3.11: The SC integrator during phase (a) φ1 and (b) φ2 First, when φ2, high, and φ1, low, the conversion at node V − can be described as Vout (n − 32 ) 3 3 3 − Cs [Vin (n − ) + ] + Cs′ Vin (n − ) − Cf′ Vout (n − ) 2 A 2 2 V (n − 1) V (n − 1) V (n − 1) out out out = − Cf′ [Vout (n − 1) + ] − Cs′ − Cs A A A (3.16) Second, when φ1, high, and φ2, low, the conversion at node V − can be described as Vout (n − 32 ) 3 Vout (n − 1) + Vout (n − )] − Cs [ ] − Cf [ A 2 A Vout (n − 12 ) Vout (n − 21 ) 1 1 = − Cs [Vin (n − ) + ] − Cf [ + Vout (n − )] 2 A A 2 (3.17) Combining Eq.(3.16) and Eq.(3.17), and assuming the op-amp DC gain≫ 1 [15], the charge conservation equation of the V − becomes Cf Cs 1 + ] Vout (n − )[Cf + 2 A A 3 Cf Cs Cs Cf′ + Cs′ 1 =Vout (n − )[Cf + + − 2( )] − Cs Vin (n − ) ′ 2 A A A Cf 2 (3.18) Taking the z-transform of Eq.(3.18), and assuming Cs′ = Cs , the approximated overall transfer function can be obtained as H(z) = − 1 − ( A1 + 1 − [1 − Cs ) ACf Cs (1 + CCs′ )]z −1 A2 Cf f (3.19) If Cs = Cs′ = Cf = Cf′ is assumed, Eq.(3.19) becomes H(z) = − 1 − A2 1 − (1 − A22 )z −1 (3.20) Where the gain error is 2/A and the pole error is 2/A2, the gain is enhanced significantly when compare to the DC gain of A for simple integrator as shown in Fig. 2.7. From analysis the 28 difference of them, we can find out the key point to design a SC integrator that insensitive to the finite gain of op-amp is the Cs . When Cs always connect at the inverted input of opamp, the voltage of −Vout /A will be sampled at the Cs during both phase. Then the term of Vout (n − 1/2)(Cs /A) and Vout (n − 3/2)(Cs /A) will be canceled as shown in Eq.(3.18). It is the reason why have effective finite gain, because only the term 1/A2 will keep. The offset of the op-amp can also canceled by Cs . The another advantage of Fig. 3.10 is the use of capacitor Cs′ . The circuit use Cs′ to sample the input first, and then compensate the voltage that dumped by Cs at previous phase. It makes the disadvantage of ”slow moving” will not happen. Here we use an ideal op-amp to construct the single-sampled integrator shown in Fig. 3.10. In order to test the function of the topology, a 10kHz sinusoidal signal with amplitude of 1mv is applied to the topology. The sampling frequency is 10MHz, and the gain of the amplifier is 40dB. Then the output magnitude and phase of an ideal inverting integrator is given by |H(z)|ideal = | 6 −1 −1 |=| fin | ≈ 159.15 −1 1−z 1 − e−j2π fs ◦ ◦ H(z)|ideal ≈ 180 − 90 = 90 (3.21) ◦ The output magnitude and phase of the integrator with no compensation shown in Fig. 3.1(b) is given by −A | ≈ 84.3 (2 + A) − (1 + A)z −1 ≈ 147.65◦ |H(z)|no compensation = | 6 H(z)|no compensation (3.22) Where A is the op-amp finite gain. The output magnitude and the phase of the integrator with gain compensation that paper proposed shown in Fig. 3.10 is given by |H(z)|paper = | − 6 H(z)|paper ≈ 92 1 − A2 | ≈ 155.9 1 − (1 − A22 )z −1 (3.23) ◦ From Eq.(3.21) and Eq.(3.23), can find the SC integrator with gain compensation is very close to ideal ones. The DC magnitude is effectively to A2 /2, and makes the op-amp more easier to design without high op-amp gain. The finite gain of op-amp not only reduce the magnitude of output signal but also cause a phase error. The simulation results shown in Fig. 3.13 and Fig. 3.14 are the output signal of the SC integrators for conventional ones with no compensation and paper proposed. The simulation results shown in Fig. 3.15 is an SC integrator with no compensation but constructed of a 80dB op-amp. The output voltage for a high gain op-amp will be more approximately to an ideal SC integrator. The frequency response of the op-amp with finite gain 40dB was shown in Fig. 3.12. 29 Figure 3.12: The frequency response of the macro model op-amp with 40dB magnitude Figure 3.13: The output voltage of the SC integrator with no gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=40dB 30 Figure 3.14: The output voltage of the SC integrator with gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=40dB Figure 3.15: The output voltage of the SC integrator with no gain compensation, fin = 10kHz with amplitude 1mv, fs = 10MHz, and A=80dB 31 The gain-compensated technology that we discussed above are single-sampled topology. It sampled the gain error during one half phase, then compensated it during next half phase. The another one was constructed with a double-sampled technology, which integrated the input voltage during both two half phase, but only one half phase has the gain compensation. Next, we will show a double-sampled gain-compensated SC integrator and find the trade off between both of them. Finally, we design a circuit which is the modification of the paper proposed, and make a comparison of them. 3.2.3 Double-Sampled Gain-Compensated Integrator A topology of SC integrator shown in Fig. 3.16 that combine with the double-sampled technique, and gain compensation has been proposed. The output is valid during both two half phase, and effectively double the sampling rate. The primary difference between doublesampled and single-sampled integrator is the sampling phase. A single-sampled SC integrator sample the gain errors only during one half phase, and then compensated it at next half phase. However, there is no additional phase for double-sampled SC integrator to use, because it integrated the input voltage at both two half phase. The circuit has two feedback capacitors Cf and Cf′ , two sampling capacitors Cs and Cs′ , one compensated capacitor Cs′′ , and was constructed C¢¢s C¢s F1 F2 F2 F1 Cf F2 Cs F2 V- F1 Vin F2 A Vout F1 Cs F1 C¢f F1 F2 C¢s F2 F2 Cf F1 F1 C¢f C¢¢s Figure 3.16: Double-sampled and gain-compensated SC integrator with no limit to input [14] 32 in differential pair. It is not only reduced the odd harmonic effects, but also can use by Cs′′ to cancel the ”slow moving” effect. There are some other properties for this topology, and can be analyzed from three half consecutive phase as shown in Fig. 3.17. To analyze more convenient, here we assume the capacitor number that connect at inverted input of op-amp during φ1 is α, during φ2 is β. C¢¢s C¢f C¢s C¢s Cf C¢¢s Cs Cf V- Cs A Vin C¢f V- A Vout Vin Vout Cs Cf C¢f Cs C¢¢s C¢s C¢f C¢¢s C¢s (a) Cf (b) Figure 3.17: Double-sampled and gain-compensated SC integrator with no limit to input during phase (a) φ1 and (b) φ2 First, when φ1 high and φ2 low, the charge conversion at node V − can be described as Vout (n − 32 ) Vout (n − 2) 3 3 ] − Cf′ [Vout (n − 2) + ] + Cs′′ [Vin (n − )] − Cs [Vin (n − ) + 2 A A 2 Vout (n − 1) Vout (n − 1) Vout (n − 1) = − Cs [ ] − Cs′ [ + Vin (n − 1)] − Cs′′ [ ] A A A Vout (n − 1) − Cf′ [ + Vout (n − 1)] A (3.24) Second, when φ2 high and φ1 low, the charge conversion at node V − can be described as Vout (n − 23 ) Vout (n − 1) 3 ] − Cf [Vout (n − ) + ] A 2 A Vout (n − 12 ) Vout (n − 21 ) 1 1 = − Cs [Vin (n − ) + ] − Cf [Vout (n − ) + ] 2 A 2 A − Cs [ 33 (3.25) Combining Eq.(3.24) and Eq.(3.25), assuming that Cs = Cs′ = Cs′′ = Cf = Cf′ , the charge conservation equation of the V − becomes −1 3 −(β − 1) A α 1 Vout (n − 2)[ − 1] + Vout (n − )[ −( )( + 1)( + 1)] + Vin (n − 1) A 2 A β−1 A A α β A 1 −α A 1 = −Vout (n − )[(1 + )(1 + )( )] + Vin (n − )[( − 1)( )] 2 A A β−1 2 A β−1 (3.26) Taking the Z-transform of Eq.(3.26), the overall transfer function can be obtained as −1 A ( −α − 1)( β−1 )−z 2 Vout (z) A = −3 −1 H(z) = A A Vin (z) z 2 ( A − 1) + z −1 [ −(β−1) − ( β−1 )( Aα + 1)( A1 + 1)] + [(1 + Aα )(1 + Aβ )( β−1 )] A (3.27) The DC gain at z=1 can be described as, and α 6= β −1 )A2 − (1 + ( β−1 α )A β−1 (3.28) | α−β From Fig. 3.17 can find that the number of capacitors at inverted input of op-amp during both |H(z)|z=1 = | φ1 (α = 4) and φ2 (β = 2), then substitute the value into Eq.(3.28), the DC magnitude at z=1 can be expressed as A2 + 5A (3.29) 2 After a careful analysis including the op-amp finite gain, here we assume A = 1/µ, the integra|H(z)|z=1 = tor output voltage in the z-domain also can given by[14] Vout (z) = Hi (z)E(z)Vin (z) (3.30) Where assume Cs = Cs′ = Cs′′ , Cf = Cf′ and Hi (z) = − E(z) = 1 Cs Cf 1 − z −1 x + µ CCfs z x(1 + µ) + 1 [xµ CCfs 1−z −1 (3.31) −1 2 − (µ CCfs )2 z −1 − (1 + µ)µ CCfs z −3 2 ] (3.32) Cs (3.33) Cf Hi (z) represents the ideal transfer function of a SC integrator, and E(z) gives an estimation of x = 1 + µ + 3µ the transfer-function deviation caused by the op-amp finite gain. The error function magnitude was computed as |1 − E|. Here we use a SC integrator with no compensation shown in Fig. 2.7, and compare to the circuit shown in Fig. 3.16. The gain errors are in the order of 2/A2 for compensated topology, but1/A for non-compensated topology. As Fig.3.18 demonstrates, the compensated topology has better magnitude accuracy. 34 0 SC Integrator With No Gain Compensation (|1−E|) Double−Sampled Gain−Compensated SC Integrator (|1−E|) −10 Magnitude Error (dB) −20 −30 −40 −50 −60 −70 0 200 400 600 800 1000 1200 Op−Amp DC Gain 1400 1600 1800 2000 Figure 3.18: Magnitude errors of the integrator for Cs = Cf , fin = 10kHz, and fs = 10MHz The circuit has twice sampling rate, equivalent high op-amp gain, and no limitation to input signal for ”slow moving”. But there is a disadvantage for op-amp offset voltage, and cannot be canceled. To know how this happen, we can see the capacitors Cs Cs′ and Cs′′ shown in Fig. 3.16. During phase φ2 the right hand side of capacitor Cs connected at inverted input of op-amp, Cs′ short to ground at two side, and Cs′′ connect at the inverted input with its left hand side. During phase φ1 the right hand side of capacitor Cs still connected at inverted input of op-amp, and the offset voltage that storage on the capacitor Cs during previous phase will be canceled. The capacitor Cs′ connect to the inverted input of op-amp, and the offset now integrated to the output. The capacitor Cs′′ connect to the inverted input of op-amp with its right hand side to compensate the input voltage that dump by the Cs at previous phase, it also integrated the offset voltage to the output. We can find that the offset voltage will be integrated due to the capacitor Cs′ and Cs′′ . If we assume that the offset voltage shows in Fig. 2.14 is 1mv, it means the 1mv will be integrated to the output during φ1 in this topology. One reason that cause the offset voltage is the capacitor Cs′ not always connect at op-amp inverted input shown in Fig. 3.16. Is it possible to reduce or cancel the offset voltage, and also have gain-compensated effect. In next section we will alter the topology of Fig. 3.16, and explain the trade off between offset voltage, input limitation, gain-compensation, and doublesampled technique. 35 3.2.4 The Modification of A Double-Sampled Gain-Compensated SC Integrators In this section, we will vary the circuit of Fig.3.16 and discuss the restrictions when design a double-sampled gain-compensated SC integrator. The modification circuit shown in Fig. 3.19 have two integrating capacitors, two sampling capacitors and three compensated capacitors. There are three steps to design the circuit and we can find out the trade off between offset voltage, input limitation, and gain compensation. F 1 F C¢s F 2 F Cs + V in F 2 F 1 F F 1 2 F F Cf 2 C¢f - F 1 V V in A C¢s V in 1 Vout 2 F Cs F 1 V in + V in Cf F F Ca Cb 2 F 1 - F + V in V - V F V in - 2 F 1 F Ca Cb 2 + V + 2 V+ F 1 F V 2 F 1 F 2 F 1 F C¢¢s 2 F 1 + Vin 2 V- F 1 F V 2 F 1 F 2 F 1 F 1 F 2 F 1 F C¢¢s V + 2 2 C¢f 1 Figure 3.19: The vary double-sampled and gain-compensated SC with no limit to input Cb + V in · Ca C¢¢s Cs C¢¢s Cs V in · Cf C¢s - A C¢f Vout C¢f C¢s Cf C¢f Cs + V in V Ca Cb Cb C¢¢s Ca C¢s C¢¢s Ca C¢s V in - V A Cf Cs C¢f Cb (a) (b) Figure 3.20: The vary double-sampled and gain-compensated SC with no limit to input during (a) φ1 and φ2 36 Cf Vout As we can see from Fig. 3.16, the sampling capacitor Cs′ not always connect at the inverted input of op-amp. It causes the offset voltage cannot be canceled and will integrate to the output. To improve this condition, first, we vary the capacitor Cs and Cs′ always connect at the inverted input of op-amp shown in Fig. 3.19 to cancel the offset voltage. But now the previous input voltage would be dumped by Cs and Cs′ at next phase. In order to solve this problem, second, we use the capacitors Cs′′ and Ca to cancel the previous input voltage that dumped by Cs and Cs′ . But now the capacitor Ca sample the negative input voltage, it will make the integrator have no input voltage can integrated to output during φ1 . In order to solve this problem, third, we use the capacitor Cb connect to the positive input. There are three steps for us to construct the topology. The capacitors we discuss above are all upper half of the differential pair circuit show in Fig. 3.20. We can find that during each phase, the capacitors are used to solve different problems that cause by the other capacitors. Then, let we check if the offset voltage can be reduced or canceled now. The capacitors Cs and Cs′ shown in Fig. 3.19 will not integrate the offset voltage during each consecutive half phase, because they always connect at the inverted input of op-amp. However, the capacitor Cb and Cs′′ will contribute a offset voltage now. Compare to the Fig. 3.16 that the offset voltage was caused of the capacitors Cs′ and Cs′′ . We can find that the offset voltage still cannot reduced. How about the finite gain in this topology. It can be described with the same way shown in Eq.(3.24)∼Eq.(3.26). The DC magnitude of this topology can be expressed from Eq.(3.28). Here we assume the capacitors Ca = Cb = Cs = Cs′ = Cs′′ = Cf = Cf′ . Substitute α = 6 and β = 4 into Eq.(3.28), the DC magnitude can be expressed |H(z)|z=1 = 1 2 A 3 + 3A 2 (3.34) As we can see, the performance of the effective finite gain is inferior to Fig. 3.16. To make the effective gain better, here we adjust the size of the capacitors Ca and Cs′ . The capacitors size can be expressed Cb = Cs = Cs′′ = Cf = Cf′ = C and Ca = Cs′ = κC where 0 ≤ κ. It will not influence the original integrator function when adjust the size of the capacitors Ca and Cs′ , because the input voltage that integrated by Ca and Cs′ are canceled by each other. The input voltage only integrated by Cb , Cf during φ1 , and integrated by Cs , Cf′ during φ2 . The analysis of this circuit is also the same, and can substitute the value of capacitor number into α and β shown in Eq.(3.28). However the value of α and β should consider of the coefficient κ. In this topology, the coefficients α and β can be expressed as α = 4 + 2κ β = 2 + 2κ 37 (3.35) Here we make a comparison between the circuit that has been modified by us shown in Fig. 3.19, and paper proposed shown in Fig. 3.16. From the result shown in Fig. 3.21 can find that the magnitude of the gain errors are proportional to the coefficient κ. We can find that the magnitude for both two circuits are very approximate, when κ is smaller than 1/8. The derivation of Eq.(3.24) and Eq.(3.25) describe the charge conservation at inverted input of opamp. We can find that the gain errors due to op-amp finite gain are attenuated during three half consecutive phase. There is only one integration capacitor can integrate the input voltage more accuracy, the another one is inferior corresponsively. Because the circuit need to sample the previous gain errors first and then cancel it at next phase. The two topologies all have at least one sampling capacitor always connect at the op-amp inverted input. It makes the gain errors can be stored and then compensated at next half phase. The effective finite gain of the SC integrator is enhanced, because it reduce the gain error at inverted input, and the charge can transferred to the output more accuracy. In order to show how this work, we use an op-amp macro model with several finite gains to construct the two topology and simulate it by HSPICE. 0 Modification SC Integrator (|1−E|, k=1/2) Modification SC Integrator (|1−E|, k=1/8) Paper Proposed SC Integrator (|1−E|, k=0) −10 Magnitude Error (dB) −20 −30 −40 −50 −60 −70 0 200 400 600 800 1000 1200 Op−Amp DC Gain 1400 1600 1800 2000 Figure 3.21: The comparison of gain errors between paper proposed and we proposed for κCa = Cb = Cs = κCs′ = Cs′′ = Cf = Cf′ , fin = 10kHz, and fs = 10MHz 38 In order to test the function of an integrator, a 10kHz sinusoidal signal with amplitude of 1mV is applied to the integrator. To see the gain-compensated effect more clear, here we assume the gain is small. The sampling frequency is 10MHz, and the gain of operational amplifier is 40dB. The magnitude of an ideal non-inverting integrator is given by fin |H(z)|ideal 6 e−jπ fs z −1/2 =| | = | fin | = 159.15 1 − z −1 1 − e−j2π fs (3.36) H(z)|ideal ≈ −90◦ The magnitude of an integrator with no compensation shown in Fig. 3.6 is given by, where A is the op-amp finite gain Az −1/2 | ≈ 84.3 (2 + A) − (1 + A)z −1 ≈ −32.53◦ |H(z)|no compensation = | H(z)|no compensation 6 (3.37) The magnitude of the inverting integrator that paper proposed shown in Fig. 3.16 is given by, where α = 4, β = 2 |H(z)|paper = A ( −α − 1)( β−1 )−z A z −3 2 −1 2 A α A ( −1 − 1) + z −1 [ −(β−1) − ( β−1 )( Aα + 1)( A1 + 1)] + [(1 + A )(1 + Aβ )( β−1 )] A A ≈156.7 6 H(z)|paper ≈91.89◦ (3.38) The magnitude of the inverting integrator that we proposed shown in Fig. 3.19 is also can given by Eq.(3.38), where α = 4 81 , β = 2 18 |H(z)|alter = A ( −α − 1)( β−1 )−z A z −3 2 −1 2 A A ( −1 − 1) + z −1 [ −(β−1) − ( β−1 )( Aα + 1)( A1 + 1)] + [(1 + Aα )(1 + Aβ )( β−1 )] A A ≈156.3 (3.39) From the simulation results shown in Fig. 3.28 and Fig. 3.29, can find that the charge on the capacitors Cf and Cf′ are different, it verify the inequality that we derive above. The gain-compensated situation only occurred during one half phase, the another half phase has no compensation. The double-sampled technique integrated the input voltage during both two half phase, so the sampling rate is twice as fast as the single-sampled technique. The effective DC gain is proportional to A2 /2. It makes the op-amp don’t need to be designed to a very high gain and also can reduce the power consumption. 39 Figure 3.22: The output voltage for a non-inverting SC integrator with no compensation shown in Fig. 3.6, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB Figure 3.23: The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.6, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB 40 Figure 3.24: The output voltage for a SC integrator that paper proposed shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB Figure 3.25: The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB 41 Figure 3.26: The output voltage for a SC integrator shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB Figure 3.27: The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=40dB 42 Figure 3.28: The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.19, k=1/8, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=20dB Figure 3.29: The transferred charge on the integration capacitor Cf , Cf′ shown in Fig. 3.16, fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=20dB 43 The simulation result shown in Fig. 3.22 is the output voltage of a double-sampled SC integrator with no gain compensation. It shows the magnitude for a sinusoidal input, and was derived by Eq.(3.37) that combined with a term of A. Compared the Fig. 3.24 with Fig. 3.26, which are the simulation results for a gain-compensated SC integrator that paper proposed and it’s modification that we proposed. We can find the accuracy for those two circuits are very approximate. It also can derived from Eq.(3.38) and Eq.(3.39) independently, that combine with a term of A2 . The charge transferred form sampling capacitor to the integrating capacitor was restricted by the op-amp finite gain. Here we reduce the op-amp finite gain to 20dB to see the difference of the charge that transferred between sampling and integrating capacitors shown in Fig. 3.28 and Fig. 3.29. The integrating capacitor that during compensated half phase have higher amplitude. Because it reduce the error voltage due to op-amp finite gain to 2Vout /A2 , then the stored charge on sampling capacitor can transferred to integrating capacitor more accuracy. However, the another one half phase don’t have gain compensation, because it was used to sample the errors. This is why only a half of phase can compensated the gain errors. As we can see, when the gain of op-amp is higher the charge during the two integrating paths will more closer shown in Fig. 3.25 and Fig. 3.27. The double-sampled gain-compensated SC integrators have the trade off between offset voltage and gain compensation, because it only have a half of phase to cancel the offset, however the input voltage always integrated at both two half phase. Although the double-sampled SC integrator cannot cancel the offset voltage completely, but it can use other auxiliary circuits to accomplish this purpose. There are some ways to reduce the offset voltage, which can be digital [5], or analog circuits [15]. Those circuits were proposed by papers and let the double-sampled gain-compensated technique can solve this problem more easier. The way that used to cancel the offset voltage, and reduce the flicker noise can be classified into two type. First, is the correlated double sampling(CDS) technique. Second, is the CHopper Stabilization(CHS) technique. The way that we use can be generalized to CDS, which can enhance the op-amp finite gain effectively. The another way of CHS technique can also makes offset voltage does not count anymore and flicker noise impact is highly reduced. But the disadvantage is that the effective gain is usually reduced[17], and usually used in continuous time system. The double-sampled gain-compensated technique is very useful and attractive in the application that need high gain and wide bandwidth. 44 3.3 A New Single-Sampled Gain-Compensated SC Integrator R2 R1 Cc1 F1 F2 Af F1 C c2 Cf F1 F2 F1 Cs F2 A Vin F1 F2 Cs Vout F2 F1 Cf C c2 F1 F2 Cc1 F1 Af R1 R2 Figure 3.30: A new single-sampled gain-compensated SC integrator The single-sampled and double-sampled gain-compensated SC integrators have been discussed above. In this section we proposed a new topology shown in Fig. 3.30 that use an additional op-amp and two compensated capacitors Cc1 and Cc2 to cancel the gain errors. The DC magnitude of the topology is ideally infinite, and can be described as follow. The circuit can be analyzed with three half consecutive phase, from (n − 3/2) to (n − 1/2). First, we assume the circuit start at the phase φ1 (n − 3/2) shown in Fig. 3.31(a). During this phase, the circuit integrated the input voltage to the output, and the errors due to op-amp finite gain also stored in the capacitors Cc1 and Cc2 . The charge in the Cc1 is three times of the charge in the Cc2 , because it was amplified by a feedback non-inverting op-amp. Next, the circuit switch to the phase φ1 (n − 1) shown in Fig. 3.31(b), the capacitors Cc1 and Cc2 are connect together, and the charge that have been stored during previous phase will make an average now. During third phase, the capacitor Cc2 will connect to the op-amp input and cancel the errors due to op-amp finite gain, then the input voltage can transferred to the capacitor Cf completely. The gain errors in this topology is ideally zero. Here we will derive the charge conservation at op-amp inverted input. 45 K Cf Cf Cc1 Cc1 C c2 VCs Cc2 Cs Cs A C c2 V- Vout A Vin Vout Cs Cc1 Cc1 Cc2 Cf K Cf (b) (a) Figure 3.31: A single-sampled gain-compensated SC integrator during (a) phase1 (b) phase2 First, when φ2 high, φ1 low, the charge on the capacitor Cc2 can be described as −Cc2 [ A1 Vout (n − 32 )] − KCc1 [ A1 Vout (n − 32 )] 3 QCc2 (n − ) = 2 2 (3.40) Where K is the closed loop gain of the feedback op-amp, and A is the op-amp finite gain. Second, when φ1 high, φ2 low, the charge conservation at node V − can be described as 1 − Cf [ Vout (n − A 1 = − Cf [ Vout (n − A 3 ) + Vout (n − 2 1 ) + Vout (n − 2 3 3 )] − Cs [Vin (n − 1)] + QCc2 (n − ) 2 2 1 1 1 1 1 )] − Cs [ Vout (n − )] − Cc2 [ Vout (n − )] 2 A 2 A 2 (3.41) Combining Eq.(3.40) and Eq.(3.41), and taking the z-transform, the overall transfer function can be expressed as −1 Cs z 2 Vout (z) H(z) = = 1 1 1 Vin (z) [ A Cf + A Cc2 + A Cs + Cf ] − [ A1 Cf + 1 (Cc2 2A + KCc1 ) + Cf ]z −1 (3.42) Assuming Cc1 = Cc2 = Cs = Cf , K=3, then the DC magnitude at z=1 can be expressed as |H(z)|z=1 = ∞ (3.43) Form Eq.(3.43) can find that the topology have infinite DC magnitude and have no pole error. It works like an ideal SC integrator under the assumption that the feedback op-amp can amplify the input voltage by a factor of three exactly. Here we use an macro op-amp model to construct the topology shown in Fig.3.30. Then an real op-amp will substitute for the macro model, and the simulation results will also discussed in next chapter. 46 A X Y β Figure 3.32: A simple feedback system In order to test the function of the topology, a 10kHz sinusoidal signal with amplitude of 1mv is applied to the topology. The sampling frequency is 10MHz, and the gain of the amplifier is 40dB. Then the output magnitude and phase of the topology is given by |H(z)|propose = | 6 z −1/2 | ≈ 154.52 (1 + A3 ) − z −1 (1 + A3 ) H(z)|propose ≈ −90 (3.44) ◦ Where the gain error is 3/A and pole error is zero. The simulation result shown in Fig. 3.33 is the output voltage of the topology. Compare to the circuit shown in Fig. 3.10, the phase error of the output signal was improved. The transfer function with no pole error is very attractive for the delta sigma modulator with MASH structure. The difficult of this topology is need to make the feedback op-amp can amplify the error voltage by a factor of three exactly. However, it is not difficult to have a precision value of a factor of three, because of the ”gain desensitization”. It can be described as [16] A 1 1 Y = ≈ (1 − ) X 1 + Aβ β βA (3.45) Where βA was called the ”loop gain”, which plays an important role in feedback system. We see from Eq.(3.45) the higher βA is the less sensitive Y /X will be to variations in A shown in Fig. 3.32. Here we take an example of the feedback system. Assuming the feedback factor β of the feedback amplifier is 1/2 and op-amp finite gain A is 70dB. Then the gain error 1/(βA) can be reduced to about 0.063%. The topology of the feedback op-amp is a single-end foldedcascode amplifier, and it can be designed to have a high gain. The DC magnitude of Eq.(3.43) with a finite gain feedback op-amp can be described as −1 |H(z)|z=1 z2 =| (1 + A3 ) − z −1 (1 + K+3 ) 2A |z=1 = 2A 3−K (3.46) Where the closed loop gain of the feedback op-amp can given by K= Af X = A Y 1 + 3f 47 (3.47) Combining Eq.(3.46) and Eq.(3.47), the DC magnitude can be described as |H(z)|z=1 = 2A · (3 + Af ) 9 (3.48) Where Af is the feedback op-amp finite gain shown in Fig. 3.30. From Eq.(3.48) we can find that the effective finite gain is the multiplication of the two opamps, A and Af . The conventional gain-compensated integrator used itself amplifier to achieve the effective gain of A2 . However, this topology shown in Fig. 3.30 used an additional feedback amplifier to get the effective gain of A · Af . The feedback amplifier was constructed of singleend topology, and can be achieve high gain easily. As we know, a traditional SC integrator was constructed with a single amplifier and sampling capacitors and integrating capacitors. If it was a gain-compensated topology, there will have additional compensation capacitors. The primary op-amp in the SC integrator need to deal with the input signal, and should be designed with high gain and wide bandwidth. However, there is a trade off when design a high gain and wide bandwidth amplifier. In this topology, we can design the primary amplifier for lower gain, and the feedback amplifier to have higher gain. Although the traditional gain-compensated SC integrator and the topology that we proposed are both can get a high effective gain of op-amp. However, the topology that used an auxiliary feedback amplifier is more attractive, because it can enhance the SC integrator DC gain with an additional op-amp and the whole circuit with no stable problem. After a careful analysis including the op-amp finite gain, here we describe the gain error of this circuitry. The output voltage in the z-domain can given by Vout (z) = Hi (z)E(z)Vi (z) (3.49) Where Hi (z) is the ideal transfer function, E(z) is the error transfer function, and is given by −1 z2 Hi (z) = 1 − z −1 E(z) = 1 − z −1 (1 + A3 ) − z −1 (1 + (3.50) K+3 ) 2A The error function magnitudes was computed as |1 − E|. Here we use a SC integrator with no compensation to compare with this topology and shown in Fig. 3.34. As it demonstrates, the gain-compensated topology has better magnitude accuracy. 48 Figure 3.33: The output voltage for a SC integrator shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=40dB, and Af = 80dB 0 SC Integrator With No Gain Compensation (|1−E|) Single−sampled Gain−Compensated SC Integrator (|1−E|) Magnitude Error (dB) −10 −20 −30 −40 −50 −60 0 200 400 600 800 1000 1200 Op−Amp DC Gain 1400 1600 1800 2000 Figure 3.34: Magnitude errors of the integrator for Cs = Cf = Cc1 = Cc2 , fin = 10kHz, and fs = 10MHz 49 The error transfer function of Eq. (3.50) can also be described as E(z) = 1 3 1+ A (1 − z −1 ) 9+6A 1− z −1 1+ 2A(3+Af f) = 1 3 1+ A (1 − z −1 ) (3.51) 1 − z −1 (1 − Epole ) 3 1+ A Where the pole error of Eq. (3.51) is given by Epole = 3− 9+6Af 6+2Af A+3 = 9 (A + 3)(2Af + 6) (3.52) Compare to the conventional single-sampled gain-compensated integrator shown in Fig. 3.10, where the pole error is 2 . A2 The pole error of Eq. (3.52) is inverse proportional to the gain of A · Af . The comparison between both the two topology is shown in Fig. 3.35, the pole error can be reduced by increasing a feedback amplifier. It is very useful on the application of sigma delta modulator with MASH structure. 20 Pole Error of Conventional Gain Compensated Integrator Pole Error of New Gain Compensated Integrator (Af = 66dB) 0 Pole Error of New Gain Compensated Integrator (Af = 69dB) Magnitude of Pole Error (dB) −20 −40 −60 −80 −100 −120 −140 0 200 400 600 800 1000 1200 Op−Amp DC Gain 1400 1600 1800 2000 Figure 3.35: Magnitude of pole errors for conventional circuit and new gain-compensated topology 50 3.4 Simulation And Results In order to construct the new topology of Fig. 3.30, here we use a folded-cascode fully differential amplifier with a gain 50dB to substitute the op-amp on the signal path. The feedback amplifier was constructed with a current feedback single-end amplifier. This type have high gain and high speed. One of this op-amp’s advantages is its closed-loop gain can be changed, when used in the feedback application, without significantly affecting its loop gain [4]. Additionally, this current feedback op-amp use of an output buffer for resistive feedback network. Here, we construct it with a gain of 60dB. The sampling and integrating capacitors are all 1pf. All of the switches would be realized by n-channel transistors only, expect for the switches connected to the outputs, which was realized by transmission gate to accommodate a wider signal swing. The resistance of the transmission gate is about 800Ω. In order to test the topology, we give a sinusoidal input with different frequency, then examine the output signal. The ratio of input signal frequency over sampling frequency, OSR, should be selected advisably to prevent the op-amp’s output swing distortion. Here, the sampling frequency is 10MHz and the input frequency is 10KHz or even larger. The results were verified by simulation results, and used TSMC standard 0.35µm CMOS technology to implement. 3.4.1 Operational Amplifier And Common Mode Feedback The fully differential analog circuits are used throughout the modulators for two reasons. First, a fully differential topology provides for high rejection of common-mode disturbances, such as common-voltage offset, supply and substrate noise. Second, for a given voltage range, a differential signal has twice the amplitude of a single-ended signal. A fully differential folded-cascode operational amplifier shown in Fig. 3.36. The output swing of this amplifier can be greater than a direct stack of transistors. The output swing of the op-amp is determined by the cascode NMOS, M7 and M8 , and by the cascode PMOS, M9 and M10 . For proper operation, all transistors should be operating in a saturation region. The new gain-compensated SC integrator operate in 10MHz sampling frequency. To make sure it has enough settling time for 1% accuracy. From Eq. (2.29) we can know the op-amp should have at least 60MHz unit-gain-bandwidth (UGB) where β = 1/3. The op-amp also need a common-mode feedback, a constant current bias circuit, and they will also be discussed at next. From MOS current equation, the overdrive voltage can given by 51 VDD Vbp1 M4 M11 M12 Vbp2 M3 M9 M10 out V Vin+ M1 M2 Vin- + Vout Vcm Vbn2 M7 M8 C1 Vbn1 Vctr M5 F2 F2 F1 C2 F1 F1 C2 F1 F2 Vcm C1 F2 Vbn1 M6 VSS Figure 3.36: A fully differential folded-cascode operational amplifier with common-mode feedback ID = µCOX W 2 µCOX W (VGS − Vt )2 = V 2 L 2 L DS,sat s 2ID L ⇒ VDS,sat = µCOX W (3.53) (3.54) The cascode devices operated in the saturation region limit the output swing of the op-amp. From Fig.3.36 can derive small-signal parameters of the op-amp. The output impedance is given by Rout ≈ [gm8 ro8 (ro2 //ro6 )]//[gm10 ro10 ro12 ] (3.55) The open loop gain is given by A = −gm1 Rout (3.56) If the second pole is behind of the unity-gain frequency, then the unit-gain-bandwidth of the amplifier is derived by |A(s)| = |gm1 (Rout // gm1 1 )| ≈ | |=1 sCL sCL 52 (3.57) ⇒ ωU GB = gm1 CL (3.58) Where CL is the op-amp output load capacitance, ωU GB is the unit-gain-bandwidth. The load capacitance will create a dominant pole at a frequency ωU GB = gm1 = gm1 Rout ωp1 CL ⇒ ωp1 = 1 Rout CL (3.59) (3.60) Where ωp1 is the op-amp dominant pole frequency. For better speed, N-channel devices should be chosen for the input pair, because of their higher mobility. Since the unit-gain-bandwidth of the op-amp is determined by the ratio of the transconductance of the input device to the output load capacitance. But the P-channel devices have better noise performance. Typically, P-channel transistors have less flicker noise than N-channel transistors. In CMOS P-substrate fabrication, P-channel transistors are isolated substrate-noise by n-well protection. For low noise and high accuracy consideration, we choose P-channel transistors as input devices. The mobility of the input devices can be compensated by increasing the width of the PMOS. The flicker noise is inversely proportional to the transistor area, (W ·L) [16]. The PMOS has less flicker noise than NMOS, if they have the same mobility. Here we choose the PMOS transistor as the input devices of op-amp. From Eq.(3.58) can find that the op-amp could be made fast by increasing the width and bias current of the input devices. However, to maintain stability, all concomitant poles must occur at the frequencies higher than the unit-gain-bandwidth of the op-amp. Therefore, the speed of op-amp is limited by the location of the first non-dominant pole. The pole is given by ωp2 = gm8 Cs8 (3.61) It is the ratio of the transconductance of the cascode N-channel devices to the total capacitance on its source. The non-dominant-pole frequency can be increased by increasing the current density through the cascode device M8 . The common mode output level of the amplifier is maintained by the SC feedback circuitry also shown in Fig. 3.36. The common-mode feedback (CMFB) circuit is based on the use of SC circuits. In this approach, capacitor C2 generate the average of the output voltage, which is used to create control voltage for the op-amp output current sources, M5 and M6 . This circuit acts like a simple SC low-pass filter having a DC input signal. The bias voltage is designed to be equal to the difference between the desired common-mode voltage, Vcm , and the desire control voltage, Vctr used for the op-amp current source. The capacitor C2 form a voltage divider to 53 VDD Vbp1 Vbp2 M8 M7 M11 M9 M6 M10 M14 VSS Vbn2 Vbn1 M3 M4 M1 M13 M5 M15 M16 M17 M12 M2 M18 Rb VSS Bias Loop Cascode Bias Strat-up Figure 3.37: A wide-swing constant transconductance bias circuit drive node Vctr , the gates of the NMOS current source transistors in the output stage. If the + − voltage Vout and Vout raise, the Vctr also raise to keep the charge of C1 at the same time. It increase the NMOS current source and reduce the output common mode voltage. The bias circuit of the op-amp is implemented by incorporating wide-swing current mirrors into the constant-transconductance bias is shown in Fig. 3.37. The circuit includes wide swing cascode current mirrors, stable transconductance bias circuit, and a start-up circuit [4]. The bias circuit is presently becoming the most popular CMOS bias circuit. The stable transconductance bias is provided by the resistor Rb and transistors M1 , M2 in the bias loop shown in Fig. 3.37. If (W/L)7 and (W/L)8 is the same. The equality results M1 and M2 of the circuit having the same current due to the current mirror pair M7 , M8 . The loop consisting of M1 , M2 and Rb , can obtain VGS2 = VGS1 + ID1 Rb 54 (3.62) Subtract the threshold voltage Vt from both sides can get VGS2 − Vt = VGS1 − Vt + ID1 Rb The Eq.(3.63) can be rewritten as s s 2ID2 2ID1 = + ID1 Rb µn Cox (W/L)2 µn Cox (W/L)1 (3.63) (3.64) Since ID1 =ID2 , Eq.(3.64) can also be written as We also know that 2 p (1 − 2µn Cox (W/L)2 ID2 gm2 = s (W/L)2 ) = Rb (W/L)1 p 2µn Cox (W/L)2 ID2 (3.65) (3.66) From Eq.(3.65) and Eq.(3.66), can obtain gm2 2 = (1 − Rb s (W/L)2 ) (W/L)1 (3.67) The transconductance of M2 is determined by the ratio of M1 and M2 size only. It is independent of power supply voltage, process parameter, temperature, or any other parameters with large variation. For special case of (W/L)1 = 4(W/L)2 , can simplified Eq.(3.67) as gm2 = 1 Rb (3.68) The circuit is necessary to add a start-up circuit that only affects the operation if all the currents are zero at start up. The start-up circuit consists of transistors M15 , M16 , M17 , and M18 . In the state that all currents in the bias loop and cascode bias are zero, the gate voltage of M17 would close to Vss , and M17 would be turn off. We assume the aspect ratio (W/L)18 is very small, so the output impedance of M18 would be very large. Since the M18 operates as a high-impedance load is always on. The gates voltage of M15 and M16 would be pulled up. The transistors M15 and M16 will inject currents into M9 and M14 , respectively, which will start up the bias loop. Once the loop start up, the bias voltages, Vbp1 , Vbp2 , Vbn1 , and Vbn2 , would settle to a stable state, then M17 would turn on and sinking all the current from M18 . Then M18 operates in the saturation region and M17 operates in the triode region. This pull down the gate voltage of M15 and M16 and thereby turns them off so no longer affect the bias circuit. The frequency response of the fully differential folded-cascode op-amp simulated by HSPICE is shown in Fig. 3.38. The transient response of the bias circuit is shown in Fig. 3.39, and it start up at t=200 ns. Then the simulated performance is summarized in Table 3.1. 55 (a) (b) Figure 3.38: The frequency response of the fully differential folded-cascode amplifier (a) 50dB magnitude (b) 88◦ phase margin Figure 3.39: Simulation of bias output voltage 56 DC Gain Phase Margin Slew rate Supply Voltage 50 dB Load ◦ 88 Unit-gain Frequency 23.9 V /µs Power 3.3 V Process 2 pF 63.1 MHz 1.21 mW 0.35 µm 2P 4M Table 3.1: Simulated summary of the fully differential folded-cascode amplifier Single-End Op-Amp VDD M4 Vbp1 M11 M3 Vbp2 M9 M12 Vbn2 M10 M15 M13 CC Vin+ M1 M2 Vin- Vout M14 M16 Vbn2 M7 M8 Vbn1 M5 M6 VSS Figure 3.40: Single-end folded-cascode op-amp with output buffer A single-end op-amp shown in Fig. 3.40 with buffer circuit is used to isolate the op-amp from the load. The load can be resistive, capacitive or a combination of the two. Capacitor Cc is used to compensated the circuit with a technique called ”Miller compensation”. However, it will cause a zero at right-hand plane, and the stability degrades considerably. The gate-drain connected MOSFETs M13 and M14 can be though of as zero-canceling resistors, which used to shift the right-hand plane zero into the left-hand plane [1]. The current through M13 and M14 is well defined, and increase the lengths of them can push the zero further into the left-half plane. Normally, since the gain of the output buffer can be low, the output MOSFETs, M15 and M16, can be sized with minimum or near-minimums lengths. The frequency response shown in FIg. 3.41 has 60 dB magnitude and 84◦ phase margin. 57 ( a) (b) Figure 3.41: The frequency response of a single-end folded-cascode op-amp (a) 60dB magnitude (b) 84◦ phase margin 3.4.2 Switch The speed of the sampling circuit is an important factor to influence the harmonic distortions of the integrator. Since the output voltage of the sampling circuit speed would take infinite time to become equal Vin . We consider the output voltage Vout settled when it is within a certain error band, △V , around the final value. Thus, the speed specification must be accompanied by an accuracy specification as well. The source and drain voltages to be approximately equal after switch turns on ts seconds shown in Fig. 3.42. The speed of a sampling circuit is given by two factors, the on-resistance of the switch and the sampling capacitor Cs . In order to achieve higher speed, a large W/L and small capacitor should be used. However, the on-resistance depends on the input level shown in Fig. 3.44. In the case of NMOS switch, the time constant is proportional to the increasing positive input voltage. In Fig. 3.42, for Vout ≈ Vin , the transistor must operate in deep triode region and hence the upper bound of Vin equals VDD − Vt . Thus, we can obtain the on-resistance 1 1 Vds = = Ron,n = W W Id µn Cox L (Vgs − Vtn ) µn Cox L (VDD − Vin − Vtn ) 58 (3.69) Vctrl Vctrl VDD Vout Vin t 0 Vout Cs ΔV Vin ts 0 t Figure 3.42: Definition of speed in a sampling circuit for NMOS switch The on-resistance of the switch shown in Fig. 3.44 as a function of the input level. In the figure, for a NMOS switch, the sharp rise as Vin approaches VDD − Vt . The device threshold voltage directly limits the input voltage swings. In order to accommodate greater voltage swings in the sampling circuit, we can observe a PMOS switch exhibits a on-resistance that decrease as the input voltage becomes more positive. Then, it is reasonable to employ a transmission gate shown in Fig.3.43 as the sampling switch at the input of integrators. The transmission gate allows rail-to-rail swings, and produce an equivalent resistance which can be described as Ron,eq =Ron,n k Ron,p = = 1 µn Cox ( W ) (V L n DD − Vin − Vtn ) k 1 µp Cox ( W ) (V L p in − Vtp ) (3.70) 1 µn Cox ( W ) (V L n DD − Vtn ) − [µn Cox ( W ) L n − µp Cox ( W ) ]V − µn Cox ( W )V L p in L p tp From Eq.(3.71), if µn Cox ( W W )n = µp Cox ( )p L L (3.71) The Ron,eq is independent to the input signal level. The turn on resistance of the transmission gate is shown in Fig. 3.44, it has less variation than the corresponding to only a NMOS or PMOS switch alone. In order to prevent the incomplete settling noise in the integrator, the sampling and integrating times of the integrator should be at least five times the RC time constant for a 1% accuracy shown in Fig. 3.43. It can express as, Ts is sampling period 1 Ts Ron,eq · Cs < ( ) 5 2 59 (3.72) Vctrl Vout ΔV Vin Vin Vout 0 Vctrl Cs ts t VDD Vctrl 0 t Figure 3.43: Definition of speed in a sampling circuit for Transmission gate Figure 3.44: Comparison of on-resistance of switch 3.4.3 Simulations Of A New Single-End Gain-Compensated Integrator In order to test the new SC integrator, a 10kHz sinusoidal signal with amplitude of 1mv is applied to the topology, and the sampling frequency is 10MHz. The Fig. 3.47 ∼ Fig. 3.53 show its output voltage with different input frequency. The Fig. 3.45 and Fig. 3.49 show a conventional non-inverting SC integrator with no compensation to make a comparison with the new topology. The Fig. 3.53 is the post layout simulation with 10KHz input frequency , and is approximate to the pre-simulation shown in Fig. 3.47. The Fig. 3.54 shows a comparison between real circuit and ideal one, and the results also conform to the specifications. 60 Figure 3.45: The output voltage for a SC integrator with no compensation shown in Fig. 3.1(a), fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=50dB Figure 3.46: The FFT of the output voltage for a SC integrator with no compensation shown in Fig. 3.1(a), fin = 10kHz with amplitude 1mV, fs = 10MHz, and A=50dB 61 Figure 3.47: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB Figure 3.48: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB 62 Figure 3.49: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 20kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB Figure 3.50: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 20kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB 63 Figure 3.51: The output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 30kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB Figure 3.52: The FFT of the output voltage for a SC integrator that we proposed shown in Fig. 3.30, fin = 30kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB 64 Figure 3.53: The post simulation for a SC integrator that we proposed, fin = 10kHz with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB 160 The Magnification of Math Derivation The Magnification of HSPICE Simulation 140 Magnitude 120 100 80 60 40 20 1 1.5 2 2.5 3 Input Frequency (Hz) 3.5 4 4.5 5 4 x 10 Figure 3.54: The magnification for a SC integrator that we proposed by varying the input frequency shown in Fig. 3.30, with amplitude 1mV, fs = 10MHz, A=50dB, and Af = 60dB 65 Figure 3.55: Layout photo of the new gain-compensated switched capacitor integrator 66 Chapter 4 Conclusion A new SC integrator for compensating the effect of op-amp finite gain is designed and realized in this thesis. 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