Download Lecture 03

ECE 342
Solid-State Devices & Circuits
3. CMOS
Jose E. Schutt-Aine
Electrical & Computer Engineering
University of Illinois
[email protected]
ECE 342 – Jose Schutt-Aine
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Complementary MOS
•
CMOS Characteristics
– Combine nMOS and pMOS transistors
– pMOS size is larger for electrical symmetry
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CMOS
• Advantages
– Virtually, no DC power consumed
– No DC path between power and ground
– Excellent noise margins (VOL=0, VOH=VDD)
– Inverter has sharp transfer curve
• Drawbacks
– Requires more transistors
– Process is more complicated
– pMOS size larger to achieve electrical symmetry
– Latch up
ECE 342 – Jose Schutt-Aine
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MOSFET Switch
NMOS
•
PMOS
Characteristics of MOS Switch
– MOS approximates switch better than BJT in off state
– Resistance in on state can vary from 100 W to 1 kW
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CMOS Switch
CMOS switch is called an inverter
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CMOS Switch – Off State
•
OFF State (Vin: low)
– nMOS transistor is off
– Path from Vout to V1 is through PMOS Vout: high
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CMOS Switch – On State
•
ON State (Vin: high)
– pMOS transistor is off
– Path from Vout to ground is through nMOS Vout: low
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CMOS Inverter
rdsn 
1
W 
k N'   VDD  VT 
 L n
rdsp 
1
W 
k P'   VDD  VT 
 L p
Short switching
transient current
 low power
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Digital Circuits
VIH: Input voltage at high state  VIHmin
VIL: Input voltage at low state  VILmax
VOH: Output voltage at high state  VOHmin
VOL: Output voltage at low state  VOLmin
Likewise for current we can define
Currents into input
Currents into output
IIH  IIHmax
IIL  IILmax
IOH  IOHmax
IOL  IOLmax
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Voltage Transfer Characteristics (VTC)
The static operation of a logic circuit is determined by its VTC
•
In low state: noise margin is
NML
NM L  VIL  VOL
•
In high state: noise margin is
NMH
NML
NM H  VOH  VIH
•
An ideal VTC will maximize noise
margins
Optimum:
NMH
VIL and VIH are the points where the
slope of the VTC=-1
NM L  NM H  VDD / 2
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Switching Time & Propagation Delay
input
output
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Switching Time & Propagation Delay
tr=rise time (from 10% to 90%)
tf=fall time (from 90% to 10%)
tpLH=low-to-high propagation delay
tpHL=high-to-low propagation delay
Inverter propagation delay:
1
t p   t pLH  t pHL 
2
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VTC and Noise Margins
For a logic-circuit family employing a 3-V supply, suggest an
ideal set of values for Vth, VIL, VIH, VOH, NML, NMH. Also, sketch
the VTC. What value of voltage gain in the transition region
does your ideal specification imply?
Ideal 3V logic implies:
VOH  VDD  3.0V ;
VOL  0.0V
Vth  VDD / 2  3.0 / 2  1.5V ;
VIL  VDD / 2  1.5V ; VIH  VDD / 2  1.5V
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VTC and Noise Margins
NM H  VOH  VIH  3.0  1.5  1.5V
NM L  VIL  VOL  1.5  0.0  1.5V
Inverting transfer characteristics
The gain in the transition region is:
VOH  VOL  / VIH  VIL    3.0  0.0  / 1.5  1.5
 3/ 0  V /V
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CMOS Noise Margins
When inverter threshold is at VDD/2, the noise margin NMH and NML are
equalized
3
2 
NM H  NM L   VDD  Vth 
8
3 
NMH: noise margin for high input
NML: noise margin for low input
Vth: threshold voltage
Noise margins are typically around 0.4 VDD; close to half power-supply voltage 
CMOS ideal from noise-immunity standpoint
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Switching Circuit
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Nonideal Switch
Vlow  V1
Rsc
Rsc  RL
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Vhigh  V1
Rso
Rso  RL
17
IV Characteristics of Switches
Non-ideal switch
Ideal switch
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Complementary Switches
Vlow
Rsc
 V1
Rsc  Rso
ECE 342 – Jose Schutt-Aine
Vhigh
Rso
 V1
Rso  Rsc
19
Problem
A switch has an open (off) resistance of 10MW and
close (on) resistance of 100 W.
Calculate the two voltage levels of Vout for the circuit
shown. Assume RL=5 kW
Vout
VCC RS

RL  RS
Open : RS  10 106 W  Vout  5V
Short : RS  102 W  Vout
5 102

 0.098V
5000  100
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Problem
If two switches are used as shown, calculate the two output voltage
levels. Assume switches are complementary
RS on  100 W , RS off  10 M W
VCC RS 2
Vout 
RS 1  RS 2
State 1: S1 off, S2 on
RS1=10 MW, RS2=100 W
Vout
5  100

 5V  0V
6
10  10  100
State 2: S1 on, S2 off
RS1=100 W, RS2=10 MW
Vout
5 10 106
5 107

 7
6
10 10  100 10  100
ECE 342 – Jose Schutt-Aine
5V
21
MOSFET Switch
NMOS
•
PMOS
Characteristics of MOS Switch
– MOS approximates switch better than BJT in off state
– Resistance in on state can vary from 100 W to 1 kW
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NMOS Switch
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CMOS Switch
CMOS switch is called an inverter
The body of each device is connected to its source  NO BODY EFFECT
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CMOS Switch – Off State
•
OFF State (Vin: low)
– nMOS transistor is off
– Path from Vout to V1 is through PMOS Vout: high
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CMOS Switch – Input Low
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CMOS Switch – Input Low
NMOS
VGSN  VTN  OFF
rdsn high
PMOS
rdsp 
1
W 
k   VDD  VTP
 L p
'
p

rdsp is low
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CMOS Switch – On State
•
ON State (Vin: high)
– pMOS transistor is off
– Path from Vout to ground is through nMOS Vout: low
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CMOS Switch – Input High
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CMOS Switch – Input High
NMOS
rdsn 
1
W 
k   VDD  VTN 
 L n
'
n
rdsn is low
PMOS
VGSP  VTP  OFF
rdsp high
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CMOS Inverter
rdsn 
1
W 
k N'   VDD  VT 
 L n
rdsp 
1
W 
k P'   VDD  VT 
 L p
Short switching
transient current
 low power
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CMOS Inverter
Advantages of CMOS inverter
 Output voltage levels are 0 and VDDsignal swing is
maximum possible
 Static power dissipation is zero
 Low resistance paths to VDD and ground when needed
 High output driving capability increased speed
 Input resistance is infinite high fan-out
Load driving capability of CMOS is high.
Transistors can sink or source large load
currents that can be used to charge and
discharge load capacitances.
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CMOS Inverter VTC
QP and QN are
matched
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CMOS Inverter VTC
Derivation






Assume that transistors are matched
Vertical segment of VTC is when both QN and QP are saturated
No channel length modulation effect  l = 0
Vertical segment occurs at vi=VDD/2
VIL: maximum permitted logic-0 level of input (slope=-1)
VIH: minimum permitted logic-1 level of input (slope=-1)
To determine VIH, assume QN in triode region and QP in saturation region
1 2 1
2
 vI  Vt  vo  vo  VDD  vI  Vt 
2
2
Next, we differentiate both sides relative to vi
dvo
dvo
 vI  Vt   vo  vo   VDD  vI  Vt 
dvI
dvI
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CMOS Inverter VTC
Substitute vi=VIH and dvo/dvi = -1
VDD
vo  VIH 
2
After substitutions, we get
1
VIH   5VDD  2Vt 
8
Same analysis can be repeated for VIL to get
1
VIL   3VDD  2Vt 
8
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CMOS Inverter Noise Margins
1
VIH   5VDD  2Vt 
8
1
VIL   3VDD  2Vt 
8
1
NM H   3VDD  2Vt 
8
1
NM L   3VDD  2Vt 
8
Symmetry in VTC  equal
noise margins
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Matched CMOS Inverter VTC
CMOS inverter can be made to switch at specific threshold voltage by
appropriately sizing the transistors
n  W 
W 
  
 
 L  p  p  L n
Symmetrical transfer
characteristics is obtained via
matching  equal current driving
capabilities in both directions
(pull-up and pull-down)
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VTC and Noise Margins - Problem
An inverter is designed with equal-sized NMOS and PMOS
transistors and fabricated in a 0.8-micron CMOS technology
for which kn’ = 120 A/V2, kp’ = 60 A/V2, Vtn =|Vtp|=0.7 V, VDD
= 3V, Ln=Lp = 0.8 m, Wn = Wp = 1.2 m, find VIL, VIH and the
noise margins.
Equal sizes NMOS and PMOS, but kn’=2kp’
Vt = 0.7V
For VIH: QN in triode and QP in saturation
1 2 1 ' W 
2
W  
k   VI  Vt Vo  Vo   k p   VDD  VI  Vt 
2  2  L p
 L n 
'
n
ECE 342 – Jose Schutt-Aine
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VTC and Noise Margins – Problem (cont’)
4 VI  Vt Vo  2V  VDD  VI  Vt 
2
o
2
(1)
Differentiating both sides relative to VI results in:
Vo
Vo

: 4 VI  Vt 
 4Vo  4Vo
 2 VDD  VI  Vt  (1)
VI
VI
VI
Substitute the values together with:
VI  VIH
Vo
and
 1
VI
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VTC and Noise Margins – Problem (cont’)
4 VIH  0.7  1  4Vo  4Vo  2 VIH  3  0.7 
8Vo  7.4
VIH 
 1.33Vo  1.23
6
(2)
From (1) : 4 VIH  0.7 Vo  2V   3  VIH  0.7 
2
o
4 VIH  0.7 Vo  2V   2.3  VIH 
2
o
2
2
(3)
solving (2) & (3) : 1.55V  4.97Vo  1.14  0
2
o
 Vo  0.22 V
VIH  1.52 V
ECE 342 – Jose Schutt-Aine
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VTC and Noise Margins – Problem (cont’)
For VIL: QN is in saturation and QP in triode
1 ' W 
1
2
2
' W  
kn   VI  Vt   k p   VDD  VI  Vt VDD  Vo   VDD  Vo  
2  L n
2
 L p 

VI  0.7 
VI  0.7 
2
2
1
2
  3  VI  0.7   3  Vo    3  Vo 
2
(1)
1
2
  2.3  VI   3  Vo    3  Vo 
2
 Vo 
Vo

 2 VI  0.7    2.3  VI   

3

V

3

V
 o
 
o
VI
VI
 VI 
ECE 342 – Jose Schutt-Aine
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VTC and Noise Margins – Problem (cont’)
Vo
VI  VIL and
 1
VI
2VIL  1.4  2.3  VIL  3  Vo  3  Vo
2
VIL  Vo  1.15
3
1
2
From (1) : VIL  0.7    2.3  VIL   3  Vo    3  Vo 
2
1
2
2
 0.66Vo  1.85   3.45  0.66Vo  3  Vo   3  Vo 
2
2
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VTC and Noise Margins – Problem (cont’)
Vo  2.96 V
VIL  0.81V
Noise Margins:
NM H  3  1.52  1.48 V
NM L  0.81  0  0.81V
Since QN and QP are not matched, the VTC is not
symmetric
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CMOS Dynamic Operation
 Exact analysis is too tedious
 Replace all the capacitances in the circuit by a single
equivalent capacitance C connected between the output
node of the inverter and ground
 Analyze capacitively loaded inverter to determine
propagation delay
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CMOS – Dynamic Operation
C  2Cgd 1  2Cgd 2  Cdb1  Cdb 2  Cg 3  Cg 4  Cw
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CMOS – Dynamic Operation
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CMOS Dynamic Operation
Need interval tPHL during which vo reduces from VDD to
VDD/2
I avtPHL  C VDD  VDD / 2 
Which gives
t PHL
CVDD

2 I av
Iav is given by
1
I av  iDN  E   iDN  M  
2
ECE 342 – Jose Schutt-Aine
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CMOS Dynamic Operation
where
1 ' W 
2
iDN  E   kn   VDD  Vtn 
2  L n
and
2

 VDD  1  VDD  
' W 
iDN  M   kn   VDD  Vtn  
 
 
 L n 
 2  2  2  
this gives
t PHL 
 nC
kn' W / L n VDD
ECE 342 – Jose Schutt-Aine
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CMOS Dynamic Operation
Where n is given by
n 
2
 7 3V  V 2 
  tn   tn  
 4 VDD  VDD  
Likewise, tPLH is given by
tPLH 
 pC
k W / L  p VDD
'
p
with
p 
2
 7 3 Vtp
Vtp

 
 4 VDD VDD
ECE 342 – Jose Schutt-Aine
2



49
CMOS Dynamic Operation
and tp is given by
1
t P   t PHL  t PLH 
2




Components can be equalized by matching transistors
tP is proportional to C reduce capacitance
Larger VDD means lower tp
Conflicting requirements exist
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CMOS – Propagation Delay
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CMOS – Propagation Delay
Capacitance C is the sum of:
– Internal capacitances of QN and QP
– Interconnect wire capacitance
– Input of the other logic gate
t PHL
1.6C
 '
kn W / L n VDD
To lower propagation delay
–
–
–
–
Minimize C
Increase process transconductance k’
Increase W/L
Increase VDD
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CMOS Inverter Problem
A CMOS inverter for which kn=10 kp=100 A/V2 and Vt =0.5 V
is connected as shown to a sinusoidal signal source having a
Thevenin equivalent voltage of 0.1-V peak amplitude and
resistance of 100 kW. What signal voltage appears at node A
with vI = +1.5 V and vI = -1.5 V?
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CMOS Inverter Problem (cont’)
For vI = 1.5 V, the NMOS operates in the triode region
while the PMOS is off.
rDSn
1
1


 10 k W
6
kn  vI  Vt  100  10 1.5  0.5
100 103 104
vA 
 9.09 mV
4
5
10  10
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CMOS Inverter Problem (cont’)
For vI = -1.5 V, the PMOS operates with
rDSP 
1
k p  vI  Vt 

1
100  106
1.5  0.5
10
100 103 105
vA 
 50 mV
5
5
10  10
ECE 342 – Jose Schutt-Aine
 105 W
55
Propagation Delay - Example
Find the propagation delay for a minimum-size inverter for
which kn’=3kp’=180 A/V2 and (W/L)n = (W/L)p=0.75 m/0.5
m, VDD = 3.3 V, Vtn = -Vtp = 0.7 V, and the capacitance is
roughly 2fF/mm of device width plus 1 fF/device. What does tp
become if the design is changed to a matched one? Use the
method of average current.
Solution
2
 7 3V  V 2 


7
3

0.7
0.7


 n  2   tn   tn    2  

   1.73
3.3
 3.3  
 4 VDD  VDD  
 4
1.73   2 fF  0.75  1 fF 
 nC
t PHL  '

0.75
kn W / L n VDD
6
180  10 
 3.3
0.5
13.38
ECE 342 – Jose Schutt-Aine
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Propagation Delay - Example
tPHL  4.85 ps
Since Vtn  Vtp , then  n   p  1.73
W  W 
We also have      , hence
 L n  L  p
'
kn
t PLH  t PHL  '  4.85  3  14.55 ps
kn
t PLH
1
1
  t PHL  t PLH    4.85  14.55  9.7 ps
2
2
ECE 342 – Jose Schutt-Aine
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Propagation Delay - Example
If both devices are matched, then
k p'  kn'
tPLH  tPHL
and
1
t p   t PHL  t PLH   t PHL  4.85 ps
2
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CMOS – Dynamic Power Dissipation
In every cycle
– QN dissipate ½ CVDD2 of energy
– QP dissipate ½ CVDD2 of energy
– Total energy dissipation is CVDD2
If inverter is switched at f cycles per second, dynamic
2
power dissipation is: PD  fCVDD
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Power Dissipation - Example
In this problem, we estimate the inverter power dissipation
resulting from the current pulse that flows in QN and QP when
the input pulse has finite rise and fall times. Let Vtn=-Vtp=0.5 V,
VDD = 1.8V, and kn=kp=450A/V2. Let the input rising and
falling edges be linear ramps with the 0-to-VDD and VDD-to-0
transitions taking 1 ns each. Find Ipeak.
13.44
ECE 342 – Jose Schutt-Aine
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Power Dissipation - Example
To determine the energy drawn from the supply per transition,
assume that the current pulse can be approximated by a
triangle with a base corresponding to the time for the rising or
falling edge to go from Vt to VDD-Vt, and the height equal to
Ipeak. Also, determine the power dissipation that results when
the inverter is switched at 100 MHz.
ECE 342 – Jose Schutt-Aine
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Power Dissipation - Example
2
I Peak
1
 W   VDD

 nCox   
 Vtn 
2
 L n  2

I Peak
1
 A  1.8

 450 2 
 0.5   36 A
2
V  2

2
ECE 342 – Jose Schutt-Aine
62
Power Dissipation - Example
The time when the input reaches Vt is:
0.5
1 ns  0.28 ns
1.8
The time when the input reaches VDD - Vt is:
1.8  0.5
 1 ns  0.72 ns
1.8
The base of the triangle is
t  0.72  0.28  0.44 ns wide
ECE 342 – Jose Schutt-Aine
63
Power Dissipation - Example
1
1
E  I Peak  VDD  t   36 A  1.8  1.44 ns
2
2
E  14.3 fJ
P  f  E  100 106 14.3 1015  1.43 W
ECE 342 – Jose Schutt-Aine
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