Download 03 Circuit Analyze, Signals, Timing Diagrams

Circuit Analyze. Clocks, Signals, Timing Diagrams.
John F. Wakerly – Digital Design. 4th edition. Chapter 3.


Goal – Teach students the basics of circuit analyze, timing diagrams and race conditions.
Learning outcome - by the end of this class the students should be able to create a simple
timing diagram (without delay or race conditions) for any simple schematic.
Introduction
Combinational or Sequential logic schematics show the circuit’s hardware implementation and
give us some knowledge about the functions of the circuit.
The exact behavior of circuit sometimes cannot be described looking at the schematic.
On the schematic there is no the way to show how the circuit behaves when the inputs are
changed – what we have on output when there are dynamic or static changes on inputs.
This is especially necessary when we want to take in account the real hardware physical
parameters, particularly signal delays on circuits caused by parasitic capacitances or resistances.
To describe the circuit in more details and to show the output state depended on input
dynamic changes we use Timing Diagrams.
Timing Diagram Example. One variable - A:
Signal,
Voltage
axis
Signal
Signal’s level is Logical 1
A
Signal’s level is Logical 0
Time axis
Above is a timing diagram for Variable A.
 At the beginning of experiment the value of A is logical “1”
 After some time the value is changed to logical “0”
 The circuit implementation logic has positive logic when:
o Logical “1” is represented as high voltage or as high level signal.
o Logical “0” is represented as low voltage or as low level signal.
 The abscissa shows the time progress
 The ordinate shows the signal level (voltage).
Another Timing Diagram Example – More professional. Two variables - A
and B.
A
B
Above is a timing diagram for Variables A and B.
 At the beginning of experiment the value of A=1, the value of B=0
 After some time the values are changed A = 0, B=1
 The axes are not shown. It is up to necessity to show them or not.
Clock Example:
Clock’s period.
Signal exists
No Signal
C1
Clock 1
Above is a timing diagram for some clock by name C1 or Clock 1.
 Clock is a periodic signal.
 Clock usually hasn’t beginning or end. It exists all the time while power is on and is
used for synchronization of circuits.
 For the period when the signal has high level sometime we say “The signal exists”
or “There is a signal”.
 For the period when the signal has low level we say “There is no signal” or “No
signal”.
 Usually the “Signal” and “No signal” times are equal and each takes the half of a
clock period.
Ideal Signal Properties:
Signal exists
Top of Signal
A
No Signal
Rising Edge
No Signal
Falling Edge
Ideal signals have rectangular form.
The edges are vertical so the signal doesn’t spend time for changes from 1 to 0 and
vice versa.
Real Signal Properties:
The real signals haven’t vertical edges because of parasitic capacitance and resistance.
They have edges changed by natural logarithm exponent laws and sometime are not
look like to signal forms we use in our timing diagrams.
In digital logic circuits we use another form of real signals which corresponds to
requirements of digital logic development and also is possible to implement on real
electronics.
Real Signal form and properties for using in digital design:
Falling Edge
Rising Edge
Top of Signal
A
No Signal
No Signal
Rising Time
Signal’s real
length
Falling Time
The points where the signal is really
changed from 1 to 0 and from 0 to 1
A real changing point of signal is the level of signal when the next
circuit feels the change of signal on its input.
Digital Signals on basic gates
Let’s see the behavior of signal passing the NOT gate.
A
Z
A
Z
T pd
T pd
The signal Propagation Delay caused by
electronics of real NOT gate.
This delay doesn’t cause any problems in this case when we discuss only one signal.
The rising and the falling times as well as the propagation delay time
we we’ll use upon necessity when they become important for the
circuit design process.
Usually this happens when we have a real gates on real chips and
there is initial design requirement to take in account the real chip
timing parameters.
Let’s see what we have on AND, OR gates when some two signals arrive to the gates’
input.
The propagation time doesn’t depend on edge rising and falling time. It depends on the
timing parameters of gate. So we can suppose that when the signal is really changed
somewhere between beginning or end of real rising edge then that point is the
vertical rising edge of virtual signal.
This assumption makes our signals rectangular however the propagation time we have to
take in account in the next several examples to see how the signals pass through other
gates.
A
&
B
Z
A
B
A
Z
A
0
0
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
A
1
B
Z
A
B
A
Z
A
0
In both above cases the propagation delay time is smaller than the
signal itself so we have delay however we have correct delayed
signals at the end of the circuit.
Signal Race
Signal racing is the condition when two or more signals change almost
simultaneously. The condition may cause glitches or spikes in the output signal
as shown below. The effects of these glitches can be eliminated by using
synchronous timing techniques. In synchronous timing the glitches are allowed to
come and go, and the logic state changes are initiated by a timing pulse (clock
pulse).
Signal racing is the condition when two or more signals change
almost simultaneously. They can cause glitches or spikes in
the output signal.
Let’s see the racing caused by edges’ rising and falling time difference of different gates.
The Glitch here is only the result of racing signals which are changed simultaneously
but not the result of delay of one of the input signals.
A
&
B
Strobe (timing, clock pulse)
to take the correct value of Z
Z
Already 1
A
B
A
Z
A
0
0
1
1
0
0
1 Yet 1
0
1
0
0
0
0
1
0
T pd
Glitch- we have false 1 when we
expect 0
To eliminate glitches we can use one of synchronization methods called Strobe (timing
or clock pulse) – taking the value of signal (variable) when it’s correct for sure.
The below circuit does a simple A AND B function however B is passed through the “n”
gates and the final delay of gates is bigger than the signal length.
Here we have another type of racing caused by additional circuits delay of one of
signals.
&
A
1
&
&
B1
B
Bn
Z
1
A is already removed but B
hasn’t been yet propagated
A
B
A
0
1
0
0
0
1
0
0
1
Bn
A
Z=A&Bn
0
0
0
0
0
0
0
Never changed
Delay caused by additional circuit