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Analysis and Design Considerations of
Integrated 3-Level Buck Converters
Abstract:
This paper presents a systematic analysis of integrated 3-level buck converters
under both ideal and real conditions as a guidance for designing robust and fast 3level buck converters. Under ideal conditions, the voltage conversion ratio, the
output voltage ripple and, in particular, the system’s loop-gain function are
derived. Design considerations for real circuitry implementations of an integrated
3-level converter, such as the implementation of the flying capacitor, the impacts
of the parasitic capacitors of the flying capacitor and the 4 power switches, and the
time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under
these conditions, the voltage conversion ratio, the voltage across the flying
capacitor and the power efficiency are analyzed and verified with Cadence
simulation results. The loop-gain function of an integrated 3-level buck converter
with parasitic capacitors and time mismatch is derived with the state-space
averaging method. The derived loop-gain functions are verified with time-domain
small signal injection simulation and measurement, with a good match between the
analytical and experimental results.
Existing system:
 Three level converters, since first proposed in, have become more and more
attractive recently in both the academia and the industry due to their many
advantages under high-voltage operations.
 Adopting high-voltage devices with a standard 2-level buck operation solves
the over-voltage problems, but degrades the efficiency due to large
switching loss. High-voltage devices bring a higher cost and may not be
available for some process options.
Proposed system:
 In this proposed system Dynamic performance is been elaborated, and the
loop-gain function under ideal conditions is derived using state-space
averaging (SSA) method with perturbation analysis.
 Design considerations and practical design issues of integrated 3-level buck
converters, such as the influences of parasitic capacitors and the time
mismatch.
 Simulation results in Cadence Virtuoso Analog Design Environment are
presented to verify all the analyses.
 A time-domain small signal injection simulation method with Bode plot
results to verify the derived loop-gain functions.
Block diagram:
Reference:
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choppers and voltage-source inverters,” in Proc. IEEE Power Electron.
Specialists Conf., Toledo, Spain, Jun. 1992, pp. 397–403.
[2] V. Yousefzadeh, E. Alarcon, and D. Maksimovic, “Three-level buck converter
for envelope tracking applications,” IEEE Trans. Power Electron.,
vol. 21, no. 2, pp. 549–552, Mar. 2006.
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and G.-H. Cho, “86.55% Peak efficiency envelope modulator for 1.5 W
10 MHz LTE PA without AC coupling capacitor,” in Proc. IEEE Symp.
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