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Hybrid CMOS-SET Devices
and Circuits: Modelling,
Simulation and Design
Santanu Mahapatra
Outline
 Introduction: CMOS scaling and emerging devices
 Single Electron Transistor (SET)
 Compact Modelling of SET
 CMOS - SET Hybrid Architectures
 CMOS - SET co-Simulation
 SETMOS – A Novel Hybrid CMOS-SET Device
 Implementation of MV logic and Memory by SETMOS
 SET Technology – CMOS-SET co-Fabrication
 Conclusion
Introduction
Pushing CMOS: the 10 nm wall
Key problems of for
sub-10nm MOSFET
(i) electrostatic limits
(ii) source-to-drain tunnelling
(iii) carrier mobility
(iv) process variations
(v) static leakage
(vi) Power density
After J.D Plummer , Proc IEEE 2001
Aggressive scaling has pushed
dimensions towards sub-10nm limits
CMOS
device
Life with and after CMOS
Single (Few) Electron Transistor
Gate
Island
Gate dielectric
Drain
Source
Ultra thin dielectric
Drain (D)
VDS
Gate (G)
CTD , RD
CTD: Drain tunnel junction capacitance
CTS: Source tunnel junction capacitance
RD : Drain tunnel junction resistance
RS : Source tunnel junction resistance
CG
VGS
CTS ,RS
Source (S)
CG : Gate capacitance
C = CG + CTD + CTS
SET vs. MOSFET: Device Perspective
source SET
sourceMOSFET
Gate
Source
Source
Drain
drain
tunneling conductive
junctions island
Gate
Source
n+
pn+
junctions
p
Drain
n+
drain
conductive
n-channel
• many electrons simultaneously
• electron conduction is one by one
participate to conduction
• island is conductor, VG only changes the
• gate potential invert the channel
potential and thus controls tunneling
• junctions highly transparent
• needs opaque junctions: RT > RQ~26kW
•mainly gate controls the threshold
• drain/gate controls Coulomb blockade
Engineers Like Numbers….
1. RT > RQ = h/e2 = 26kW
2. e2/C > kBT  C < e2/ kBT
where  = 10 (Memory Application), 40 (Logic Application)
C (aF)
T  = 10
T  = 40
 (nm)
10
5
1
0.5
18K
37K
195K
370K
4.6K
9K
46K
92K
46
23
4.6
2.3
0.1
1855K
463K
0.5
Present Tech.
RT = 0.5-1MW
C = 2-3 aF
Characteristics of SET (1)
IDS vs. VGS @ #VDS
20
e/C= 0.04V
10
101
0.04 V
5
0.06 V
-5
-10
-15
-20
-25
-0.08
14
e/C= 0.04V
e/CG
12
IDS vs. VGS @10#T
15
0
Drain to source current, I DS (nA)
25
Drain to source current, IDS (nA)
Drain to source current, I DS (nA)
IDS vs. VDS @ #VGS
-0.04
0.0 V
10-1
T = 1K 11.6K [40]
10-2
0.00
0.04
8
23.2K [20]
0.02 V
100
0.08
VDS (V)
Drain to source voltage,
10-3
VDS = 0.03V
0.05V
6
0.03V
0.04V
4
2
T = 1K
0
-0.10
-0.05
0.00
0.05
Gate to source voltage, VGS (V)
5.8K [80]
0.02 RTD
0.03
CTD=-0.01
CTS= 0.00
1aF, C0.01
= RTS0.04
= 1MW
G= 2aF,
Gate to source voltage, VGS (V)
0.10
Characteristics of SET (2)
Drain to source current, I DS (nA)
Background Charge (BC) effect
9
8
T =1K, VDS = 0.03 V
ne
n + 0.25e
When BC is integer (n)
there are no change in
SET characteristics,
however, it experienced a
shift of (BCeffe)/CG on VGS
axis when BC is fractional.
n - 0.25e
7
6
5
4
3
2
1
0
-0.06
For proper operation,
-0.04
-0.02
0.00
0.02
0.04
0.06
Gate to source voltage, VGS (V)
0.08
BC < n + 0.1e
A second gate with proper bias can compensate the B.C. Effect!
Carrier Transport in SET
Drain (D)
 = e/(2C); VD =  ; VS = 0
Gate (G)
VIS = (CG/C)VGS + (CTD/C)VDS
constant
CTD , RD
CG
Tunneling occurs only when lVISl or lVDIl > 
D
I
S
D
I
1
3
2
ON

D
I
S
3
2
4
Source (S)
S
3
CTS ,RS
3
2
2
1
2
0
-
-
OFF (C.B.)
1
6

0
2
5

3
4
0
-
ON
SET Simulation Techniques
Monte Carlo
(SIMON, MOSES)
Master Equation
(SETTRAN)
Macro Model
+ Accurate
+ Applicable for any SE device
- Time Consuming (specially for
current biased SET, resistance)
+ Faster than MC
- Time consuming for big circuits
+ Spice Compatible
- Non Physical
A successful implementation of SET as a
post-CMOS VLSI Candidate demands spicecompatible COMPACT analytical models
SET Compact Analytical Model- MIB*
• Based on the Orthodox theory, i.e., charge discrete,
energy continuous, etc.
D
I
S
IS
ID
VS

0
VD
-
IDS =
ID
I DI S
IS
ID + IS
IDS
ID = VD/RD
IS = VS/RS

2
At T <<e2/C , VD and VS
are either positive or zero
*S. Mahapatra et al. EDL 02, IEDM 02,TED 04
The Complete MIB Model
I DS
I S ( 0 )I D ( 1 )  I S ( 0 )I S ( 1 )  I D ( 1 )I D ( 0 )

I S ( 0 )I S ( 1 ) I D ( 1 )I D ( 0 )
IS (0 )  ID(1) 

ID( 2 )
I S ( 1 )
IS ( n ) 
Visland  ( 2n  1 )
 Visland  ( 2n  1 )  and
1  exp 

where
ID( n ) 


VT
VDS  Visland  ( 2n  1 )
 VDS  Visland  ( 2n  1 ) 
1  exp 

VT


VT is thermal voltage and  holds the sign of VDS
Model is valid for VDS 3e/C and T < e2/(10kBC)
Model Verification
IDS vs. VGS @ #VDS
10
10.00
T = 10K
e/C= 40mV
VDS (mV) = 55
12
Drain Current, IDS, (nA)
Drain to source current, IDS (nA)
15
IDS vs. VGS @ #T
50
9
30
6
45
20
3
40
10
-20
20K
15K
-1
0.10
10
10K
-2
0.01
10
-3
10
0.00
5K
VDS = 30 mV
0
-40
1.001
0
20
40
60
80
-4
0.00
10
-10
Gate to source voltage, VGS (mV)
Symbol: MC Solid Line: Analog MIB
0
10
20
30
40
Gate to source voltage, VGS, (mV)
Dotted Line: Digital MIB
CTD= CTS= 1aF, CG= 2aF, RTD = RTS = 1MW
SET INVERTER
VSS = e/2(CG + CT)
VSS = e/2(CG + CT)
CTS = CTD = CT
CG + CT = 4aF
T = 5K
12
8.0
8
RD = RS = 1MW
4.0 4
Vout (mV)
Input and Output voltage (mV)
Vin
Vout
12.016
0
CG:CT =
-4
1
3
-4.0-8
T = 5K1.6
-12
7
-8.0
CL = 1fF
0.0
-16
-12.0 -20
0
-10
10
0
20
Vin 30
(mV)
Time (ns)
CG : CT = 3:1
10
40
20
50
60
15
3.5
10
3.0
2.5
5
2.0
0
1.5
-5
1.0
-10
0.5
-15
0.0
-20
-10
0
10
20
VDD to VSS current, I static,(nA)
Output, Vout (mV)
Power Dissipation in SET Logic* (1)
There is a nonzero static current
from VDD to VSS
when the SET
inverter is in Logic
HIGH or LOW,
however this static
current is zero
during logic
transition, which is
just opposite to the
CMOS inverter.
Input,Vin, (mV)
*S. Mahapatra et al. IEDM 02, DAC 02
Power Dissipation in SET Logic (2)
10-7
15
VDD = 20 mV
RTS = RTD = 1MW
CG = 3aF
CTS = CTD = 1aF
T=0.1K
10K
20K
50K
5
10-8
50K
20K
10-9
10K
0
+Vdd
-5
0.1K
Vin
10-10
Vout
-10
Power @ 0.1K (W)
-Vdd
-15
-20
-10
0
Input voltage, Vin (mV)
10
10-11
20
Static Current, I (nA)
Output voltage, Vout (mV)
10
Power Dissipation in SET Logic (3)
1. Static Power Dissipation (Pstatic)
2. Dynamic Power Dissipation (Pdynamic)
3. Temperature Induced
Dissipation (Pleakage)
Leakage
Power
Ptotal = Pstatic + Pdynamic + Pleakage
In SET logic, power dissipation is essentially
static: (~ 10-8 W), which is almost 4-5
decades lower than CMOS!
SET Random Number Generator*
Conventional
SET Based
Random Bit Stream
Random Bit Stream
Schematic
VOUT
Noise
Source
AMP.
COMPARATOR
VIN =
Const.
Memory
Node
Noise
Source
Thermal, Shot Noise
Single Electron
Capture/Emition
Noise (Vrms)
~1V
~0.1V
Size
On Board (10-100 cm2)
On Chip (ultra small, ultra
low power dissipation)
• Room temp. operation (randomness increases with temp.)
• RTS ratio greater than one decade (highest)
*Toshiba, IEDM 02
CMOS & SET: Competitor/Collaborator?
SET
 Nanoscale device
 Ultra low power dissipation
 New functionalities
CMOS
 High Speed
 Very Stable Technology
– Lack of room temperature  SCE/DIBL
operable technology
 Power dissipation
– Reproducibility at nanoscale  Process variations at
Low Current drive (~nA)
nanoscale
Background charge effect
Concept of Hybrid CMOS-SET
Architecture
 Practical SET digital circuit applications are likely not
feasible with a pure Single Electronics approach,
mainly due to its low current drive
 Combining SET and CMOS, and exploiting the
Coulomb Blockade oscillation phenomenon of SET
and high current drive facility of CMOS, one can
bring out new analog functionalities, (neuron cell,
Multiple Valued Logic) which are very difficult to
implement by pure CMOS approach.
Challenges of Hybrid CMOS-SET
Architecture Design
 Enable
advanced
SET/CMOS
cosimulation and design
 Development of common technological
platform
 Innovation on new functionalities of
hybrid IC architectures, which are really
un-paralleled to the pure CMOS circuits.
CMOS-SET Co-simulation* (1)
 Proposed
model
MIB
is
implemented
in
SMARTSPICE** through its Verilog-A (AHDL) interface
 It is assumed that interconnect capacitances at gate,
source and drain terminals are much bigger than the
SET
device
capacitances.
Therefore
SET
characteristics depends only on the nodal voltages.
 Model parameters are device capacitances (CG,CG2,
CTD,CTS), device Resistances (RD,RS) and Background
Charge which could be defined through the SPICE
MODEL CARD.
* S. Mahapatra et al., ICCAD 03
**SILVACO International
CMOS-SET Co-simulation (2)
SMARTSPICE simulation flow
Verilog-A
SET module
module set(drain, gate1, gate2, source);
inout drain, gate1, gate2, source;
electrical drain,gate1,gate2,source;
SPICE
NETLIST
SOURCE
VerilogA
Compiler
C file
RUN
C-compiler
.so file
SMARTSPICE
// Default value of the model parameters
parameter real CTS = 1e-18, CTD = 1e-18
parameter real CG = 2e-18, CG2 = 0;
parameter real RD = 1e6, RS = 1e6;
parameter real BC = 0;
analog
begin
::::::::::::::::::::::::::::::MIB Subroutine
end
endmodule
Circuit Simulation: Neuron Cell
VSS
1.5
M2
M1
M3
VOUT
VIN
VDD
VOFFSET1
VOFFSET2
* M. Goossens,
Delft University Press
Output VOUT(V)
1.3
T = 300 K
1.1
0.9
0.7
0.5
VOFFSET1 = 1V
VOFFSET2 = 1V
VOFFSET1 = 0.5V
VOFFSET2 = 1V
0.3
0.1
0.0
0.5
1.0
1.5
Input VIN(V)
SET : CG = CG2 = 0.04aF, CTD = CTS = 0.02aF, RD = RS = 1MW
PMOS: L = 0.5m, W = 0.8m, TOX = 9.74nm, VTH = 0.55
2.0
Circuit Simulation: MVL Cell
Quantizer
Memory
6
Experimental
Simulation
Vout(V)
5
Vout
VGG
4
3
2
1
0
Vin
1
2
3
Vin(V)
SET: CG = 0.27aF, CTD = CTS = 2.7aF, RD = RS = 200kW
NMOS: W = 12m, L = 14m, Tox = 90nm, VTH = 0.64V
VGG is set to 1.08V and Vout is hard-limited at 5V
*H. Inokawa et al., TED ‘03
4
5
EPFL’S Variable Hysteresis Cell*
60
VIN
S1
IIN
S2
Input Current I IN (nA)
IBIAS
0
T = 150 C
50
CG = 0.2aF,
50 nA
40
40 nA
30
CTD = CTS = 0.15aF,
30 nA
20
RD = RS = 1MW
20 nA
10
IBIAS = 10 nA
0
0.00
0.40
0.10
0.20
0.30
40 nA
0.40
30 nA
Input Voltage VIN (V)
Input Voltage VIN (V) 0.35
0.30
50 nA
20 nA
IBIAS =
10 nA
0.25
0.20
0.15
S. Mahapatra and A.M.Ionescu et al. JJAP’04,
IEEE NANO ‘04
0
T = 150 C
0.10
0
10
20
30
40
Input Current IIN (nA)
50
60
SETMOS Device – C.B. at A Range!
Drain
Drain(D)
(D)
VDS1,MAX
e/CG
IDS2
Gate (G)
(G)
IDS1
VDS1
BIAS
IIBIAS
~e/C
VGS1
VGS1
VDS1
VGS2
If VDS1,MAX <= VTH, MOS is operating just
under VTH (subthreshold)
VDS2
IBIAS
D
Log10 IDS2
Source(S)
(S)
Source
Exponentially amplified
drain current
G
S
S. Mahapatra et al., IEDM 03, EDL 04
VGS2
SETMOS Device Characteristics (1)
CTD = 0.15aF
CTS = 0.15aF
RD = 1MW
RD = 1MW
C = 0.5aF
Ø ~ 2.5nm
1.20
0.5
1.00
0.4
0.80
0.3
0.2
0.1
VDS (V) =
CG = 0.2aF
Drain to Source Current, I DS (A)
IDS vs VGS @ #VDS
T = 1000C
IBIAS = 40nA
L = 65nm
W = 100nm
VTH = 0.32V
e/CG = 0.8V
0.60
TOX = 1.7nm
0.40
Calibrated
65nm BSIM4
model
0.20
0.00
-1.00
-0.50
0.00
0.50
Gate to Source Voltage, VGS (V)
1.00
[BSIM Web]
SETMOS Device Characteristics (2)
IDS vs. VGS @ #T
CTD = 0.15aF
CTS = 0.15aF
RD = 1MW
RD = 1MW
Drain to Source Current IDS (A)
CG = 0.2aF
VDS = 1V
10-6
L = 65nm
W = 100nm
0
T = 25 C
VTH = 0.32V
10-7
TOX = 1.7nm
10-8
0
10-9
-225 C
Sub Ambient (00C to –1500C) Operation:
1000C
1) Realistic SET (Ø ~ 2.5nm)
10-10
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2) Improved MOS
Characteristics
in terms
of
SS, PDP, leakage Gate
[I.Aller
et al., Voltage
ISSCCV‘00
]
to Source
GS (V)
2.0
Sub-ambient operation of CMOS
At sub-ambient temp.
1) Mobility increases
2) Static Power dissipation
decreases
3) Sub. Slope improves
4) Speed increases
BULK
New Architectures
Roadmap
Sub-ambient operation
Y. Taur and E.J. Nowak, IEDM 97
SETMOS NDR Device
Drain (D)
Slope:
CG/(CTS+CG)
IIN
Slope:
 CG/CTD
Gate (G)
VDS1
IBIAS
VIN
VGS1 = VIN
PDR
Log10 IDS2
Source (S)
VDS2 = VIN
NDR
IBIAS
VGS2 = VDS1
SETMOS NDR Device Characteristics
IIN vs. VIN @ #IBIAS
Gate
Leakage
Effect
6.0
5.0
4.0
VIN
VIN
IBIAS
I BIAS (nA)=
3.0
50nA
2.0
IG
40nA
0
1.0
IG (nA)
Input Current, IIN (A)
T = 1000C
0.0
0.00
-20
30nA
20nA
I
50nA
BIAS
-40
= 20nA
0.50
1.00
1.50
Input Voltage, VIN (V)
-60
0.0
0.5
1.0
VIN (V)
1.5
2.0
2.00
No impact of leakage
IG < IBIAS/10
Interconnect Issues in Nanoscale ICs
Not
only
the
fundamental
limitations of the nano-scaled
MOSFET,
but
also
the
interconnect limits have threaten
to decelerate or halt the historical
progression of the semiconductor
industry
because
the
miniaturization of interconnects,
unlike transistors, does not
enhance their performance
After K. Banerjee et al. Proc. IEEE 2001
As larger the chips become, the number of local modules grows
as l2 (where l is the chip edge length) and the number of
interconnects in a generally connected network grows as (l2!)
Multiple Valued (MV) Logic: Motivation
MV Logic is a logic system where the radix is more than 2.
radix (r) = 2 (binary), 3(ternary), 4 (quaternary)
Binary
MV
Analog
The information per line carried by binary system (either 0 or 1) is
much less than analog system (infinity). That’s why interconnect
complexities have always been a problem in Digital (Binary) ICs than
Analog one.
However, digital systems have other advantages compared to the
analog counterpart in terms of precision, stability, noise immunity etc.
BUT ARE THOSE ADVANTAGES SOUGHT TO BE
FOUND ONLY IN THE BINARY DOMAIN????
MV Logic Applications
(i) Complete replacement of Binary world by MV logic may
not be possible, however a hybrid binary-MV system
can be used to solve the interconnect complexities.
(ii) Large scale memories, Content Addressable Memories
(iii) Neural Network, Intelligent Systems
(iv) Advanced systems, e.g., molecular computing system
Pass Gate
s0, s1,……..sk
(substrates)
e0, e1,……..ek
(enzymes)
0 (if s=si and e = ei)
s (otherwise)
MV Logic Implementations
Concept of MV logic is NOT AT ALL very new, however its
CMOS implementation has always been strugling because:
1. MOSFET is a single threshold device
2. CMOS implementation of MV logic either demands
MOSFETs having different threshold voltage on the same
wafer or highly asymmetric (like 200:1) device aspect ratio.
However, the Coulomb blockade oscillations (multiple
threshold points) could be directly linked to MV operations.
SETMOS, which combines the features from both SET
and CMOS could be an attractive candidate for MV logic
and memory realization.
SETMOS Quaternary Literal Gate* (1)
Literal Gate (axb) : f(x) = r –1 when when a  x  b else 0
Universal Literal Gate (xs): f(x) = xs = r  1 when x = s  S else 0
Here, for quaternary logic system, r = 4, S = (0,1,2,3), and a, b, x, s  S.
Example: if x = (0,1,2,3) 2x3=(0,0,3,3) and x1,3 = (0,3,0,3)
Working Principle:
IC
I BIAS
VZ
IBIAS
IC
VOUT
VZ
VOUT
V IN
VGS2
VT
VOUT
VGS2
VZ
VZ
VIN
VIN
*S.Mahapatra and A.M.Ionescu, submitted to TNANO
SETMOS Quaternary Literal Gate (2)
04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V
1,3
1.20
x
Gate
IC = 0.4uA
IBIAS = 59nA
VGS2 = 0.35V
2 3
x Gate
1.2
0.90
-1000C
VOUT (V)
VOUT (V)
0.9
-500C
0.60
-1000C
-500C
0.6
0 0C
0 0C
0.30
0.00
0.00
0.3
IC = 0.4uA
IBIAS = 55nA
VGS2 = 0.123V
0.0
0.30
0.60
VIN (V)
0.90
0.0
0.3
0.6
0.9
VIN (V)
Using literal gates one can implement the Transmission Gate
(T-Gate) which is a building block of all MV logic functions.
Binary-to-Quaternary Converter
VDD
VB1
1.0
04
VB2
0.9
LSB
MSB
LSB
0.8
MSB
VB1
14
0.7
VB2
MSB
LSB
24
VDD
VB1
0.6
0.5
0.4
VOUT
VB2
0.3
MSB
LSB
0.2
34
VDD
VB1
VOUT
(MVL)
Voltage (V)
2-to-4 binary MOS-SET hybrid decoder
VDD
VB2
0.1
0.0
MSB
LSB
0
100
200
300
400
Time (ns)
04 = 0V, 14 = 0.3V, 24 = 0.6V, 34 = 0.9V
04 = 0V, 14 = 0.9V
500
Quaternary-to-Binary Converter
1.0
0.9
LSB
0.8
MSB
2 3
x
MSB
VIN
(MVL)
x1,3
LSB
Voltage (V)
0.7
VIN
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
100
200
300
Time (ns)
400
500
Interconnect Reduction Scheme
Traditional Binary System
I1
O1
O1
Module 2
Module 1
O2
I2
I1
O1
Module 1
I2
O2
Global Interconnects
B2Q
Q2B
Local Interconnects
O2
Q2B
I2
I1
O1
Module 2
I2
Hybrid Binary-MV System
O2
B2Q
I1
SETMOS MV SRAM (1)
IDS
VDS
IBIAS
I0 > I2
I2
NDR
I1
IDS
I0
IC
I2
I1
I0
V0  04
VDS
V1  14 V2  24
V3  34
IBIAS
VDS
Hysteresis
I2
IDS
VDS
V3
V2
I1
I2
V1
I1
I0
V0
IC = (I0 + I2)/2
I0
IK
IC
IK
IDS
SETMOS MV SRAM (2)
1.8
2.0
T = 500C
1.6
1.8
1.4
1.6
1.4
1.2
0
1.0
T= 0 C
@ 70nA
0.8
T= -1000C
@ 70nA
0.6
IBIAS =
80nA
0.4
70nA
VDS (V)
VDS (V)
T = 500C
IBIAS = 70nA
1.2
1.0
BC = 0
0.8
BC = 0.1
0.6
0.4
BC = -0.1
60nA
0.2
0.2
0.0
0.0
0
2
4
6
IDS (A)
8
10
12
0
2
4
6
IDS (A)
8
10
SETMOS MV SRAM (3)
WLW
MW
MW
BLR
BLW
IC
IR Buffer
IBIAS
WLR
• IR~1A (100 times larger than some other MOS-SET approaches)
• Writing is ideally instanteneous, Reading time is in the same order of
conventional CMOS SRAM
• Minimum Transistors needed to develop one SRAM cell by pure CMOS
approach is 12 [U. Cilingiroglu, IEEE CAS II, 2001]
SET Technology
 Unlike CMOS, there is no
technology for SET fabrication
fixed,
well
defined
 SET could be made by Si, Metal, III-V Material or even
by Carbon Nanotubes
Some of the possible Si-SET technologies are:
 PADOX – SD [NTT]
 Undulated Film – MD [Toshiba]
 Nano-grain PolySi – MD [Hitachi]
 Electronic SET – SD [Korea]
 MOS-SET – SD [LETI]
SD : Single Dot
MD: Multiple Dot
E
P
F
L
Single Dot SET Fabrication (1)
FEEL THE CHALANGE !!
8 inch
0.4mm
5nm
ISOLATE
SET island
Si/SOI wafer
LITHOGHRAPHY IN THREE DIMENTIONS ??
Single Dot SET Fabrication (2)
PAttern Dipendent OXidation (PADOX)*
Idea  stressed silicon has a lower oxidation rate
EPFL’s Approach : (i) no e-beam
(ii) smaller island size
*NTT Japan
Multi Dot SET Fabrication (1)
Multi Dot Device: Non-classical SET
7
5
Gate
4
3
Drain to source current, IDS (nA)
Drain to source current, IDS (nA)
Drain
Source
nanograin wire
VGS = 0V
2
1
0
-1
Coulomb Blockade
-2
-3
-4
-5
-0.1
0.0
0.0
0.0
0.0
5
4
3
2
1
0
-0.2
0.1
Drain to source voltage, V DS (V)
(a)
6
(b)
VDS = 0.045V
-0.1
Advantage: Easier to fabricate than single dot device
Difficulties: Modelling and Design
0.0
0.1
Gate to source voltage, V GS (V)
0.2
(c)
Multi Dot SET Fabrication (2)
EPFL’s nano-grain polysilicon wire technique
 = 10-20nm
CMOS-SET Co-Fabrication*
*S. Ecoffey et al. MNE 04
Summary
• Single Electron Transistor (SET) is an attractive candidate
for future ultra low power nano-electronics.
• Due to some of its intrinsic limitations (low current drive,
lack of room temperature operable technology) it is
unlikely that SET can replace the CMOS world.
• However, the unique properties (e.g., Coulomb blockade
oscillations) of SETs can be exploited to increase CMOS
functionalities by hybrid CMOS-SET approach.
• SETMOS is one such hybrid CMOS-SET architecture,
which combines the virtues of both devices and exhibits
many novel functionalities which are very difficult to
achieve by either of these technologies.