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Transcript
MARS EXPRESS
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MEX-MMT-SP-0007
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E_IDS-i
ANNEX A (E-IDS)
ELECTRICAL INTERFACE REQUIREMENT
SPECIFICATION
MARS EXPRESS
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E_IDS-ii
FOREWORD
This annex specifies the electrical interfaces and the data exchange protocols for the for the
spacecraft units and for the payload instruments. It is annexed to the Unit Requirement
Document (URD) and to the Payload Interface Document (PID_A).
MARS EXPRESS
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I
CONTENTS
FOREWORD ............................................................................................................................................ ii
1
1.1
1.2
1.3
Power Supply .......................................................................................................................................... 1
General Requirements .......................................................................................................................... 1
Latch Current Limiter interface ........................................................................................................... 4
Foldback Current Limiter interface ...................................................................................................... 6
2.1
2.2
Pyrotechnic .............................................................................................................................................. 7
General Requirements .......................................................................................................................... 7
EED Interface Characteristics .............................................................................................................. 8
2
3
Data Management ................................................................................................................................... 9
3.1
General Data Management Requirements ............................................................................................ 9
3.1.1
General requirements and standards ........................................................................................... 9
3.1.2
Redundancy .............................................................................................................................. 11
3.1.3
Standard Balanced Digital Link (SBDL) .................................................................................. 16
3.2
Telecommand Channels ..................................................................................................................... 18
3.2.1
Emergency Off Signal .............................................................................................................. 18
3.2.2
High Power Commands (HPC) ................................................................................................ 19
3.2.3
Extended High Power Commands (EHP; not available to payload) ........................................ 21
3.2.4
Memory Load Commands (MLC) ............................................................................................ 23
3.2.5
Delayed Memory Load Commands (DML) ............................................................................. 28
3.3
Timing and Synchronisation Signals.................................................................................................. 29
3.4
Telemetry Channels ........................................................................................................................... 33
3.4.1
Serial Digital Telemetry (SDT) ................................................................................................ 33
3.4.2
Analogue Channels (ANS) ....................................................................................................... 40
3.4.3
Bi-Level Digital Channels (BLD) ............................................................................................ 43
3.4.4
Relay/Switch Status Channels (RSS) ....................................................................................... 46
3.5
Temperature Housekeeping Channels ................................................................................................ 49
3.5.1
Standard Temperature HK Channels (ANC) ............................................................................ 49
3.5.2
Platinum Thermistor HK Channels (ANP) ............................................................................... 53
3.6
Converter Synchronisation ................................................................................................................. 57
3.7
High Rate Data Interface IEEE 1355 (HRD) ..................................................................................... 58
4
Command Distribution and Data Acquisition Protocols ................................................................... 65
4.1
Packet Structure ................................................................................................................................. 66
4.1.1
Telemetry Source Packet Structure .......................................................................................... 66
4.1.2
Telecommand Packet Structure ................................................................................................ 66
4.2
Command Distribution ....................................................................................................................... 67
4.3
Discrete and SDT Telemetry Acquisition .......................................................................................... 70
4.3.1
Serial Digital Telemetry ........................................................................................................... 70
4.3.2
Discrete TM user (BLD, RSS, ANS, ANC, ANP) ................................................................... 74
4.4
Timer Synchronisation ....................................................................................................................... 75
4.5
High Rate Data Transmission ............................................................................................................ 77
4.5.1
High Rate Link Protocol ........................................................................................................... 77
4.5.2
High Rate Science Data Acquisition ........................................................................................ 88
4.5.3
High Rate Plain File Transfer ................................................................................................... 92
MARS EXPRESS
1
Power Supply
1.1
General Requirements
IFOD-001:
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E-IDS -1
The power bus with 28 V DC regulated by the PCU will be distributed by the PDU
via
1) Latching Current Limiters (LCL) for the ‘non-essential’ loads (e.g. users which
do not need to be permanently powered such as the payload instruments).
The LCLs will be switched ON – respectively OFF - by TCs to perform the
connection – respectively the disconnection - of the power lines to the users.
The LCLs will provide the following protections:
- limitation of the maximum current to the user
- automatic disconnection (LCL trip-off) of a user in case of overload.
2) Foldback Current Limiter (FCL) which are permanently ON for essential loads
(e.g. receivers, decoders)
Foldback Current Limiters (FCL) are not available to payload.
The FCLs will provide a protection by limiting the maximum current of a user in
case of overload.
The power distribution concept is shown on fig 1.1-1.
IFOD-005
A nominal and a redundant LCL – operated in cold redundancy – will be provided to
each user. This applies for users with a redundant power supply and for users with a
non-redundant power supply.
Exceptions are the spacecraft heaters that will receive only one LCL (no
redundancy).
Redundant power lines shall be diode-isolated if joined to a common power bus in
the user.
Power lines shall be routed through dedicated connectors
MARS EXPRESS
LCL
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E-IDS -2
HEATER
‘Essential’ Load
FCL
NOM
FCL
RED
REGULATOR
‘Non-Essential’ Load
28V ± 1%
LCL
NOM
LCL
RED
LCL
EXP1)
PS/S
LCL
1)
when required and agreed for thermal control, an additional, non-redundant heater will be
provided
Figure 1.1-1: MARS EXPRESS Power Distribution Block Diagram
MARS EXPRESS
IFOD-010
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Users are requested to implement an additional ON/OFF switching capability. This
shall be done by mean of latching relays for each primary supply and for each heater
supply .
The user shall accept a nominal and a redundant TC for power ON switching.
The user shall accept a nominal and a redundant TC for power OFF switching.
The status of a power ON/OFF relay shall be made available on redundant pins for
redundant acquisition by the telemetry.
IFOD-015:
All power converters and switching regulators shall be free running at a fixed
frequency of 131 kHz ± 5 % corresponding to the Data Management High Frequency
Clock (HFC)
Other converter frequencies
- at the harmonics (262 kHz, 393 kHz, 524 kHz) or
- at half the frequency (65.5 kHz)
may be granted on request.
For DC/DC converters a minimum set of basic requirements as defined in ESA-PSS02-10 shall be applied wrt stability and electrical design.
IFOD-020:
On user side overvoltage protection has to be performed.
IFOD-025:
Each user shall define its average, long peak and short peak power demand per power
line in accordance with the definitions below:
Average Power
The average power demand is the maximum average power drawn from a power
line in the worst case voltage conditions. The maximum average shall be defined as
the mean value (without long peaks) over a period of 5 minutes shifted to any point
in time where this value yields a maximum.
Long Peak
The long peak is defined as the mean value during a period of 100 msec shifted to
any point in time where this value will yield a maximum. A long peak is defined as a
power demand lasting less than 5 minutes and more than 100 msec.
Short Peak
The short peak is defined as the mean value during a period of 1 msec shifted to any
point in time where this value will yield the maximum. A short peak is defined as a
power demand lasting less than 100 msec.
MARS EXPRESS
1.2
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Latch Current Limiter interface
IFOD-030:
The Latch Current Limiter interface characteristics shall be as specified in the
following data sheet:
INTERFACE DATA SHEET
page 1 of 2
I/F Designation:
Latch Current Limiter
Code: LCL
POWER S/S SPECIFICATION
LCL class
Each user shall define the LCL class needed for its supply
lines. This shall be done in accordance with the LCL class
definition presented in the table below depending on the
maximum nominal current drawn on the considered line.
Classes F and G are not available to the payload.
ON/OFF switching
LCLs can be commanded ON and OFF by TCs
Trip-off point /
Limiting point
The trip-off point and the limiting point shall be identical.
The limiting point shall be set to maximum nominal current
of the LCL class plus 30%.
The accuracy of the setting shall be –0%/+15% for all
classes.
Overcurrent limitation delay
An overcurrent to the load shall be limited by the LCL
within 5 µs after trespassing of the limiting point.
Trip-off delay
The LCL shall disconnect the corresponding line (LCL tripoff) when it has been in continuous limiting condition for
16 ms 5ms.
Undervoltage protection
LCLs will automatically switch off in case the input voltage
drops below 25.5 V 0.4 V
Monitoring provisions
-
Ripple & Transient
As defined in PID-A annex E-EMC §5.1.
Switch over
no automatic switch over from one current limiter to the
other (i.e. nominal to redundant)
LCL Class Definition
LCL Class
class A
class B
class C
class D
class E
class F (*)
class G (*)
(*) not available to payload
LCL current with a resolution of ±3%
current limiter ON/OFF status
Trip-off / limiting point
11 W/0.4 A
22 W/0.8 A
44 W/1.6 A
82 W/3.0 A
109 W/4.0 A
136 W/5.0 A
163 W/6.0 A
Max. nominal current
0.3 A
0.6 A
1.2 A
2.3 A
3.1 A
3.8 A
5.0 A
MARS EXPRESS
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INTERFACE DATA SHEET
I/F Designation:
Latch Current Limiter
LOAD SPECIFICATION
Input Voltage
+28 V +1%/-2% - R_out*I_load
(at nominal load)
Inrush Current
MEX-MMT-SP-0007
Page 2 of 2
Code: LCL
(1)
To be limited by the load to < 1 A/µs
At load switch on the LCL will limit the inrush current if
necessary at the limiting point of the LCL class.
Within 8 ms after switch on the load input voltage shall
have reached its nominal value and the current shall be
lower than 80 % of the trip-off current of the LCL class.
The load shall then reduce the current to or below its
maximum nominal value within one second after switch
on.
Overvoltage Generation
For inductive load, the user shall limit the overvoltage
generation to 35 V (provision of freewheeling diodes).
HARNESS SPECIFICATION
Wiring Type
Twisted Pair (TP)
NOTES:
(general reqts. in PID-A § 6.7)
1- each resistance including an assumed interconnecting harness between PDU and
load of 4m:
R_out = 775 mOhm for class A
R_out = 740 mOhm for class B
R_out = 300 mOhm for class C
R_out = 300 mOhm for class D
R_out = 150 mOhm for class E
R_out = 150 mOhm for class F, G
MARS EXPRESS
1.3
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Foldback Current Limiter interface
IFOD-035:
The Foldback Current Limiter interface characteristics shall be as specified in the
following data sheet:
INTERFACE DATA SHEET
I/F Designation:
Foldback Current Limiter
POWER S/S SPECIFICATION
PCU Voltage
+28 V ±1%
Page 1 of 1
Code: FCL
Overcurrent
The current limiter shall be sized to deliver the maximum
power current levels compatible with the load plus a 30%
margin. The limiting point shall have a tolerance not
greater than -0/+15%.
Monitoring
the current (1) with a resolution of ±3% shall be included
in the unit housekeeping data
Max. Nominal Current
1.1 A
Limiting Current
1.4 A
Switch off Delay Time
not applicable
Ripple & Transient
As defined in PID-A annex E-EMC §5.1.1
Switch over
not applicable
LOAD SPECIFICATION
Input Voltage
(at nominal load)
Overvoltage Generation
+28 V ± 0.3 V including load variation and component
drift during the mission lifetime
For inductive load, the user shall limit the overvoltage
generation to 35 V (provision of freewheeling diodes).
HARNESS SPECIFICATION
Wiring Type
Twisted Pair (TP)
Note: this interface is not available to payload
(general reqts. in PID-A § 6.7)
MARS EXPRESS
2
2.1
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Pyrotechnic
General Requirements
a)
Items, which require pyrotechnic release, shall incorporate Electro-Explosive Devices
(EED's) as integral part of the item.
b)
All EED's shall be initiated via the spacecraft dedicated pyrotechnic circuitry.
c)
Only qualified initiators will be accepted for use, subject to Prime/ESA approval.
d)
Only one firing command to a single filament will be provided at a time.
IFOD-045:
Redundancy shall be provided for each function by duplication up to at least the
initiators.
The Pyro electronic interface, as well as the interconnecting harness including Antistatic
Resistor, shall be as shown in figure 2.1-1. (The safe plug configuration is indicated by
dashed lines.)
Pyro Electronic Circuit
Pyro (User)
Arm Plug
Save Plug
Test
Load
1.3
current
limiter
+
f iring
sw itch
Nom.
current
limiter
+
f iring
sw itch
Red.
arm
sw itch
selection
sw itch
Firing Line
TSP
TSP
Antistatic
Resistor
360
Return Line
Mainbus-/BatteryReturn
Structure
Ground
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 2.1-1: Pyro Electronic Interface and Schematic Circuitry
Bridgew ire
MARS EXPRESS
2.2
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E-IDS -8
EED Interface Characteristics
IFOD-050:
The Pyro Firing Line interface characteristics shall be as specified in the following
data sheet:
INTERFACE DATA SHEET
I/F Designation:
PYRO firing
SOURCE CIRCUIT SPECIFICATION
Firing Pulse Duration
(24 ± 2) ms
Repetition Rate
> 100 ms
Firing Current
4.5 A < Ifire < 6.0 A
Grounding Resistor
1 MOhm to structure ground
page 1 of 1
Code: PYR
RECEIVER CIRCUIT SPECIFICATION
Max No-Fire Current
1 A for 5 min
All Fire Current
4.0 A within 20 msec
Input Resistance
Ri < 1.3 Ohm
(1)
Isolation Resistance
> 2 MOhm at 250±5% VDC for >15 s
(2)
HARNESS SPECIFICATION
Wiring Type
Twisted Shielded Pair (TSP)
Antistatic Resistor
300 Ohm < RAS < 390 Ohm
(general reqts. in PID-A §3.7)
NOTES: 1. Applicable for maximum drive/sink current of 200 µA
2. between filaments and EED-case before firing
3. implemented in the Pyro harness (between Squib and Safe/Arm plug)
(3)
MARS EXPRESS
3
3.1
3.1.1
IFDG-001:
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Data Management
General Data Management Requirements
General requirements and standards
The DMS user interfaces shall be compatible with the following ESA standards:
- Packet Telemetry Standard (ESA PSS-04-106)
- Packet Telecommand Standard (ESA PSS-04-107)
- Telecommand Decoder Specification (ESA PSS-04-151)
IFDG-005:
The commanding of DMS users shall be performed by telecommand packets as
defined in the ESA Packet Telecommand Standard, transferred at the physical level
as 16 bit memory load commands as per ESA Data Handling Interface Standard
(ESA PSS-47/TTC-B-01).
The telecommand packet structure is shown and described in the MARS EXPRESS
Space/Ground ICD (SGICD MEX-ESC-IF-5001 §6.1).
IFDG-010:
In addition, a limited number of discrete commands (e.g. ON/OFF commands) shall
be distributed by the DMS.
The distribution of single/unpacketized Memory Load Commands shall be possible.
This capability is not available to the payload (see §3.2.5).
IFDG-015:
The telemetry acquisition rate via the overall OBDH bus (i.e. the transfer rate) will
be 131 kbps. It will be distributed between the users according to a programmable
polling scheme.
IFDG-020:
All data transfer will be controlled by the DMS not interrupt driven.
IFDG-025:
The telemetry from DMS users shall be acquired as telemetry packets formatted as
defined in the ESA Packet Telemetry Standard. They shall be transferred at the
physical level:
- as 16 bit serial digital telemetry as per ESA Data Handling Interface Standard (ESA
PSS-47/TTC-B-01)
- as High Rate Data per IEEE 1355 link where applicable for high rate data
instruments (e.g. HRSC, OMEGA).
Each DMS user shall format its housekeeping (and science, if applicable) serial data
into telemetry source packets.
The telemetry source packet structure is described in the MARS EXPRESS
Space/Ground ICD (SGICD MEX-ESC-IF-5001 §5:1).
IFDG-030:
In addition, a limited number of discrete telemetry inputs (i.e. analogue and bi-level
status housekeeping) shall be acquired from the users and then packetized by the
DMS.
MARS EXPRESS
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IFDG-035:
DMS users, which do not support the packet telemetry/telecommand standards, shall
be supplied with standard unpacketized telemetry/telecommand channels. This
capability is not available to the payload.
IFDG-040:
The on-board solid state mass memory (SSMM) shall support an input data rate of up
to 25 Mbps over the direct High Rate Data (HRD) links from the high rate
instruments via the IEEE 1355 interfaces.
IFDG-045:
The DMS shall maintain the spacecraft Elapsed Time (SCET) and shall distribute it
on the OBDH bus to all on-board users.
IFDG-050:
All time reference in telemetry, telecommand and on-board the spacecraft shall be in
SCET.
MARS EXPRESS
3.1.2
IFDD-001:
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Redundancy
The Data Management shall deliver main and redundant lines to the users for each
required function (except for platinum thermistors if they are not redundant- see B
below).
The redundant interface shall be used only in case of failure of the spacecraft main
Data Management section or other major spacecraft or payload malfunctions.
NOTE:
The nominal and the redundant core of the RTU are powered alternatively whilst the
interface bank is powered permanently.
Each driver/receiver of the interface bank can be accessed by the active core.
Therefore, it is the responsibility of the user to interconnect these lines according to
the reliability scheme adopted to avoid failure propagation.
Optionally, the user may provide an additional second cross strapping as indicated
in the redundancy figures by dashed lines.
In the following figures (Figure 3.1-2 to 3.1-5) the redundancy schematic is outlined for both,
non-redundant and redundant users.
A) Output Signals from DMS to users
IFDD-005:
Signals coming from the DMS subsystem shall be available on two functional lines
(one main and one redundant).
A non-redundant user shall accept the main and redundant lines (refer to figure 3.12). The ‘Oring’ of the main and redundant signal shall be done in such a way that a
permanent high or a permanent low level of one signal does not invalidate the other
signal.
For a redundant user, the nominal line shall be connected to the nominal branch and
the redundant line to the redundant branch, refer to figure 3.1-3.
This shall be done in such a way that a single component failure on one side has no
impact on the performance of the other side.
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Non-redundant USER
RTU
nom.
core
Ref
nom.
nominal line
driver
nom.
receiver
nonred.
branch
red.
core
red.
redundant line
driver
red.
receiver
Figure 3.1-2: Commanding Schematic of Non-redundant user
Redundant USER
RTU
nom.
core
nom.
red.
core
red.
nominal line
driver
driver
nom.
receiver
redundant line
red.
receiver
Figure 3.1-3: Commanding Schematic of Redundant user
nom.
branch
red.
branch
MARS EXPRESS
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Implementation of Redundancy
IFDD-010:
The following signals provided by the DMS shall be active only on one side at a
time(i.e. the redundant channel is in quiescent state):
- High Power Commands (HPC) lines
- Memory Load Command Sampling (MLS) lines- Serial Digital Telemetry
Sampling (SDS) lines
IFDD-015:
The following signals provided by the DMS shall be active on both sides in parallel
(i.e. nominal and redundant channel are operating):
- Serial Data Clock (SDC) (MLC/SDT clock)
- Memory Load Data lines (MLD)
- High Frequency Clock (HFC)
- Timer Synchronisation Pulse (TSY)
B) Input Signals from users to DMS
IFDD-020:
Signal coming from the user (telemetry data) shall be acquired by the DMS through
two functional lines (one main and one redundant).
In case of a non-redundant user, the user shall support not only the nominal input of
the RTU, but also the redundant one, each on dedicated lines as shown in figure 3.14a
For a redundant user, the nominal line of the user shall be connected to the nominal
RTU input and the redundant line to the redundant RTU input, refer figure 3.1-4b.
This shall be done in such a way that a single component failure on one side has no
impact on the performance of the other side.
IFDD-025:
High Rate Data from/to users
High Rate Data Link interface with the user shall be served by the DMS through
two functional lines (one main and one redundant).
In case of a non-redundant user, the user shall support not only the nominal input of
the SSMM, but also the redundant one, refer figure 3.1-5a
For a redundant user, the nominal input shall be connected to the nominal branch
and the redundant input to the redundant branch of the user, refer figure 3.1-5b
This shall be done in such a way that a single component failure on one side has no
impact on the performance of the other side.
IFDD-030:
Platinum Thermistor Conditioning
The platinum thermistor conditioning shall only be redundant when the thermistor is
redundant.
MARS EXPRESS
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RTU
Non-redundant USER
nom.
Ref
nominal
line
nom.
receiver
nom.
core
nonred.
branch
red.
driver
redundant
line
red.
receiver
red.
core
Figure 3.1-4a: Telemetry Acquisition Schematic from Non-redundant user
Redundant USER
RTU
nom.
branch
nom.
driver
nominal
line
nom.
receiver
nom.
core
red.
branch
red.
driver
redundant
line
red.
receiver
red.
core
Figure 3.1-4b: Telemetry Acquisition Schematic from Redundant user
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SSMM
Non-redundant User
C Nom.
Memory Modules
IEEE-1355 Nom.
Non-red.
branch
IEEE-1355 Red.
C Red.
Figure 3.1-5a: SSMM Telemetry Acquisition Schematic from Redundant user
SSMM
Redundant User
Nom.
branch
MUX
N
IEEE-1355 Nom.
C Nom
M
od
M
ule
e
s
m
Red.
branch
MUX
R
IEEE-1355 Red.
C Red
or
y
Figure 3.1-5b: SSMM Telemetry Acquisition from Redundant user
MARS EXPRESS
3.1.3
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Standard Balanced Digital Link (SBDL)
IFDD-035:
For all serial digital interfaces, the signals shall be sent on balanced lines. The
principle scheme is given by figure 3.1-6. The link is symmetrical; the two lines
shall be identified as 'true' and 'complementary' lines.
differential driver
differential receiver
V+
V+
twisted shielded pair
TRUE
COMP
Signal GND
Signal GND
Structure GND
Structure GND
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.1-6: SBDL Interface Circuits (principle drawing)
NOTES
1.
2.
The 'true' line is the non-inverting output of the driver ('TRUE')
The 'complementary' line is the inverting output of the driver ('COMP')
For the SBDL I/F, the circuit as shown in figure 3.1-6a is proposed as preferred solution,
whilst the proposed alternative solution is given in figure 3.1-6b.
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DRIVER
MEX-MMT-SP-0007
RECEIVER
5V
5V
56
3k
SIGNAL TRUE
TSP
TSP
22pF
56
1/4
HS-26C31RH
or equivalent
3k
SIGNAL COMP
1/4
HS-26C32RH
or equivalent
Signal GND
Signal GND
Chassis GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.1-6a: SBDL Interface Circuits (proposed preferred solution)
SOURCE
RECEIVER
5V
110
110
169k
SIGNAL TRUE
TSP
681k
TSP
12k
2/8
54HC244
or equivalent
5V
110
12k
SIGNAL COMP
5.1k
169k
110
LM119
or equivalent
2/8
54HC240
or equivalent
5V
Signal GND
Signal GND
Chassis GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units.
Figure 3.1-6b: SBDL Interface Circuits (proposed alternative solution)
MARS EXPRESS
3.2
3.2.1
Telecommand Channels
Emergency Off Signal
Not available.
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -18
MARS EXPRESS
3.2.2
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -19
High Power Commands (HPC)
General Concept
a) The purpose of the HPC is to present to the user a pulse of fixed duration on a dedicated
line
b) The HPC must perform a unique action such as switch ON or switch OFF of a user.
IFDP-011:
The signal shall be transmitted via twisted shielded pairs with the cable shield
connected at both sides of the interface to chassis ground.
For units receiving more than one High Power Command channel from the same
output module, one redundant ´common return´ line (TBC) may be used for up to 5
channels. The link shall then use a twisted-shielded n-tuple cable including the
signal lines (max. 5) and one ´common return´.
Nominal and redundant branches shall use separate ´common return´ lines.
IFDP-013:
The active state voltage of the HPC is the high level (VOH).
The quiescent state voltage of the HPC is the low level (VOL).
IFDP-014:
High Power Command receivers of relay-type shall have redundant (in parallel) free
wheeling diodes.
The High Power ON/OFF Command interface including driver, receiver and interconnecting
harness shall be as shown in figure 3.2-2.
OBDH
USER
V+
1
n
enable
HIGH POWER ON/OFF.SIG
TSP
relay,
TSP
optocoupler or
LOGIC
HIGH POWER ON/OFF.RTN
Signal GND
differential receiver
Signal GND
Chassis GND
Chassis GND
The cable
shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.2-2: High Power ON/OFF Command Interface and Schematic Circuitry
MARS EXPRESS
IFDP-012:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -20
High Power Command Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
High Power Command
SOURCE CIRCUIT SPECIFICATION
Circuit Type
single ended driver
Transfer
DC coupled
Zero Reference
signal ground
page 1 of 1
Code: HPC
High Level Output Voltage
Low Level Output Voltage
12 V < VOH < 16 V (active state)
0 V < VOL < 0.5 V (quiescent state)
Pulse Width
Rise and Fall Times
tw = 11 to 30 ms
50 µs < (tr, tf) < 500 µs
(1)
Current Drive and Sink
Capability
|IOH, IOL| > 180 mA, sufficient to comply with specified
rise and fall times (tr, tf)
(1)
Short Circuit
< 300 mA during and < 100 µA after pulse
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +28 V
-0 V to +17 V
(2)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
relay, optocoupler, or differential receiver
Transfer
DC coupled
High Level Input Voltage
Low Level Input Voltage
VIH > 6.0 V
VIL < 2.5 V
Input Current
the load shall be able to work with current and pulse
width of the signal source
Input Capacitance
< 300 pF
Noise Rejection
as specified in the PID-A annex E-EMC §5.1
Max. Fault Voltage
Tolerance:
Emission:
(3)
-2 V to +18 V
-2 V to +25 V
HARNESS SPECIFICATION
(general reqts. in PID-A §6.7
Wiring Type
Twisted Shielded Pair (TSP)
NOTES:
1. when loaded with 2 nF (harness plus user input cap.)
2. with an overvoltage source impedance of 1.5 kOhm
3. at the user I/F connector
(2)
MARS EXPRESS
3.2.3
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -21
Extended High Power Commands (EHP; not available to payload)
General Concept
a)
Extended High Power commands are pulse commands, which drive high power loads
such as relays.
b)
The EHP must perform a unique action within the user.
IFDP-015:
The extended high power pulse command source shall be referenced to RTU
primary power ground; the load shall be isolated from electrical references of the
users.
IFDP-020:
The signal shall be transmitted via twisted shielded pairs with the cable shield
connected at both sides of the interface to chassis ground.
IFDP-025:
The active state of the EHP is the high level voltage VOH (Power switch closed).
The quiescent state voltage of the EHP is the low level voltage (power switch open).
IFDP-027:
Extended High Power Command receivers of relay type shall have redundant (in
parallel) free wheeling diodes.
The command interface circuitry including driver, receiver and inter-connecting harness shall
be as shown in figure 3.2-3.
OBDH
USER
Primary Power
+28V
Isolate
d
Powe
r
Switch
Driver
Power
Switch
RECEIVER
EXT. HIGH POWER
TSP
TSP
ISOLATED
INTERFACE
EXT. HIGH POWER RTN
Primary Power
Return
Signal GND
Signal GND
Structure GND
Structure GND
The cable shield may be connected directly to the connector housings or grounded inside the units.
Figure 3.2-3: Extended High Power Command Interface and Schematic Circuitry
MARS EXPRESS
IFDP-030:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -22
Extended High Power Command Interface Characteristics
INTERFACE DATA SHEET
I/F Designation:
Extended High Power Command
SOURCE CIRCUIT SPECIFICATION
Circuit Type
single ended driver
Transfer
DC coupled
Zero Reference
RTU primary power ground
page 1 of 1
Code: EHP
High Level Output Voltage
Low Level Output Voltage
25 V < VOH < 28 V (active state)
0 V < VOL < 0.5 V (quiescent state)
Pulse Width
Rise and Fall Times
tw = 600 to 1000 ms
(tr, tf) < 500 µs
Leakage Current
IL < 2.5 µA
Current Drive Capability
IOH : up to 500 mA, sufficient to comply with specified
rise and fall times (tr, tf)
Short Circuit
< 600 mA during pulse; after that < 100 µA
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +31 V
0 V to +31 V
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Relay coil or Optocoupler
Input Threshold Voltage and
Input Current
the load shall work with voltage, current and pulse width
defined by the signal source
Input Capacitance
< 300 pF
Noise Rejection
as specified in the PID-A annex E-EMC §5.1
Max. Fault Voltage
Tolerance:
Emission:
(1)
-2 V to +32 V
-2 V to +28 V
HARNESS SPECIFICATION
Wiring Type
Twisted Shielded Pair (TSP)
NOTES: 1. at the user I/F connector
(general reqts. in PID-A §6.7
MARS EXPRESS
3.2.4
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -23
Memory Load Commands (MLC)
General Concept
a)
The purpose of the memory load command (or 16 Bit serial load command) interface
is to transfer a 16 bit word, in serial form, from the DMS subsystem via the RTU to
the users.
b)
The MLC interface consists of three signal lines issued from the RTU:
one data line (MLD)
one clock line (SDC)
one sampling address line (MLS)
IFDM-001:
Each user shall be provided with only one redundant Serial Data Transfer Clock
(SDC) which shall be shared between Memory Load Command and Serial Digital
Telemetry.
IFDM-005:
One redundant line for memory load data (MLD) shall be provided by the DMS to
each MLC user.
One redundant sampling address line (MLS) shall be provided by the DMS to each
MLC user.
IFDM-007:
The transfer of the MLC data shall take place during the sampling pulse at a rate
defined by the clock for serial data transfer.
The Most Significant Bit (MSB) of the command data shall be transmitted first from
the RTU to the user.
The transmission of the following bits shall then be controlled by the trailing edge of
the transfer clock.
IFDM-010:
The three MLC signals shall be transmitted via a Standard Balanced Digital Link,
with the cable shield connected at both sides of the interface to chassis ground.
IFDM-015:
The memory load data provided to the user shall be a serial NRZ-L PCM signal.
IFDM-020:
Outside of the memory load transfer period, the quiescent state of the 'true' lines
shall be:
- the high level for the clock and the sample lines,
- the low level for the data lines.
Clock and data lines may be active outside the memory load transfer period.
The memory load command channel interface circuitry including driver, receiver and the
interconnecting harness shall be as shown in figures 3.2-4 and 3.2-5.
MARS EXPRESS
RTU
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -24
USER
Memory Load Sampling
(address n)
MLC to User at
address n
Memory Load Sampling
(address 1)
MLC to
User at
address 1
Memory Load Data
Serial Data Transfer Clock
Serial Telemetry Data
Data from
User at
address 1
Serial Telemetry Sampling
(address 1)
Serial Telemetry Sampling
(address n)
Data from
User at
address n
Figure 3.2-4: Memory Load Command Interface
(See also 3.6.1.3 for proposed interface circuits)
MARS EXPRESS
IFDM-025:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -25
Memory Load Command Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Memory Load Command
The interface comprises the following three lines:
- Memory Load Command Data (MLD)
- Serial Data Transfer Clock (STC)
- Memory Load Command Sampling (MLS)
Time relation defined in figure 3.2-6
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Balanced CMOS driver
Transfer
DC coupled
Zero Reference
Signal ground
page 1 of 1
Code: MLC
Coding
Bit Rate
NRZ-L
262 kbps (for an 8 bit Burst)
Low Level Output Voltage
High Level Output Voltage
Differential Output Voltage
0 V < VOL < 0.5 V
2.5 V < VOH < 5.5 V
Logic ‘1’:
2.0 V < VOD < 5.5 V
Logic ‘0’: -5.5 V < VOD < -2.0 V
|VLogic 1| - |VLogic 0| < 1.0 V
(1)
(1)
Rise and Fall Times
Spurious Noise
Current Drive and
Sink Capability
(tr, tf) < 700 ns
As specified in PID-A annex E-EMC §5.1
Sufficient to comply with specified tr & tf
(2)
Short Circuit
Maximum Fault Voltage
Short circuit proof; current limited to <100 mA
Tolerance: -0.5V to +7.5V
Emission: -0.0V to +7.0V
Unbalance of Diff. Output
(2)
(3)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver, CMOS compatible
Transfer
DC coupled
Differential Input Voltage
(-1.0 V < VCM < 1.0 V)
Hysteresis
Low: < - 1 V
High: > + 1 V
Switching shall occur only for voltage steps > 1 V
Common Mode Isolation
Diff. Input Impedance
> 10 kOhm
Noise Rejection
as specified in the PID-A annex E-EMC §5.1
Maximum Fault Voltage
Tolerance:
Emission:
-0.5V to +7.5V
-0.0V to +7.0V
(4)
(3)
HARNESS SPECIFICATION
(general reqts. in PID-A §6.7
Wiring Type
Twisted Shielded Pair - Low capacitance (TSPL)
Core to Core Cap.
< 700 pF
Core to Shield Cap.
< 1 nF
MARS EXPRESS
NOTES: 1.
2.
3.
4.
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -26
non-inverting (true) & inverting (comp) output with ref. To signal ground;
when loaded with differential 1.2 nF (harness & user input capacitance)
with power off: -0.5 V to 7.0 V
Only if ‘Alternative Solution’ of SBDL Interface Circuit is used!
MARS EXPRESS
IFDM-030:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -27
Memory Load Command Timing Diagrams
The phase relation between the three signals for the 16 bit Memory Load Command
shall be as depicted in figure 3.2-6.
t
t
1
1
(4)
(1)
t
t
2
t
4
t
t
5
6
t
9
t
2
3
+t
t
4
9
(2)
t
t
7
B0
t
8
B1 B2 B3 B4 B5 B6 B7 B8
8
B9 B10 B11 B12 B13 B14 B15
(1)
Sampling (address) signal
(2)
Serial data transfer clock signal (16 pulses)
(3)
Memory-Load 16 bit serial data
(Bit 0 is transmitted first to the user and is the most significant bit)
(4)
Time interval corresponding to the interrogation bus interval
t1
t2
t3
t4
t5
t6
t7
t8
t9
=
=
=
=
=
=
<
=
>
61.0
3.8
118.3
26.7
3.8
1.9
3.8
1.4
1.4
µs
µs + 1.5/- 1.0 µs
µs + 1.0/- 1.5 µs
µs + 1.0/- 1.5 µs
µs
µs + 0.5 µs
µs
µs + 0.5/- 0.6 µs
µs
Figure 3.2-6: Memory Load Command Timing Diagram
(3)
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -28
IFDM-040:
The transmission rate shall be 16 Bit within 122 µs (131.072 kbps) as shown on fig
3.2-6.
IFDM-045:
The serial data transfer clock (SDC) shall be in phase with the HF clock with an
accuracy of 0,5 µ (see figure 3.2-7).
A
HF Clock
Serial Data
Transfer Clock
Sampling
Part. A
2 T
2 T
Figure 3.2-7: Phase Relationship between HF-Clock and Serial Data Transfer Clock
3.2.5
Delayed Memory Load Commands (DML)
This type of command is not available to the payload
IFDM-050:
For users which are not following the packet telecommand standard, the DMS shall
deliver on demand Delayed Memory Load Commands (DMLs). Those commands
shall have the same electrical and timing characteristics as standard MLCs (see §
3.2.4), but with a delay time of 100ms between consecutive MLCs on the same
channel.
The user shall ignore commands received within the delay time.
IFDM-052:
DMLs shall be used for PCU and PDU channels only (TBC).
On these channels only DMLs shall be allowed.
IFDM-054:
Any other command type issued after a DML shall not be delayed.
IFDM-056:
The allocation of command slots on the OBDH-Bus shall be such that at least TBD
PCU/PDU DMLs can be executed within 1 second.
MARS EXPRESS
3.3
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -29
Timing and Synchronisation Signals
General Concept
The DMS subsystem shall deliver timing and synchronisation signals to the user, all being
derived from the central on-board clock controlled by an oscillator.
IFDS-001:
Timing information shall be provided with each telemetry packets. It shall allow the
correlation of on-board time with Universal Time (UTC) with an accuracy of 3
msec.
The allocation of the error introduced by the Ground Segment is assumed to be less
than 0.1 msec (TBC).
IFDS-003:
At experiment/user switch-on systematically and at regular intervals based on user
request (typically once per hour, to be agreed with the system responsible) a TC
Time Packet shall be distributed to the experiment/user.
IFDS-005:
In order to enable a user to synchronise to the onboard time the DMS shall distribute
via the RTU a Timer Synchronisation Pulse (TSY) to all users in parallel and with a
repetition rate of 8 seconds.
The rising (first) edge of the TSY. Pulse shall be used to set the user internal timer
to the on-board time transmitted within the TC time packet.
The signal characteristics are defined in the data sheet OTS
IFDS-010:
The user shall maintain the time between two updates of the onboard time. When
requested by the user a High Frequency Clock (HFC) will be distributed via the
RTU to support the maintenance of the time.
The signal characteristics are defined in the data sheet OTS
IFDS-015:
The TSY and HFC signals shall be distributed via redundant, standard balanced
digital lines (SBDL), with the cable shield connected at both sides of the interface to
chassis ground.
The HFC and TSY line interface circuitry including driver, receiver and the interconnecting
harness shall be as shown in figure 3.3-1.
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -30
USER
OBDH
Preferred SBDL Driver
Preferred SBDL Receiver
or
Alternative SBDL Driver
Alternative SBDL Receiver
or
5V
5V
SIGNAL TRUE
TSP
TSP
SIGNAL COMP
Signal GND
Signal GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.3-1: DMS Timing and Sync. Signal Interface and Schematic Circuitry
Chassis GND
MARS EXPRESS
IFDS-020:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -31
DMS Timing and Sync. Signals Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
DMS Timing & Sync Signals
This Interface Data Sheet comprises the following lines:
- High Frequency Clock (HFC)
- Timer Synchronisation Pulse (TSY)
The individual timing characteristics are defined below
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Balanced CMOS driver
Transfer
DC coupled
Zero Reference
Signal ground
Low Level Output Voltage
High Level Output Voltage
Differential Output Voltage
page 1 of 2
Code: OTS
0 V < VOL < 0.5 V
2.5 V < VOH < 5.5 V
Logic ‘1’:
2.0 V < VOD < 5.5 V
Logic ‘0’: -5.5 V < VOD < -2.0 V
|VLogic 1| - |VLogic 0| < 1.0 V
(1)
(1)
Rise and Fall Times
(tr, tf) < 700 ns
(2)
Spurious Noise
As defined in PID-A annex E-EMC §5.1
Current Drive and Sink
Capability
Sufficient to comply with specified tr & tf
Short Circuit
Short circuit proof; current limited to <100 mA
Maximum Fault Voltage
Tolerance:
Emission:
Unbalance of Diff. Output
-0.5V to +7.5V
-0.0V to +7.0V
(2)
(3)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver, CMOS compatible
Transfer
DC coupled
Differential Input Voltage
(-1.0 V < VCM < 1.0 V)
Hysteresis
Low: < - 1 V
High: > + 1 V
Switching shall occur only for voltage steps > 1 V
(4)
Common Mode Isolation
Diff. Input Impedance
> 10 kOhm
Noise Rejection
as specified in the PID-A annex E-EMC §5.1
Maximum Fault Voltage
Tolerance:
Emission:
-0.5V to +7.5V
-0.0V to +7.0V
(3)
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -32
INTERFACE DATA SHEET
Page 2 of 2
I/F Designation:
DMS Timing & Sync Signals
Code: OTS
HARNESS SPECIFICATION
(general reqts. in PID-A §6.7)
Wiring Type
Twisted Shielded Pair - Low capacitance (TSPL)
Core to Core Cap.
< 700 pF
Core to Shield Cap.
< 1 nF
NOTES: 1. non-inverting (true) & inverting (comp) output with ref. to signal ground;
2. when loaded with differential 1.2 nF (harness & user input capacitance)
3. with power off: -0.5 V to 7.0 V
4. Only if ‘Alternative Solution’ of SBDL Interface Circuit is used!
INDIVIDUAL TIMING CHARACTERISTICS
Frequency:
High Frequency
131.072 kHz (217)
(5)
Mark
to
space
ratio:
1:1
±
5%
Clock (HFC):
Phase relation:
in phase with the SDT clock
(see figure 3.2-7)
Accuracy:
Better than
Short term: 3*10-7 / day
Long term: 4*10-6 / year
Pulse width
3.8 to 62 µsec
Timer Sync. Pulse
Jitter
< 2 µsec
(TSY):
NOTES: 5. Nominal frequency; variable with the DMS oscillator initial setting
MARS EXPRESS
3.4
3.4.1
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -33
Telemetry Channels
Serial Digital Telemetry (SDT)
General Concept
a)
The DMS shall provide Serial Digital Telemetry (SDT) input channels for acquisition
of housekeeping data and experiment scientific data. The purpose of the interface is to
transfer, in serial form, 16-bit data words from the user to the RTU.
b)
The SDT interface consists of three signal lines issued from the RTU:
one data line (serial 16 Bit NRZ-L)
one clock line (serial data transfer clock)
one sampling address line
IFDT-001:
Each user shall be provided with only one redundant Serial Data Transfer Clock
(SDC) which shall be shared between Serial Digital Telemetry and Memory Load
Command.
IFDT-005:
One redundant line for serial digital data (SDD) shall be acquired by the DMS from
each SDT user.
One redundant sampling address line (SDS) shall be provided by the DMS to each
SDT user.
IFDT-007:
The transfer of the SDT data shall take place during the sampling pulse at a rate
defined by the clock for serial data transfer.
The Most Significant Bit (MSB) of the serial data shall be transmitted first from the
user to the RTU.
The acquisition of the following bits shall then be controlled by the trailing edge of
the transfer clock.
IFDT-010:
The three SDT signals shall be transmitted via a Standard Balanced Digital Link,
with the cable shield connected at both sides of the interface to chassis ground.
IFDT-015:
The serial digital data provided by the user shall be a serial NRZ-L PCM signal.
IFDT-020:
Outside of the serial data transfer period, the quiescent state of the 'true' lines shall
be the high level.
The clock line may be active outside the serial data transfer period.
The serial 16-bit digital channel interface circuitry including driver, receiver and the
interconnection harness shall be as shown in figure 3.4-1 and 3.4-2.
MARS EXPRESS
RTU
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -34
USER
Memory Load Sampling
(address n)
MLC to User at
address y
Memory Load Sampling
(address 1)
MLC to
User at
address x
Memory Load Data
Serial Data Transfer Clock
Serial Telemetry Data
Data from
User at
address 1
Serial Telemetry Sampling
(address 1)
Serial Telemetry Sampling
(address n)
Data from
User at
address n
Figure 3.4-1: Serial 16 Bit Digital Telemetry Interface
(M/L Command is indicated by hairlines)
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -35
USER
OBDH
Preferred SBDL Driver
Preferred SBDL Receiver
or
Alternative SBDL Driver
Alternative SBDL Receiver
or
5V
5V
SIGNAL TRUE
TSP
TSP
SIGNAL COMP
Signal GND
Signal GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units.
Figure 3.4-2: Serial 16 Bit Digital Sampling and Transfer Clock Line Interface
and Schematic Circuitry
Chassis GND
MARS EXPRESS
IFDT-020:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -36
Serial 16 Bit Digital Telemetry Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Serial 16 Bit Digital Telemetry
The interface comprises the following three lines:
- Serial Digital Telemetry Data (SDD)
- Serial Data Transfer Clock (SDC)
- Serial Digital Telemetry Sampling (SDS)
Time relation defined in figure 3.4-4
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Balanced CMOS driver
Transfer
DC coupled
Zero Reference
Signal ground
Coding
NRZ-L
Bit Rate
262 kbps (Burst)
Low Level Output Voltage
0 V < VOL < 0.5 V
High Level Output Voltage
2.5 V < VOH < 5.5 V
Differential Output Voltage
Logic ‘1’:
2.0 V < VOD < 5.5 V
Logic ‘0’: -5.5 V < VOD < -2.0 V
Unbalance of Diff. Output
|VLogic 1| - |VLogic 0| < 1.0 V
Rise and Fall Times
Spurious Noise
Current Drive and
Sink Capability
Page 1 of 1
Code: SDT
(tr, tf) < 700 ns
As specified in PID-A annex E-EMC §5.1
Sufficient to comply with specified tr & tf
Short Circuit
Maximum Fault Voltage
Short circuit proof; current limited to <100 mA
Tolerance: -0.5V to +7.5V
Emission: -0.0V to +7.0V
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver, CMOS compatible
Transfer
DC coupled
Differential Input Voltage
(-1.0 V < VCM < 1.0 V)
Hysteresis
Common Mode Isolation
Diff. Input Impedance
Input Impedance to signal
ground (data line only)
Low: <- 1 V
High: > + 1 V
Switching shall occur only for voltage steps > 1 V; the
DMS receiver hysteresis is active only during the
acquisition of data
(1)
(1)
(2)
(2)
(3)
(4)
> 10 kOhm
During acquisition:
> 100 kOhm
Outside acquisition:
> 20 MOhm
RTU with power OFF
> 1 kOhm
Noise Rejection
As specified in the PID-A annex E-EMC §5.1
Maximum Fault Voltage
Tolerance: -0.5V to +7.5V
(3)
Emission: -0.0V to +7.0V
HARNESS SPECIFICATION
(general reqts. in PID-A § 6.7)
Wiring Type
Twisted Shielded Pair - Low capacitance (TSPL)
Core to Core Cap.
< 700 pF
Core to Shield Cap.
< 1 nF
MARS EXPRESS
NOTES: 1.
2.
3.
4.
Ref
:
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: 02 Rev. : 00
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:
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:
E-IDS -37
non-inverting (true) & inverting (comp) output with ref. to signal ground;
when loaded with differential 1.2 nF (harness & user input capacitance)
with power off: -0.5 V to 7.0 V
Only if ‘Alternative Solution’ of SBDL Interface Circuit is used!
MARS EXPRESS
IFDT-025:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -38
Serial 16 Bit Digital Telemetry Timing Diagrams
The phase relation between the three signals for the 16 bit serial channel shall be as
shown in figure 3.4-4.
t
t
t
1
t
2
t
t
4
t
5
6
t
9
t
2
1
(4)
(1)
3
+t
t
4
9
(2)
t
t
7
B0
t
8
B1 B2 B3 B4 B5 B6 B7 B8
(1)
(2)
(3)
8
B9 B10 B11 B12 B13 B14 B15
Sampling signal at the user's input
Serial data transfer clock signal at the user's input
User's serial data at the RTU input
(Bit 0 is transmitted first by the user and is the most significant bit)
Time interval corresponding to the interrogation bus interval
(4)
t1
t2
t3
t4
t5
t6
t7
t8
t9
=
=
=
=
=
=
<
<
>
61.0
3.8
118.3
26.7
3.8
1.9
15.3
1.1
1.4
µs
µs + 1 µs
µs + 1 µs
µs + 1 µs
µs
µs + 0.5 µs
µs
µs
µs
Figure 3.4-4: Serial 16 Bit Digital Timing Diagram
(3)
MARS EXPRESS
Ref
:
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Issue
: 02 Rev. : 00
Date
:
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:
E-IDS -39
IFDT-035:
The acquisition rate shall be 16 Bit within 122 µs (131.072 kbps) as shown on fig
3.2-6.
IFDT-040:
The time interval (start to start) between read outs of consecutive16 bit words shall
be 122 µs 1 µs.
The user is responsible to reload the channel register if consecutive read-out on the same
telemetry channel is required.
The serial data transfer clock shall be in phase with the HF clock as defined in § 3.2.
MARS EXPRESS
3.4.2
Ref
:
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: 02 Rev. : 00
Date
:
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:
E-IDS -40
Analogue Channels (ANS)
General Concept
a)
The DMS shall provide analogue input channels to the user. The analogue data shall
be presented by the user in the form of a voltage varying between two defined limits.
This voltage shall be sampled regularly, converted analogue to digital and issued as an
8 Bit TM word, the most significant bit (MSB) being transmitted first.
b)
Two states are defined for the analogue input:
c)
during acquisition:
outside acquisition:
the input gate is opened
the input gate is closed
The acquisition of the analogue channels by the RTU shall be such as to allow the A/D
conversion of one analogue voltage input in each interrogation bus interval (32-bit
long time slot on the interrogation bus).
IFDT-100:
IFDT-105:
IFDT-110:
IFDT-115:
The range of the analogue parameter shall be scaled in such a way that it is spread
over the full input range of the DMS (0 to 5.12 V)
The A/D converter accuracy including temperature and voltage variations, lifetime
and radiation shall be better than 40 mV (2 LSB).
The accuracy of the measurement of an analogue input shall not be influenced by the
voltage of the previously sampled analogue input.
The analogue signal shall be transmitted via twisted shielded pairs.
The cable shield shall be connected at both sides of the interface to chassis ground
either via the connector housing or via a connector pin.
The analogue channel interface circuitry including driver, receiver and the interconnection
harness shall be as shown in figure 3.4-5.
MARS EXPRESS
Ref
:
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: 02 Rev. : 00
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:
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:
E-IDS -41
USER
MEX-MMT-SP-0007
OBDH
signal receiver
V+
ANALOG
TSP
TSP
ANALOG RTN
V-
Signal GND
Signal GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.4-5: Analogue Interface and Schematic Circuitry
Chassis GND
MARS EXPRESS
IFDT-120:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -42
Analogue Channel Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Analogue Telemetry
SOURCE CIRCUIT SPECIFICATION
Circuit Type
single ended
Transfer
DC coupled
Zero Reference
Signal ground
Voltage range
Current Drive Capability
Output Impedance
page 1 of 1
Code: ANS
0 to 5.12 V
Up to 10 mA
< 5 kOhm
Spurious Noise
As specified in PID-A annex E-EMC §5.1
Max. Fault Voltage
Tolerance:
Emission:
-16.5 V to +16.5 V
-1 V to +12 V
(1)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver with multiplexed input
Transfer
DC coupled
Input Impedance
during acquisition 6 MOhm < R < 50 MOhm
outside acquisition: > 20 MOhm
RTU with power OFF:
> 1 kOhm
Input Capacitance
during acquisition: < 250 pF
outside acquisition: < 180 pF
RTU with power OFF:
< 180 pF
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +14 V
-15.8 V to +15.8 V
(1)
HARNESS SPECIFICATION
(general reqts. in PID-A §6.7)
Wiring Type
Twisted Shielded N-tuple (TSn)
NOTES: 1. With an overvoltage source impedance (series res.) of 1.5 kOhm
MARS EXPRESS
3.4.3
Ref
:
MEX-MMT-SP-0007
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: 02 Rev. : 00
Date
:
06.07.99
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:
E-IDS -43
Bi-Level Digital Channels (BLD)
General Concept
a)
Each bi-level digital channel shall be used to acquire one of a number of discrete
status bits of DMS users.
b)
Each bi-level digital channel corresponds to one bit of an 8-bit telemetry word.
IFDT-200:
IFDT-205:
IFDT-210:
IFDT-215:
The bi-level digital information shall be presented by the user in the form of a
voltage that can assume one of two distinct values:
- an "ON" (logical "1") shall be represented by a positive voltage
- an "OFF" (logical "0") shall be represented by a zero voltage
with respect to the ground reference.
The acquisition of the bi-level channels shall be organised in such a way as to
collect eight bi-level inputs during one interrogation bus interval.
Each channel shall be allocated a specific bit position within an 8-bit telemetry
word. The channel, which has the lowest address number, shall be put as the MSB
(bit 0). The serialisation of the channels shall be performed by the RTU.
The Bi-Level Digital data shall be transmitted via twisted shielded pairs.
The cable shield shall be connected at both sides of the interface to chassis ground
either via the connector housing or via a connector pin.
The Bi-Level Digital interface circuitry including driver, receiver and the interconnection
harness shall be as shown in figure 3.4-6.
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -44
OBDH
USER
V
signal receiver
V+
BI-LEVEL DIGITAL
TSP
TSP
BI-LEVEL DIGITAL.RTN
V-
Signal GND
Signal GND
Chassis GND
The cable shield may be connected directly to the connector housings or grounded inside the units .
Figure 3.4-6: Bi-Level Digital Interface and Schematic Circuitry
Chassis GND
MARS EXPRESS
IFDT-220:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -45
Bi-Level Digital Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Bi-Level Digital Telemetry
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Single ended
Transfer
DC coupled
Zero Reference
Signal ground
Low Level Output Voltage
High Level Output Voltage
0 V < VOL < 0.5 V (Logical "0" Level)
4.5 V < VOH < 5.5 V (Logical "1" Level)
Current Drive Capability
Output Impedance
> 5 mA
< 7.5 kOhm
Max. Fault Voltage
Tolerance:
Emission:
-16.5 V to +16.5 V
-1 V to +12 V
page 1 of 1
Code: BLD
(1)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver with multiplexed input
Transfer
DC coupled
Input Voltage Threshold
2 V ± 0.5 V
Input Impedance
During acquisition: > 100 kOhm
outside acquisition: > 20 Mohm
RTU with power OFF:
> 1 kOhm
Input Capacitance
During acquisition: < 250 pF
outside acquisition: < 180 pF
RTU with power OFF:
< 180 pF
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +14 V
-15.8 V to +15.8 V
(1)
HARNESS SPECIFICATION
(general reqts in PID-A §6.7)
Wiring Type
Twisted Shielded N-tuple (TSn)
NOTES: 1. with an overvoltage source impedance (series res.) of 1.5 kOhm
MARS EXPRESS
3.4.4
Ref
:
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: 02 Rev. : 00
Date
:
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:
E-IDS -46
Relay/Switch Status Channels (RSS)
General Concept
a) The RTU shall acquire via the Relay/Switch Status inputs the open/closed status of a
relay/switch contact for conversion into a TM bit.
b) The receiver utilises a pull-up resistor for the detection of the Relay/Switch Status. The
comparator input is referenced to signal ground. A closed contact corresponds to a "0"
level and an open contact to a "1" level.
A principle diagram is given in figure 3.4-7.
IFDT-300:
IFDT-305:
IFDT-310:
IFDT-312:
The driver shall be constituted by the Relay/Switch contact itself, which is isolated
from the ground. The same kind of receiver as for Bi-Level digital channels is used,
but with one pull-up resistor added at input level. The signal shall be transmitted via
twisted pair or twisted N-tuple lines.
The acquisition of the Relay/Switch Status channels shall be organised in such a
way as to collect eight Relay/Switch Status inputs during one interrogation bus
interval.
Each channel shall be allocated a specific bit position within an 8-bit telemetry word
in such a way, that the channel, which has the lowest address number, is put at the
MSB (Bit 0). The necessary serialisation of the channels shall be performed by the
RTU.
A Relay/Switch status shall be transmitted via twisted pairs
The cable shield shall be connected at both sides of the interface to chassis ground
either via the connector housing or via a connector pin.
The Relay Switch Status interface circuitry including source, receiver and interconnection
harness shall be as shown in figure 3.4-7.
MARS EXPRESS
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -47
V+
Signal source
Signal receiver
Figure 3.4-7: General Relay/Switch Status Interface
USER
OBDH
V+
Signal Receiver
V+
RELAY/SWITCH STATUS
TP
TP
Switch
n
2 1
RELAY/SWITCH STATUS.RTN
from other
switches
V-
Signal GND
Chassis GND
Figure 3.4-8: Relay/Switch Status interface RTU/Load and Schematic Circuitry
MARS EXPRESS
IFDT-315:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -48
Relay/Switch Status Telemetry Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Relay/Switch Status T/M
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Relay contact
Transfer
DC coupled
Contact Current Capability
> 10 mA
Resistance
Closed status:
< 50 Ohm
opened status: > 1 MOhm
Max. Fault Voltage
Tolerance:
Emission:
-16.5 V to +16.5 V
not applicable
Page 1 of 1
Code: RSS
(1)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver with pull-up
Resistor and multiplexed inputs
Transfer
DC coupled
Input Voltage Threshold
2 V ± 0.5 V
Voltage provision
Current provision
5V nominal, via series resistor
0.1 to 10 mA
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +14 V
-15.8 V to +15.8 V
(1)
HARNESS SPECIFICATION
(general reqts in PID-A §6.7)
Wiring Type
Twisted Pair (TP), Twisted n-tuple (Tn)
NOTES: 1. with an overvoltage source impedance of 1.5 kOhm
MARS EXPRESS
3.5
3.5.1
Ref
:
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: 02 Rev. : 00
Date
:
06.07.99
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:
E-IDS -49
Temperature Housekeeping Channels
Standard Temperature HK Channels (ANC)
For acquisition of Standard Temperature HK values, the DMS shall be able to directly
interface with the thermistors.
For that purpose the thermistors shall be powered by the DMS as shown on figure 3.5.1-1.
The resulting voltage shall be utilised to feed a dedicated analogue channel.
Such channels are called Analogue Conditioned (ANC) channels They shall be treated by the
DMS (RTU) in the same way as standard analogue channels specified in §3.4.2.
IFDT-400:
The thermistor voltage acquired by the analogue channel shall vary with the
thermistor temperature according to figure 3.5.1-2.
IFDT-405:
The A/D converter accuracy including temperature and voltage variations, lifetime
and radiation shall be less than 40 mV (2 LSB).
The DMS measurement accuracy and the overall measurement accuracy (including
DMS accuracy and thermistor tolerance) for the various thermistor types as a
function of temperature are shown in figure 3.5.1-2.
IFDT-410:
The accuracy of the measurement of an ANC input shall not be influenced by the
voltage of the previously sampled ANC input.
IFDT-415:
The signal shall be transmitted via twisted pairs.
The cable shield shall be connected at both sides of the interface to chassis ground
either via the connector housing or via a connector pin.
The Standard Temperature Channel interface including source, receiver and the
interconnection harness shall be as shown in figure 3.5.1-1.
MARS EXPRESS
Ref
:
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: 02 Rev. : 00
Date
:
06.07.99
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:
E-IDS -50
USER
MEX-MMT-SP-0007
OBDH
V+
Signal Receiver
R1
V+
COND. ANALOG
TP
TP
R2
Thermistor
n
2 1
COND. ANALOG RTN
from other
thermistors
V-
Signal GND
Chassis GND
Figure 3.5.1-1: Conditioned Analogue Interface and Schematic Circuitry
MARS EXPRESS
IFDT-420:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -51
Standard Temperature Channel Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Standard Temperature Channel
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Thermistor
Transfer
DC coupled
Thermistor Type
Type A:
Type B:
Yellowspring YSI 44907
Rosemount 118MF (PT2000)
Operating Temperature Range
Type A:
Type B:
from -55 to +90 deg C
from -200 to +150 deg C
Max. Fault Voltage
Tolerance:
Emission:
-16.5 V to +16.5 V
not applicable
page 1 of 1
Code: ANC
(1)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Conditioning circuitry
Transfer
DC coupled
Calibration Resistors R1/R2
(see fig. 3.5.1.1)
Type A: R1 = 100 kOhm; R2 = 100 kOhm
Type B: R1 = 4750 Ohm; R2 = Ohm
Conditioning Module Supply
Voltage
10 V
HK-Voltage
The HK voltage acquired by the subsequent analogue
channel shall vary with the thermistor temperature
between 0 and 5.12V
Overall Accuracy
Max. Fault Voltage
40 mV (2 LSB)
Tolerance:
Emission:
-3 V to +14 V
-15.8 V to +15.8 V
(1)
HARNESS SPECIFICATION
(general reqts. in PID-A § 6.7)
Wiring Type
Twisted Pair (TP), Twisted N-tuple (Tn)
NOTES: 1. With an overvoltage source impedance of 1.5 kOhm
MARS EXPRESS
Ref
:
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: 02 Rev. : 00
Date
:
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:
E-IDS -52
12.0
DMS Measurement Accuracy [+/-°C]
Overall Measurement Accuracy (incl. Thermistor Tolerance) [+/-°C]
5.50
11.0
90
85
80
75
70
65
60
55
0.0
50
0.00
45
1.0
40
0.50
35
2.0
30
1.00
25
3.0
20
1.50
15
4.0
10
2.00
5
5.0
0
2.50
-5
6.0
-10
3.00
-15
7.0
-20
3.50
-25
8.0
-30
4.00
-35
9.0
-40
4.50
-45
10.0
-50
5.00
Measurement Accurracy [+/- °C]
HK-Voltage [V]
6.00
-55
HK-Voltage [V]
Type A (Yellowspring YSI-44907)
Temperature
20.0
HK-Voltage [V]
DMS Measurement Accuracy [+/-°C]
Overall Measurement Accuracy (incl. Thermistor Tolerance) [+/-°C]
4.50
18.0
4.00
16.0
3.50
14.0
3.00
12.0
2.50
10.0
2.00
8.0
1.50
6.0
1.00
4.0
0.50
2.0
0.00
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
Tem perature
Figure 3.5.1-2: Standard Temp. Thermistor HK-Voltage versus Temperature
120
140
0.0
160
Measurement Accuracy [+/-°C]
HK - Voltage [V]
Type B (Rosemount 118MF)
5.00
MARS EXPRESS
3.5.2
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
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:
E-IDS -53
Platinum Thermistor HK Channels (ANP)
For acquisition of Platinum Thermistor HK values, the DMS shall be able to interface with
platinum thermistors.
For that purpose the thermistors shall be powered by the DMS and conditioned by a
Wheatstone-Bridge circuit as shown on figure3.5.2-1. The resulting voltage shall be amplified
before feeding the dedicated multiplexed analogue channel.
Such channels are called ANP (Analogue Platinum) channel. They shall be treated by the
DMS (RTU) in the same way as standard analogue channels.
IFDT-450:
The Platinum thermistor voltage after conditioning and amplification by the
analogue channel shall vary with the thermistor temperature according to figure
3.5.2-2.
IFDT-455:
The A/D converter accuracy including temperature and voltage variations, lifetime
and radiation shall be less than 40 mV (2 LSB).
The DMS measurement accuracy and the overall measurement accuracy (including
DMS accuracy and thermistor tolerance) for the various thermistor types as a
function of temperature are shown in figure 3.5.2-2.
Note:
For the accuracy of the bridge circuit, the following parameters shall be taken into
account:
- two-wire- or three-wire-bridge design
- the tolerance and temperature coefficient of the bridge resistors
- the accuracy and stability of the conditioning voltage supply
- self heating of the thermistor
IFDT-460:
The accuracy of the measurement an ANP input shall not be influenced by the
voltage of the previously sampled ANP input.
IFDT-465:
The signal shall be transmitted via twisted pairs (two-wire-bridge) or a twisted-ntuple (three-wire-bridge) cable.
The platinum thermistor channel interface circuitry including source, receiver and
interconnecting harness shall be as shown in figure 3.5.2-1.
MARS EXPRESS
Ref
:
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Issue
: 02 Rev. : 00
Date
:
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:
E-IDS -54
Wheatstone Bridge
Condit. Amplifier
V+
V+
C1
R1
R2
R5
R4
BRIDGE OUT
TP/Tn
TP/Tn
Platinum
Thermistor
R3
V-
BRIDGE IN
BRIDGE RETURN
Three-Wire-Bridge
Tw o-Wire-Bridge
Signal GND
Chassis GND
Bridge return: to be reviewed on case by case basis
Figure 3.5.2-1: Platinum Temperature Channel
Interface and Schematic Circuitry
MARS EXPRESS
IFDT-470:
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -55
Platinum Temperature Channel Interface Characteristics:
INTERFACE DATA SHEET
I/F Designation:
Special Temperature Channel
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Platinum Thermistor
Transfer
DC coupled
page 1 of 1
Code: ANP
Thermistor Type
Type A:
Type B:
Rosemount 118MF (PT500) TBC
PT 200 TBC
Operating Temperature Range
Type A:
Type B:
from -200 to +150 deg C
from -200 to +150 deg C
Max. Fault Voltage
Tolerance:
Emission:
-16.5 V to +16.5 V
not applicable
TBC
(1)
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Conditioning circuitry
Transfer
DC coupled
Bridge Resistors (see fig.
3.5.2-1)
Amplifier Gain:
R1 =
R2 =
R3 =
8
Type A:
10.7 kOhm
10.7 kOhm
84.5 Ohm
TBC
Type B:
TBD kOhm TBC
TBD kOhm TBC
TBD Ohm; TBC
19
TBC
Conditioning Module Supply
Voltage
10 V
HK-Voltage
The HK voltage acquired by the subsequent analogue
channel shall vary with the thermistor temperature
between 0 and 5V
Overall Accuracy
< ± 1%
Max. Fault Voltage
Tolerance:
Emission:
-3 V to +14 V
-15.8 V to +15.8 V
(2)
(1)
HARNESS SPECIFICATION
(general reqts. in PID-A §6.7)
Wiring Type
Twisted Pair (TP), Twisted N-tuple (Tn)
(3)
NOTES: 1. With an overvoltage source impedance of 1.5 kOhm
2. The HK voltage is understood as the platinum thermistor bridge output
voltage conditioned by an amplifier stage (output voltage of amplifier)
3. Depending if two- or three-wire-bridge design used
MARS EXPRESS
Ref
:
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: 02 Rev. : 00
Date
:
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:
E-IDS -56
20.0
HK-Volt. [V]
DMS Measurement Accuracy [+/-°C]
4.50
18.0
Overall Measurement Accuracy (incl. Thermistor Tolerance) [+/-°C]
4.00
16.0
3.50
14.0
3.00
12.0
2.50
10.0
2.00
8.0
1.50
6.0
1.00
4.0
0.50
2.0
0.00
-200
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
Temperature
ANP Type B: TBD
Figure 3.5-2: Special Temperature HK-Voltage versus Temperature
100
120
140
0.0
160
Measurement Accuracy [+/-°C]
HK - Voltage [V]
ANP-Type A: Rosemount 118MF (PT 500)
5.00
MARS EXPRESS
3.6
Ref
:
MEX-MMT-SP-0007
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: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -57
Converter Synchronisation
Special Converter Synchronisation lines are not foreseen (see also §1.1, IFOD-015)
MARS EXPRESS
3.7
Ref
:
MEX-MMT-SP-0007
Issue
: 02 Rev. : 00
Date
:
06.07.99
Page
:
E-IDS -58
High Rate Data Interface IEEE 1355 (HRD)
The requirements defined below shall be considered preliminary as long as a
baseline for the interface between the new (wrt to Rosetta) SSMM and the
IEEE users has not been defined and agreed.
General Concept
The purpose of the High Rate Data (HRD) interface is to provide a point-to-point serial data
link between two devices.
IFDH-001:
The high rate data interface shall be implemented as DS-DE link (Data/Strobe
encoding, differential electrical transmission)
IFDH-005:
A high rate data interface shall consist of a link input (DS-DE-link) and a link
output (DS-DE-link), each comprising two differential point-to-point connections:
O
DS_Data
(serial bit stream)
O
DS_Strobe
(decoded strobe)
Issued from the active data source (see figure 3.7-1).
IFDH-010:
The data-strobe system shall carry an ‘encoded’ clock as shown in figure 3.7-2. The
receiving device shall synchronise to the incoming data (asynchronous).
IFDH-012:
At Power on, the DS link outputs shall hold both the data and strobe signals at logic
‘0’ (i.e. the reset level) until started/operating.
The first bit transmitted after a reset shall be a zero. This implies that the first
transition low to high is on the strobe line.
In case a unit comprises multiple link inputs (i.e. redundant or multiplexed inputs),
the following conditions at a link shall not invalidate the other links:
- link drivers are not powered
- link drivers are in high impedance state
- link driver(s) is(are) permanently at high or low level
Note:
The high rate data signals will be serial bit-streams:
- A bit '1' corresponds to a positive differential voltage (high level voltage of true
line / low level of comp line, with respect to signal ground).
- A bit '0' corresponds to a negative differential voltage (low level voltage of true
line / high level of comp line, with respect to signal ground).
IFDH-015:
Each connection shall be established via an impedance controlled transmission line
(see wiring type in IFDH-020) with the cable shield connected at both sides of the
interface to chassis ground via the connector housing.
.
MARS EXPRESS
IFDH-017:
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The interface circuitry including driver, receiver and the interconnection harness
shall be as shown in figures 3.7-1
The transmission line shall be terminated either at the driver outputs (source
termination) or at the receiver inputs (shunt termination) by termination resistors,
depending on the interface implementation (see IFDH-020).
Device X
Device Y
TxData
RxData
TxStrobe
RxStrobe
RxData
TxData
RxStrobe
TxStrobe
Figure 3.7-1: High Rate Data Interface
0 1 0 0 1 1 0 1 1 0
DS_Data
DS_Strobe
Note: The strobe line shall change state each time when the
next bit on the accompanying data line has the same
value than its previous one. (Clock recovery by X-ORing)
Figure 3.7-2: DS-Link Signal Encoding
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RECEIVER
DRIVER
5V
5V
Rso
56
Rso
1/4
HS-26C31RH
Rsi
SIGNAL.TRUE
TCX
TCX
1k
Rsi
SIGNAL.COMP
56
1/4
HS-26C32RH
1k
Signal GND
Signal GND
Chassis GND
with TCX = TwinAx cable, GORE GSC 6509 Rev.6
Chassis GND
Figure 3.7-3a: High Rate Data Line I/F and Schematic Circuitry - Standard S/C Circuitry
DRIVER
RECEIVER
5V
5V
SIGNAL.TRUE
TCX
TCX
Rt
120
SIGNAL.COMP
1/4
HS-26C32RH
or equivalent
1/4
HS-26C31RH
or equivalent
Signal GND
Chassis GND
Signal GND
TCX = TwinAx cable
GORE GSC 6509 Rev.6 on S/C
GORE GSC 7101 Rev.B on ground
Figure 3.7-3b: High Rate Data Line I/F and Schematic Circuitry - SSMM/EGSE
Chassis GND
MARS EXPRESS
IFDH-020:
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High Rate Data Link Interface Characteristics:
INTERFACE DATA SHEET
Page 1 of 2
I/F Designation:
High Rate Data Link
Code: HRD
The interface comprises the following lines with different implementations depending on line
termination approach:
- TxData
(HDO)
- TxStrobe (HSO)
Standard S/C
Source termination
- RxData
(HDI)
Circuitry
(see figure 3.7-3a)
- RxStrobe (HSI)
- TxData
(EDO)
- TxStrobe (ESO)
S/C – EGSE
Receiver termination
- RxData
(EDI)
Circuitry
(see figure 3.7-3b)
- RxStrobe (ESI)
Time relation defined in figure 3.7-4
SOURCE CIRCUIT SPECIFICATION
Circuit Type
Balanced CMOS driver (HS-26C31RH)
Transfer
DC coupled
Zero Reference
Signal ground
Coding
Transfer Bit Rate
IEEE1355, DS-Link
up to 25 Mbits/s (link capability) TBC
Serial Output Resistor Rso
- 56 Ohm (HDO, HSO, HDI, HSI)
- N\A (EDO, ESO, EDI, ESI)
Low Level Output Voltage
High Level Output Voltage
Differential Output Voltage
0 V < VOL < 0.55 V
2.45 V < VOH < 5.5 V
logic 1:
+1.9 V < VOD < +5.5 V
logic 0:
- 5.5 V < VOD < -1.9 V
(tr, tf) < 40 ns
as defined in the EMC spec., RO-DSS-RS-1002
Sufficient to comply with specified tr & tf
Rise and Fall Times
Spurious Noise
Current Drive and
Sink Capability
Short Circuit
Maximum Fault Voltage
short circuit proof; current limited to <150 mA
Tolerance: -0.5V to +7.5V
Emission:
-0.0V to +7.0V
(1)
(2)
(2)
(3)
(4)
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INTERFACE DATA SHEET
I/F Designation:
High Rate Data Link
RECEIVER CIRCUIT SPECIFICATION
Circuit Type
Differential receiver, CMOS (HS-26C32RH)
Transfer
DC coupled
Differential Input Voltage
Low: VID < - 0.6 V
High: VID > + 0.6 V
Common Mode Isolation
as defined in the EMC spec., RO-DSS-RS-1002
Serial Input Resistor Rsi
- 1 kOhm
Polarisation Resistor Rp
- 6.8 kOhm
Termination Resistor Rt
- N/A (HDO, HSO, HDI, HSI)
- 120 Ohm (EDO, ESO, EDI, ESI)
Diff. Input Impedance
> 4 k (HDO, HSO, HDI, HSI)
120 (EDO, ESO, EDI, ESI)
Noise Rejection
as defined in the EMC spec., RO-DSS-RS-1002
Maximum Fault Voltage
Tolerance:
Emission:
page 2 of 2
Code: HRD
-0.5 V to +7.5 V
-0.0 V to +7.0 V
HARNESS SPECIFICATION
(general reqts. in PID-A para 6.7)
Wiring Type
120 Ohm TwinAx (TCX)
Max. Cable Length
10 m for onboard-links
(30m for S/C - EGSE-links)
NOTES: 1.
Transfer Bit Rate defines the link speed, not the data throughput
2. non-inverting (true) & inverting (comp) output with ref. to signal ground;
when loaded with cable and user input impedance
3. when loaded with cable and user input impedance
4.
with power off -0.5 V to +7.0 V
5. Cable to be used:
on spacecraft: ESA/SCC 3902/002-23 (AWG28)
on ground:
S/C cable or not space qualified equivalent
(5)
MARS EXPRESS
IFDH-025:
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High Rate Data Link Timing Diagrams:
The timing relations between the data and the strobe signal shall be as shown in
figure 3.7-4.
0
Digital Data
1
0
0
1
1
0
1
DS Data
DS Strobe
Comp
Data
True
tbitp
tdsi
tdsi
Comp
Strobe
True
tbitp
Data
Strobe
Comp
True
2 x tdso
2 x tdso
Figure 3.7-4: High Rate Data DS-Link Timings
1
0
MARS EXPRESS
IFDH-030:
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The timing values shown in figure 3.6.2-7 shall be as follows, valid for max. and
lower speed transmissions:
Min
Max
Parameter
Tdso
-
5 ns
output skew between consecutive DS data or strobe
edges (data or strobe true (resp. comp) to data or
strobe true (resp. comp) line
Tdsi
20 ns
-
separation time between consecutive edges on the
data and strobe inputs;
an implementation shall not require this to be
greater than the specified value
Tbitp
80 ns
750 ns
sustainable input bit period that shall be accepted
for the Transfer Bit Rate
Symbol
The disconnect time-out period shall be 850ns as defined in the IEEE Std 13551995 (para 5.7.5.2).
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Command Distribution and Data Acquisition Protocols
Telecommands are distributed on board MARS EXPRESS by the DMS-computer to the users
via the OBDH-Bus and the RTUs as discrete or packet telecommands.
Standard Telemetry and Science Data from the users are acquired on board MARS EXPRESS
by the DMS-computer via the OBDH-Bus and the RTUs as TM-Blocks containing TM
Source Packets. Discrete telemetry is acquired, conditioned, serialized and packetized by the
RTU
The TC distribution channels are defined §3.2 of this annex.
The standard TM channels for housekeeping and science data are defined in §3.4, §3.5 of this
annex.
The channels for High Rate (Science) Data from the Experiments to the DMS (SSMM) are
defined in § 4.5 of this annex.
General requirements on TC and TM via the OBDH Bus are defined below.
IFDC-001:
The theoretical OBDH bus slots of 16384 interrogations per second cycle shall be
allocated after system-initialisation as follows:
12,5% max
for Non-Packet TC distribution and TM acquisition
(See 4.2b and 4.3b).
25,0% max.
for Packet-TC users, (see 4.2a)
62,5% min.
for TM-Block acquisitions (see 4.3a)
Note:
IFDC-005:
The allocated slots may be distributed over the one second
Cycle. This includes the DMS and OBDH-Bus overhead.
This overhead shall not be more than 5% TBC (for worst
case ref. to IFDC-202, last bullet).
If slots of the Packet-TC users are not used for commanding, they shall
dynamically be re-allocated for that cycle to the TM-Block acquisition.
MARS EXPRESS
4.1
Packet Structure
4.1.1
Telemetry Source Packet Structure
IFDC-010:
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The Packet Terminals shall provide their telemetry data formatted in source packets
to the RTU.
All telemetry source packets shall conform to the structure defined in the SGICD
§5.1.
The assignment of the application ID for the TC packets is provided in the SGICD (MEXESC-IF-5001, Appendix 3).
IFDC-020:
4.1.2
IFDC-050:
Source packets shall not be filled up with dummy data. Exceptions to this
requirement have to be agreed by the Prime.
Telecommand Packet Structure
The Packet Terminal shall receive telecommands formatted in telecommand packets
from the RTU.
All telecommand packets shall conform to the structure defined in SGICD §6.1.
The assignment of the application ID for the TM packets is provided in the SGICD (MEXESC-IF-5001, Appendix 3).
MARS EXPRESS
4.2
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Command Distribution
The requirements defined in this chapter shall be considered as preliminary
requirements - based on Rosetta DMS software- as long as a DMS Software
Requirement Document (SRD) has not been issued for Mars Express.
The intention is to copy the Rosetta SRD but still some requirements or
parameters may need to be adapted to the specificity (mission, number of
instruments, new SSMM, etc.) of Mars Express.
On/Off-Commands (HPC and EHP) shall be distributed via discrete channels and do not
require a specific protocol.
The distribution of serial digital commands is subdivided into the following categories:
a) Packet TC users (i.e. all payload instruments):
The DMS distributes TC packets (TCP) to the users. The user application software shall then
decode them.
IFDC-101:
The telecommand packets shall be distributed from the RTU to the experiment/user
via the MLC Channel.
IFDC-105:
The Packet TC user shall cope with the maximum physical data transfer rate of the
MLC-I/F and shall buffer the telecommand packets accordingly
(see also paragraph 3.2.4).
However, the TC throughput rate shall not exceed 16 kbits/sec; the user shall
comply with this rate.
Note: No artificial slow-down of commanding rate to the user will be supported by
the DMS.
IFDC-107:
The DMS shall always support the maximum TC throughput rate of 16 kbits/sec and
shall limit the TC-traffic on the OBDH bus to the allocated value as given in IFDC
001.
MARS EXPRESS
IFDC-110:
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The Packet TC user shall collect the Memory Load Data and perform a consistency
check on each TC Packet Format.
In case of a TC packet format error (e.g. wrong length, wrong APID) or in case of
time-out the Packet user shall
1) reflect this event in its telemetry (TC verification packet, see SGICD service 1
2) suspend the TC processing for 16 sec (+10% / -0% tolerance)
3) flush the TC input buffer
4) acquire the next TC packet
Time-out shall be declared if a complete TC-Packet is not received within 2 sec
(+10% / -0% tolerance).
The TC packet can be transmitted in 1 to n non-contiguous MLC’s. That means the
DMS can interrupt the TC packet transfer for other DMS activities. (See figure 4.21).
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The Telecommand Packet Distribution is shown in principle in figure 4.2-1:
TCP 1
Last MLC
TCP 1
MLC 2
TCP 1
MLC 1
OBDH-Bus (I/B)
other DMS interrogations
TCP 1
Word 1
TCP 1
Word 2
TCP 1
Last Word
TCP 1
Last MLC
TCQueue
TCP 1
MLC 1
MLCs
RTU
TCP 2
Word 1
DMS-Computer
TCP 1
Word 1
TCP 1
Word 2
TC
Buffer
TCP 1
Last Word
TCP 2
Word 1
USER
Figure 4.2-1: Telecommand Packet Distribution
b) Non-Packet TC users (not applicable to payload instruments):
For non-packet users, serial digital telecommands are distributed by the DMS via the MLC
channels.
Note: TC packets from ground will be opened by the DMS computer and then the data
content is distributed to the user.
IFDC-115:
Serial digital telecommands shall be distributed from the RTU to the Non-Packet TC
user as MLC or as DML (see §3.2.5). commands
IFDC-120:
The Non-Packet TC user shall cope with the maximum repetition rate of the related
command type (MLC, DML).
IFDC-125:
If the allocation of the Non-Packet TC user (see req. IFDC-001) is exceeded, the
remaining TC shall be delayed to the next cycle.
MARS EXPRESS
4.3
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Discrete and SDT Telemetry Acquisition
The requirements defined in this chapter shall be considered as preliminary
requirements - based on Rosetta DMS software- as long as a DMS Software
Requirement Document (SRD) has not been issued for Mars Express.
The intention is to copy the Rosetta SRD but still some requirements or
parameters may need to be adapted to the specificity (mission, number of
instruments, new SSMM, etc.) of Mars Express.
4.3.1
Serial Digital Telemetry
Serial Digital Telemetry will be acquired on board Mars Express by the DMS-computer via
the RTU as TM-Blocks containing TM Source Packets. For some S/C units (e.g. PCU, PDU)
- but not for payload instruments - serial digital telemetry may also be acquired as nonpacketized data. Therefore the requirements for the acquisition protocol of serial data via
OBDH Bus and RTU are classified in the following categories depending on the user:
a) Packet TM user (TM Packet Terminal)
IFDC-201:
TM-Block
Size Information
The Source Packet Telemetry Acquisition shall be performed according to the
“Packet TM-Block Acquisition Protocol” as shown in figure 4.3-1:
1 x SD16
16 bit
TM-Block
Length “n”
n = number of following 16 bit TM data words
SD16
TM-Block
Data
16 bit
16 bit
16 bit
16 bit
SD16-1
SD16-2
SD16-3
SD16-n
n x SD16
Figure 4.3-1: Packet TM-Block Acquisition Protocol
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IFDC-202:
Definition: Polling of a Packet Terminal (PT) is understood as the acquisition of
the TM-Block defined in Fig. 4.3-1.
The DMS shall sequentially poll each Packet terminal (PT) according to a
predefined polling sequence modifiable by a dedicated telecommand with the
following constraints:
each PT shall be polled at least once per 8 sec.
each PT shall not be polled more than once per 1 sec
each PT shall be polled at the maximum rate possible within the above
constraints and within the maximum allocation for TM-Block acquisition
defined in IFDC-001. If this cannot be achieved an event packet shall be
generated by the DMS (SGICD service 5,3), the acquisition shall be continued
and the polling sequence shall be delayed.
the time between the end of acquisition of a TM-Block of a packet terminal
and the beginning of the next polling of the same Packet Terminal shall
always be greater than 125 (TBC) msec.
Exception to IFDC-001: In case where no data is available from any other
packet terminal to achieve the delay of 125 (TBC) msec, the OBDH bus
overhead may increase by 12% (TBC) the nominal overhead of IFDC-001.
IFDC-203:
After a positive poll (i.e. packets are available) the complete TM-Block shall be
acquired before the next packet terminal is polled.
IFDC-204:
The polling sequence shall be modifiable by a dedicated telecommand (SGICD
service 16) to allow polling from zero up to the maximum number of Packet
Terminals.
IFDC-205:
Depending on the OBDH Bus traffic, the block acquisition may be interrupted;
the time interval (start to start) between two consecutive 16 bit acquisitions can
vary in the range from 122 sec up to 1 sec.
IFDC-206:
The TM Packet Terminal shall be able to buffer its telemetry packets for a period
of 16 sec without loss of any data.
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IFDC-210:
The telemetry shall be collected in TM-Blocks consisting of a defined number of
16 bit words.
A TM-Block is either empty (i.e. no TM-Packet available) or it can contain 1 or
more complete TM Source Packets
The first word shall give the number “n” of the following 16bit words in the TMBlock (“TM-Block Length”).
For the Packet Terminal, the maximum allowed TM-Block length shall be 6144
words. The DMS shall be capable to acquire a maximum block size of 8191
words. (Note: in case a specific Packet Terminal shows a high average data rate,
on approval by the Prime the maximum allowed TM-Block length for this
dedicated Packet Terminal can be extended from 6144to the maximum of 8191 .
An empty TM-Block shall consist of only one 16bit word consisting of the TMBlock Size Information only, which shall be set to 0000h.
At Power-On or Reset the Packet Terminal shall set its telemetry output buffer to
zero (all bits=0) within 1 sec to allow the DMS to detect that no telemetry data is
available.
IFDC-215:
The DMS shall verify that the data is collected correctly by checking the validity
of the APIDs and the consistency of the length of each packet within the TMBlock.
If the DMS detects an error in the packet structure it shall:
1) issue an Event Packet (SGICD service 5, 4) containing Packet Terminal ID,
error location in the block where the error occurred, Data (TBD).
2) STOP acquisition of this Packet Terminal
3) Discard the complete TM-Block
4) Disable the acquisition of this particular source
IFDC-235:
The DMS shall not poll a packet terminal, which is powered off.
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b) Non-Packet SDT user (not applicable to payload)
IFDC-240:
The DMS shall acquire the nominal serial Telemetry of all Non-Packet TM users
at least every 4 sec
IFDC-245:
The acquisition of Non-Packet SDT (16bit) TM-Data shall be according figure
4.3-2
IFDC-247:
After reception of a Memory Load Command “TM Mode Request” the user shall
filled his buffer and the data shall be available for acquisition until the next “TM
Mode Request” Command is received.
DMS
DMS to request
and trigger
TM-Mode
DMS to acquire
TM-Data
DMS to generate TMPacket with time stamp
of DMS packet
elaboration time
Synch. Task
To be provided
Known Fixed Delay
Acquisition
Timeline
OBDH bus
Timeline
100ms
Known Fixed
Delay
DMS PF
delay time < 1 cycle
Variable Duration
(due to OBDH Bus
traffic)
ML Cmd for
TM Mode
Request
SDT (16bit) Seq.
for TM-Buffer
read-out
Fixed
Duration
max. 400ms
User
Timeline
Acquire TM
and fill
TM-Buffer;
Mark
TM- Buffer
as filled
Mark
TM-Buffer
as empty
Figure 4.3-2: Acquisition Protocol of Non-Packet SDT (16bit) TM-Data
Next DMS
trigger
(Period 1 to 4 s)
Synch. Task
MARS EXPRESS
4.3.2
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Discrete TM user (BLD, RSS, ANS, ANC, ANP)
IFDC-250:
The DMS shall acquire all discrete Telemetry at least every 4 sec.
IFDC-255:
The discrete TM shall be correlated to the same time-stamp as used for the serial
(SDT) telemetry.
IFDC-260:
It shall be possible to present in one TM-Packet the acquired discrete TM and
serial (SDT) telemetry (non-packet-TM) which is related to one S/S or unit.
MARS EXPRESS
4.4
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Timer Synchronisation
The Timer Synchronization shall be performed according to the “Timer
Synchronization Protocol” shown in figure 4.4-1:
IFDC-301:
BCP3 (Cyclic 8sec interval)
BCP3
OBDH timeline
DMS H/W:
latch S/C time
DMS S/W:
add 8sec to the
latched S/C time
TC Time Packet
Transfer (via MLCommands to User)
Experiment: decoding
and arming of timeset
Set experiment timer
with TC Packet time
TSY
TSY
RTU timeline
Margin for TC
packet generation
(6 sec, TBC)
Margin for
TC packet decoding
(0.5 sec, TBC)
Figure 4.4-1: Timer Synchronisation Protocol
MARS EXPRESS
IFDC-305:
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On-Board Time Distribution/Synchronization
The OBDH broadcast protocol shall make use of only one BCP signal with a period
of 8 seconds. The BCP-3 protocol shall be modified for this purpose.
The modified BCP-3 shall be derived cyclically from the OCXO and issued
into the OBDH interrogation protocol by the DMS computer.
On occurrence of the BCP-3 the SCET shall be read and stored by the DMS
computer.
When the time synchronization of an experiment is to be performed the DMS
SW shall
Add one BCP-3 interval (8 sec) to the stored SCET
Generate the TC time packet with the new calculated time within the
present BCP-3 time interval (8 sec) Sent to that experiment the TC packet with a margin of 0.5 s (TBC) wrt
to the rising edge of the TSY signal to allow the experiment to process
the TC time packet.
The rising (first) edge of the Timer Sync. Pulse (TSY) shall be used to set the
user internal timer to the on-board time transmitted within the TC time packet.
The structure of the Time packet is defined in the SGICD - MEX-ESC-IF-5001 appendix A2.9
(service 9)
IFDC-310:
Software Tasks:
- The TC time packet generation of the DMS must be synchronized with the
generation of the BCP-3 to provide a time margin of 0.5 sec (TBC) to the
experiment.
- The TC time packet generation shall have priority for distribution on the
OBDH bus.
- The TC time packet decoding within the experiment must be done with a
sufficient margin in order to be ready for the updating of the internal timer
at occurrence of the next BCP-3 pulse (TSY)
MARS EXPRESS
4.5
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High Rate Data Transmission
The requirements defined in this chapter shall be considered as preliminary
requirements - based on Rosetta DMS software- as long as a DMS Software Requirement Document (SRD) has not been
issued for Mars Express and
- as long as a baseline for the interface between the new (wrt to Rosetta)
SSMM and the IEEE users has not been defined and agreed.
4.5.1
High Rate Link Protocol
The Transmission Protocol of the High Rate Link includes the following layered structure,
derived from the IEEE 1355 Standard, as shown in figure 4.5.1-1.
Transaction Layer
Packet Layer
Exchange Layer
Character Layer
Signal Layer
Physical Media
Figure: 4.5.1-1: IEEE 1355 Protocol Layers (DS-Link)
The logical layers (signal to transaction layer) are defined as a protocol stack where each layer
defines representations (information formats) in terms of the immediately lower layer,
together with rules (protocols) for the exchange of these representations (character layer to
packet layer).
The interaction of the logical layers is described in the IEEE 1355-1995 Standard §4.3
(Interaction of layers).
Physical Media
The Physical Media defines the electrical properties of the transmission media (cable,
connector...). For MARS EXPRESS the definition is different to the IEEE 1355 standard.
MARS EXPRESS
IFDC-410:
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The physical media characteristics of the High Rate Interface shall be as specified in
paragraph 3.7 of this annex.
Signal Layer
The Signal Layer defines the electrical characteristics (levels, timing...) of the link. Onboard
the MARS EXPRESS S/C, different buffers will be used. Therefore the Signal Layer
definition is different to the IEEE Std 1355 for DS-Links.
IFDC-420:
The Signal Layer characteristics for the High Rate Interface shall be as specified in
§4 of this document.
Character Layer
Bits are transmitted as groups called ‘characters’. They represent the smallest usable unit of
information.
Characters are used by the higher layers of the protocol to transmit data or to control the
transmission of a continuous sequence of characters on the link.
The data and control character structure is defined in figure 4.5.1-1
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Data Characters
P 0 X X X X X X X X
0 1 2 3 4 5 6 7
LSB
Data-Control Flag
Parity Bit
MSB
LSB transmitted first
Control Characters
P 1 0 0
FCC
Flow Control Character
P 1 0 1
EOP_1 Normal End of Packet
P 1 1 0
EOP_2 Exceptional End of Packet
P 1 1 1
ESC
Escape
P 1 1 1 P 1 0 0
Data Character
NULL
EOP_1
FCC
P 0 X X X X X X X X P 1 0 1 P 1 0 0
Parity
Coverage
Parity
Coverage
Figure 4.5.1-1: IEEE-1355 Link Character Encoding and Parity Coverage
IFDC-430:
The Character Layer shall be according to the IEEE 1355-1995 Standard, § 5.6 (DSSE and DS-DE character level).
Exchange Layer
The exchange layer describes the procedure of the node-to-node exchange of characters (or
groups of characters) to ensure flow control and the proper start-up and functioning of the
link.
A general description of the exchange layer is given in the IEEE 1355-1995 Standard,
§4.2.3.2.
IFDC-440:
The Exchange Layer shall be according to para. 5.7 of the IEEE 1355-1995
Standard, (DS-SE and DS-DE exchange level) but with the link timing constraints
as defined in para. 3.7 of this document.
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IFDC-442:
A flow control mechanism for the exchange layer shall be implemented as defined
in the IEEE 1355-1995 Standard, para. 4.2.3.3 (Flow control).
The considerations about maximum line length are not applicable.
The flow control tokens used shall not be visible to the packet protocol.
IFDC-444:
After power-on the link data and strobe signals shall be low without clocks, i.e.
inactive. Following power-on reset, before starting the link, each high rate link
(IEEE1355) controller shall be initialized to the following default transfer bit rates
(link speed):
Following power-on reset, before starting the link, each high rate link (IEEE1355)
controller shall be initialised to the following default transfer bit rates:
- TBD MBit/s for data transfer from Payload Instrument to SSMM.
- TBD MBit/s for data transfer between SSMM and EGSE (TBC)
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Packet Layer
A general definition of a “1355-Packet” is given in IEEE1355-1995 Standard, para. 4.2.4.1.
IFDC-450:
A 1355-Packet shall consist of a “data area”, delimited by an “End-of-Packet”
marker.
The “data area” of a 1355 packet shall always consist of an even number of 16 bit
words delivered by the data transmitter, represented by “Data-characters”. On the
1355 link the byte-order of the 16 bit word shall be most significant byte (MSByte)
first, least significant byte (LSByte) last.
(see figure 4.5.1-4).
Note: According to IEEE1355, each byte will be transmitted “little endian”
(i.e. least significant bit LSB first, most significant bit MSB last).
In case of Science Data Transfer (para. 4.5.2) the 1355 packet shall consist of one
complete TM Source packet delimited by EOP1. (see fig. 4.5.1-2).
The first byte of a TM packet transmitted by the payload shall be the byte containing
the packet version number (ie. MSByte of the 'Packet Id' field).
In case of Plain File Transfer (para. 4.5.3) the 1355 packet shall consist of
- one complete plain file (e.g. image) delimited by EOP1 (see fig. 4.5.1-3a)
- or the plain file can be segmented into multiple 1355 packets, terminated by
EOP2 with the last 1355 packet of the plain file (end of file) always terminated
by EOP1. (see fig. 4.5.1-3b)
EOP1 is the “Normal-End-of-packet-character” (acc. IEEE1355 Std) while EOP2 is
the “Exceptional-End-of packet-character”.
The EOP marker shall not be stored at the receiver side with the data packet from
the source. It shall be filtered out by the high rate (1355) link controller (this implies
that a plain file send with intermediate EOP2 may be re-transmitted with different
EOP2 structure or without EOP2) (see figure 4.5.1-4).
IFDC-452:
The maximum length of a 1355 packet shall be
- in case of Science Data Transfer 4112 bytes (max. TM Source Packet)
- in case of Plain File Transfer 10 Mbytes (with or without EOP2).
IFDC-455:
The transmission of a 1355-Packet on a link shall be completed before transmission
of the successive 1355-Packet may begin.
The acknowledge of high rate packets transferred between Payload and SSMM by
automatically exchanging acknowledge packets on the high rate links is not
foreseen.
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Transaction Layer
Transactions are not defined in the IEEE 1355 Standard. For the data transfer between SSMM
and Payload Units, the transactions are defined in para. 4.5.2 and 4.5.3.
1355 pa cke t
1355 pa cke t
EO P 1
1355 pa cke t
EO P 1
1355 pa cke t
EO P 1
EO P 1
Figure 4.5.1-2: Science Data Transfer - 1355 packet(s)
a)
1355 pa cke t
EO P 1
com p el te f iel
b)
1355 pa cke t
1355 pa cke t
EO P 2
1355 pa cke t
EO P 2
1355 pa cke t
EO P 2
EO P 1
com p el te f iel
Figure 4.5.1-3: Plain File Transfer - 1355 packet(s)
The transfer of a data packet on the High Rate (IEEE1355) link is shown in principle in figure
4.5.1-4:
MARS EXPRESS
Receiver Buffer
Word 0
B0
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Transmitter Buffer
B0: Most Significant Bit (MSB)
B15: Least Significant Bit (LSB)
Word 0
Start
Address
B0
B15
B15
Word n
B0
MSB
Start
Address
B15
Word 1
Word 1
B0
MEX-MMT-SP-0007
TMSource
Packet
End
Address
B15
LSB
1355 Link
Controller
remove EOP and
Flow Control Tokens
B0
B15
1355 - Packet Level
Word 0
Word 1
MSByte LSByte MSByte LSByte
B7-B0 B15-B8 B7-B0 B15-B8
DataChar.
DataChar.
DataChar.
DataChar.
P0B7-B0 P0B15-B8 P0B7-B0 P0B15-B8
P0: Parity Bit + Control Bit (zero)
Word n
Word n
MSByte LSByte
B7-B0 B15-B8
DataChar.
DataChar.
B0
MSB
EOP
P0B7-B0 P0B15-B8
(Flow Control Tokens not shown)
TMSource
Packet
End
Address
B15
LSB
1355 Link
Controller
add EOP and
Flow Control Tokens
Figure 4.5.1-4: High Rate Data Transfer on 1355-Packet Level
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High Rate Link General Procedures
IFDC-460:
The Payload Users shall provide the capability for the following Telecommands
send via the RTU Memory Load Command Channels:
1. Reset SMCS (HS-link to SSMM)
Service 255, Subtype 2 (TBC)
2. Start (Establish) HS-link to SSMM
Service 255, Subtype 3 (TBC)
3. Reset SMCS & Start HS Link to SSMM
Service 255, Subtype 4 (TBC)
IFDC-462:
The Start-up of the High Rate Link between Payload Users and SSMM shall be
performed according to the “High Rate Link Start-up Procedure” as shown in figure
4.5.1-5.
SSMM
PAYLOAD USER
SSMM power on
-reset signal inactive (SMCS)
- initialise (SMCS)
- SMCS in "Ready" state
(No NULL tokens sent)
wait for NULL tokens
RTU-PL power on
Configure 1355cross-strapping
Connect SSMM link MUX
to inactive PL-link (N or R)
Wait time for
Payload Ready
(TBD by Payload)
Payload power on
(or SMCS reset)
- reset signal inactive (SMCS)
-initialise (SMCS)
- SMCS in "Ready" state
(no NULL tokens sent)
Connect SSMM link MUX
to active PL-link (N or R)
send NULL
NULL tokens received
DMS internal command:
start link
DMS command: start link
Service 255,Subtype 3 (TBC)
send FCC and NULL
send FCC and NULL
NULL tokens received
link established
link established
link running
link running
Figure 4.5.1-5: High Rate Link Start-up Procedure
MARS EXPRESS
IFDC-465:
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In case of failures on the High Rate Link (Disconnect error, Parity error) between
Payload Users and SSMM the “High Rate Link Failure Procedure” as shown in
figure 4.5.1-6 shall be performed.
SSMM
PAYLOAD USER
link running
link running
parity error detected:
halt outputs
disconnect error:
go silent
disconnect error
go silent
exchangeof-silenceprotocol
exchangeof-silenceprotocol
Ready
Ready
Event packet to DMS
send NULL
NULL tokens received
DMS internal command:
start link
DMS command: start link
Service 255,Subtype 3 (TBC)
send FCC and NULL
send FCC and NULL
NULL tokens received
link established
link established
link running
link running
Figure 4.5.1-6: High Rate Link Failure Procedure (Disconnect Error, Parity Error)”
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SSMM Reconfiguration
IFDC-467:
In case of SSMM Reconfiguration, i.e. switch-over between nominal and redundant
interfaces, the “High Rate Link SSMM Reconfiguration Procedure” as shown in
figure 4.5.1-7 shall be performed.
Alternatively a Reset-Command will be applied to the Payload Users after SSMM
reconfiguration (reset of Payload User SMCS).
MARS EXPRESS
RTU-PL
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SSMM
MEX-MMT-SP-0007
PAYLOAD USER
Procedure Fig. 3.7.5.2-1d
or
Procedure Fig. 3.7.5.3-1d
or
Procedure Fig. 3.7.5.3-2c
link running
Connect RTU Mux
to inactive SSMMController (N or R)
disconnect error
go silent
Power-off active
SSMM Controller
(N or R)
wait for SSMMController power-off
Connect RTU Mux
to powered-off SSMMController (N or R)
Power-on the other
SSMM Controller
(N or R)
wait for SSMMController power-on
Connect RTU Mux
to active SSMMController (N or R)
Ready
Ready
send NULL
NULL tokens
received;
DMS internal
command: start link
DMS command:
start link
Service 255,
Subtype 3 (TBC)
send FCC and NULL
send FCC and NULL
NULL tokens
received;
link established
link established
link running
link running
Figure 4.5.1-7: High Rate Link SSMM Reconfiguration Procedure”
MARS EXPRESS
4.5.2
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High Rate Science Data Acquisition
High Rate Science Data from the Payload Users will be acquired on board the Mars Express
spacecraft under control of the DMS-computer directly by the SSMM via the High Rate
Interface as “1355-Packets” each containing one complete TM Source Packet.
IFDC-470:
The High Rate Science Data Acquisition from the Payload Users to the SSMM shall
be performed according to the “High Rate Science Data Acquisition Protocol” as
shown in figure 4.5.2-1a.
The data transfer on the high rate link itself shall be according to the “High Rate
Link Protocol” (see para 4.5.1)
IFDC-472:
The High Rate Science Data shall be collected in 1355-Packets each containing one
complete TM-Source Packet as defined in IFDC-450 “Science Data Transfer” and
IFDC-452 (para. 4.5.1).
IFDC-474:
The High Rate Science Data shall be stored in a file of type “packet store”, which
shall be handled as any other TM-packet store in the SSMM for the later
transmission to ground.
IFDC-476:
The DMS shall have the overall control of the data transfer from the High Rate
Instruments (Payload) to the SSMM.
The control of the High Rate Instruments by the DMS shall be by the TM/TC
protocol via the RTU interface using the corresponding packet services, defined in
the Mars Express Space/Ground ICD.
IFDC-478:
The Telemetry Source Packet shipped via the High Rate Link shall consist of an
even number of 16 bit words with a maximum length of 4112 bytes.
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Link Start-up Procedure
(Fig.3.7.5.1-5)
Link established
Packet
Store
created/
open?
Y
N
Normal Protocol:
Create Packet Storage
(Fig.3.7.5.2-1b)
Normal Protocol:
Enable / Transmit
(Fig.3.7.5.2-1c)
normal
failure
Normal
Protocol:
Transfer
termination
by DMS
Normal
Protocol:
Transfer
termination
by P/L User
Failure Case
Protocol:
Packet
Boundary
reached
IEEE1355
Link Error:
Link
Failure
Procedure
(Fig.3.7.5.2-1d)
(Fig.3.7.5.2-1e)
(Fig.3.7.5.2-1f)
(Fig.3.7.5.1-6)
Figure 4.5.2-1a: High Rate Science Data Acquisition Protocol
General Protocol Structure
MARS EXPRESS
DMS => SSMM
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Create Packet Store “filename” of size “X” bytes
including file margin size “P” bytes
Via
Internal Link
Figure 4.5.2-1b: High Rate Science Data Acquisition Protocol
Normal Protocol: “Create Packet Storage”
DMS => SSMM
Initialise/Append transfer from User “Y” for
“filename”
Via
Internal Link
DMS => USER
Enable Science Data Transmission
(on High Rate Link to SSMM)
Packet Service 20, Subtype 10
Via
Normal Link
USER => SSMM
Science Data Transmission
(Transfer of TM Source Packets
via “High Rate Link Protocol (see para 4.5.1))
Packet Service 20, Subtype 13
Via
High Rate Link
Figure 4.5.2-1c: High Rate Science Data Acquisition Protocol
Normal Protocol “Enable/Transmit”
DMS => USER
Disable Science Data Transmission
(on High Rate Link to SSMM at next packet boundary)
(Packet Service 20, Subtype 11)
Via
Normal Link
USER => DMS
TC Verification Packet
(Acceptance and Execution Report)
(Packet Service 1, Subtype 1 or 2 and 7 or 8)
Via
Normal Link
DMS => SSMM:
Stop transfer (link remains established/running)
Via Normal Link
Figure 4.5.2-1d: High Rate Science Data Acquisition Protocol
Normal Protocol “Transfer termination by DMS”
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USER => DMS
Event Packet from User
“Science Data Transmission Stopped
(at a packet boundary)”
(Packet Service 5, Subtype 3 or 4)
Possible action (can also be within an OBCP)
Via
Normal Link
DMS => SSMM:
Stop transfer (link remains established/running)
Via Normal Link
Figure 4.5.2-1e: High Rate Science Data Acquisition Protocol
Normal Protocol “Transfer termination by Payload User”
SSMM => DMS
Event packet from SSMM:
Packet Store “filename” reached “X-P” bytes
Via
Internal Link
Perform Event Recovery Action,
e.g. OBCP for “Transfer termination by DMS”
(ref. To Fig. 4.5.2-1d)
Figure 4.5.2-1f: High Rate Science Data Acquisition Protocol
Failure Case Protocol “Packet Store Boundary Reached”
Note:
DMS:
USER:
Normal Link:
Internal Link:
DMS-Computer
High Rate Instruments (Payload)
TC/TM via OBDH-Bus/RTU and MLC/SDT;
Avionics Subsystem Internal interface
MARS EXPRESS
4.5.3
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High Rate Plain File Transfer
High Rate Plain Files from the Payload Users will be dumped/retrieved on board the Mars
Express spacecraft under control of the DMS-computer directly to/from the SSMM via the
High Rate Interface as “1355-Packets”.
IFDC-480:
The High Rate Plain Files shall organised in 1355 packet(s), each containing a even
number of 16 bit words.
IFDC-482:
The High Rate Plain File shall be collected as 1355-Packet(s) as defined in IFDC450 “Plain File Transfer” and IFDC-452 (para. 4.5.1).
IFDC-484:
The High Rate Plain File shall be stored in a file of type “plain file” in the SSMM.
Only complete plain files will be replayed.
IFDC-486:
The DMS shall have the overall control of the data transfer between the High Rate
Instruments (Payload) and the SSMM.
The control of the High Rate Instruments by the DMS shall be by the TM/TC
protocol via the RTU interface using the corresponding packet services, defined in
the Mars Express Space/Ground ICD.
IFDC-487:
The Plain File shipped via the High Rate Link shall consist of a even number of 16
bit words with a maximum length of 10 Mbytes.
IFDC-488:
Data transmission from the Payload User to the SSMM shall not occur in parallel to
data retrieval from SSMM to the same Payload User.
MARS EXPRESS
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Plain File Transfer from Payload User to SSMM
IFDC-490:
The High Rate Plain File Transfer from the Payload Users to the SSMM shall be
performed according to the “High Rate Protocol - Plain File Transfer to SSMM” as
shown in figure 4.5.3-1a.
The data transfer on the high rate link itself shall be according to the “High Rate
Link Protocol” (see para 4.5.1)
Link Start-up Procedure
(Fig.3.7.5.1-5)
Link established
Normal Protocol:
Create Plain File
(Fig.3.7.5.3-1b)
Normal Protocol:
Enable / Transmit
(Fig.3.7.5.3-1c)
normal
failure
Normal
Protocol:
Transfer
termination
by EOP1
received
Failure Case
Protocol:
Plain File
Boundary
reached
IEEE1355
Link Error:
Link
Failure
Procedure
(Fig.3.7.5.3-1d)
(Fig.3.7.5.3-1e)
(Fig.3.7.5.1-6)
Figure 4.5.3-1a: High Rate Protocol - Plain File Transfer to SSMM
General Protocol Structure
MARS EXPRESS
DMS => SSMM
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Create Plain File “filename” of size “X” bytes
including file margin size “P” bytes
MEX-MMT-SP-0007
Via
Internal Link
Figure 4.5.3-1b: High Rate Protocol - Plain File Transfer to SSMM
Normal Protocol: “Create Plain File”
DMS => SSMM
Initialise transfer from User “Y” for “filename”
Via
Internal Link
DMS => USER
Enable Plain File Transmission to SSMM,
Plain File “filename” of size “X” bytes
(on High Rate Link)
(Packet Service 20, Subtype 20)
Via
Normal Link
USER => SSMM
Plain File Transmission
Via
(Complete Plain File via “High Rate Link Protocol (see High Rate Link
para 4.5.1))
Figure 4.5.3-1c: High Rate Protocol - Plain File Transfer to SSMM
Normal Protocol: “Enable/Transmit”
DMS => USER
Disable Plain File Transmission
(on High Rate Link)
(Packet Service 20, Subtype 21)
Via
Normal Link
USER => DMS
TC Verification Packet
(Acceptance and Execution Report)
(Packet Service 1, Subtype 1 or 2 and 7 or 8)
Via
Normal Link
DMS => SSMM
Stop transfer (link remains established/running)
Close Plain File “filename”
Via
Internal Link
Figure 4.5.3-1d: High Rate Protocol - Plain File Transfer to SSMM
Normal Protocol: “Transfer termination by EOP1 received”
MARS EXPRESS
SSMM => DMS
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Event packet from SSMM:
Plain File “filename” reached “X” bytes
MEX-MMT-SP-0007
Via
Internal Link
Perform Event Recovery Action,
e.g. OBCP for “Transfer termination by EOP1
received” (ref. To Fig. 4.5.3-1d)
Figure 4.5.3-1e: High Rate Protocol - Plain File Transfer to SSMM
Failure Case Protocol “Plain File Boundary Reached”
Note:
DMS:
USER:
Normal Link:
Internal Link:
DMS-Computer
High Rate Instruments (Payload)
TC/TM via OBDH-Bus/RTU and MLC/SDT;
Avionics Subsystem Internal interface
