Download Delay Models

EE M216A .:. Fall 2011
Lecture 3
Delay Models
Alireza Tarighat ([email protected])
•
•
Slides are Courtesy of Prof. Dejan Marković.
Some slides adapted from “Digital Integrated Circuits; J. M.
Rabaey, et al”. Copyright 2003 Prentice Hall/Pearson.
Gate Delay
 Gate delay is a measure of time between an input transition and
an output transition
– May have different delays for different input to output paths
Inputs
Outputs
Logic Gates
– Different for an upward or downward transition
● tpLH – propagation delay from LOW-to-HIGH (of the output)
 A transition is defined as the time at which a signal crosses a
logical threshold voltage
– Digital abstraction for 1 and 0
– Often use VDD/2
EEM216A .:. Fall 2011
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Static CMOS Gate Delay
 Output of a gate drives the inputs to other gates (and wires)
– Only pull-up or pull-down, not both
– Capacitive loads
in
in
out
out
VM
tpHL
CLOAD
 The delay of EACH stage is treated separately
in
tPD1
tPD2
out
tPD = tPD1 + tPD2
 Transition moment is defined at VM (logical threshold)
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Voltage Transfer Characteristics (VTC)
 Characterize the DC response of
a simple inverter
in
 5 Regions of operation
– Vin<VTN, Vout=VDD,
WP/LP
out
WN/LN
● N-Off, P-Lin
– Vin>VTN, Vout>Vin - VTP
● N-Sat, P-Lin
– Vin>VTN, Vin-VTP>Vout>Vin-VTN
● N-Sat, P-Sat
– Vin<VDD+VTP, Vin-VTN>Vout
● N-Lin, P-Sat
– Vin> VDD+VTP, Vout=VGND,
● N-Lin, P-Off
 Logical threshold
– When Vin = Vout
P:Lin
N:Sat
Vout
P:Lin
N:Off
VM
P:Sat
N:Sat
P:Sat
P:Off
N:Lin
N:Lin
Vin
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Logical Threshold Voltage
 Set IDSATP = IDSATN and solve
– Dependence on P:N sizing
and mobility ratio
– Slight dependence on VTP/N
in2
WP/LP
out
WN/LN
in
WP2
in1
– Depends on which input
the gate is driving
out
in2
 Not so easy if not an inverter
WP1
WN2
in1 WN1
Vout
VM
● In1 to Out transfer
characteristic can be
different from In2 to Out
– Use VDD/2 as average case
● Unless severely skew the
P:N ratio
Vin
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Calculating VM
VDSATp 

V


0
kn VDSATn  VM  VTn  DSATn   k p VDSATp  VM  VDD  VTp 
2 
2 


VDSATp 

V



VTn  DSATn   r  VDD  VTp 
2 
2 


VM 
1 r
1.8
1.7
1.6
1.5
r
k p VDSATp
kn VDSATn

 satp W p
 satn Wn
1.3
M
V (V)
1.4
1.2
High VDD:
Long L or low VDD:
1.1
1
0.9
0.8
0
1
10
10
Wp/Wn
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Sensitivity of VTC to P:N
 Fortunately, the logical threshold is not very sensitive to P:N
ratio
– Ranges from 1.35V to 1.75V (for a 3.3-V VDD)
– VDD/2 is quite reasonable
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Delay Definitions
tp 
t pLH  t pHL
2
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Propagation Delay: RC Model
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
1
Ron
VDD
0.5
0.36
Vin = V DD
t
RonCL
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Calculating the Resistance
 Because of the non-linearity, the resistance is an “effective”
resistance that is averaged
– RON = VDS/IDSLIN ~ 1/bVGT
● Clearly too small
– Average different regions of operation
● Let R be the large signal resistance, R(VDS=VDS0) = VDS0 / IDS(VDS = VDS0)
● Ravg = 0.5 (R(VDS=VDD/2) + R(VDS=VDD))
● For velocity saturated device, Ravg = 0.5 (VDD/2IDSAT + VDD/IDSAT)
● A rough approx. for Rpull down that is better than just using VDD/IDSAT
– Input transition dependent
● Input may not be a perfect step
● Fortunately, not a very strong function of input rise time
 Ideal “estimate” is really through a simulator like SPICE
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Effective R for Velocity-Saturated Device (TwoPoints)
VGS ≥ VT
S
ID
Ron
D
VGS = VDD
Rmid
R0
VDS
VDD /2
VDD
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Effective R for Velocity-Saturated Device
(Integrated)
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Delay as a Function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
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Delay vs. Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
2
4
6
8
S
10
12
14
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Calculating the Capacitance
 Like R, MOS capacitances are voltage-dependent
 There are many capacitance
models, here’s a common one:
G
G
CGS
CGD
D
S
S
D
CGB
CSB
This model is too detailed
for circuit designers…
CDB
B
B
 For delay analysis, we linearize gate and diffusion caps
– Gate capacitance
● #1: Gate-Channel Capacitance
● #2: Gate Overlap Capacitance
– #3: Junction/Diffusion Capacitance
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Gate Capacitance
 Gate Channel Capacitance = C_gb + C_gs + C_gd
G
G
CGC
S
G
CGC
D
S
CGC
D
S
D
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Diffusion Capacitance
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MOS Capacitances (Summary)
 Gate-Channel Capacitance
– CGC = Cox·W·Leff
– CGC = (2/3)·Cox·W·Leff
(Off, Linear)
(Saturation)
Cgate
 Gate Overlap Capacitance
– CGSO = CGDO = CO·W
Circuit design
(Always)
 Junction/Diffusion Capacitance
– Cdiff = Cj·LS·W + Cjsw·(2LS + W)
 Typically g = Cpar / Cgate < 1
− 90nm GPDK: g = 0.61
(Always)
Cparasitic
 Simple linear models
− Designers typically use
C / unit width (fF/mm)
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Input Slope
 We can model the delay as tp = 0.69RC
– When driving w/ non-step in, the rise/fall time is absorbed in R
– R is different than the one extracted from I-V
 The output delay is linearly depended on input rise/fall time:
tp = 0.69RC + ηts
– η is the slope factor (typical values: 0.1 – 0.2)
– The model is limited to a range of fanouts
 More accurate delay models propagate two quantities:
delay and signal slope
– Both can be modeled as linear or table lookups (std-cell libs)
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Example: RC Gate Delay (Discard Internal Load)
 NAND gate driving an Inverter
 Assume the following, RN_DN = 3kW-mm, RP_UP = 7.5kW-mm,
CGN = CGP=2fF/mm.
– RDRVN = 1.5k, RDRVP = 2.5k
– CLOAD = 36fF
– tNANDpull_up = 90ps, tNANDpull_dn = 108ps
in2
in1
3mm
3mm
out
in2
2mm
in1
2mm
Pull-Up
Pull-Down
12mm
out
6mm
RDRVN
RDRVN
CLoad
RDRVP
out
CLoad
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Self-Loading Capacitance
 The previous calc. did not account for all the capacitances


– Diffusion capacitances (depend on the layout and sharing)
For hand calculation, we use a single number to represent all
capacitance associated with Source/Drain
– Area/Perimeter/Gate overlap etc.
– CDN=1.5fF/mm, CDP=2fF/mm
Pull-Up
– Possible for different numbers for N and P
RDRVP
Model is now RC network and depends on input
– In1 switching
Pull-Down
out
out
RDRVN
CN
CLoad
CLoad
RDRVN
CN
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Elmore Delay for RC Network
Example A
Example B
 RC network (N nodes)
N
tdelay(i ,m )   Ri ,k Ck
k 1
Delay from node i to node m
Ri,k = path resistance (i to k) shared
with the path between i and m
 Example A: tElmore = tDELAY (x-CL) = RXCX + (RX+RL)CL

– Longer RC chains result in superlinear increase in delay
Example B: tElmore = tDELAY (in-O2) =
R1*(C1+C2+C3)+(R1+R4)C4+(R1+R4 +R5)C5+(R1+R4 +R5+R6)C6
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NAND Example: Find the Capacitances
 First, calculate the capacitance
 Assume
– CLOAD = Cinv + Cself = 51fF
−
−
−
−
● Cinv = 2fF*(12+6) = 36fF
● Cself = 3*2fF + 3*2fF + 2*1.5fF = 15fF
– CN = 2*1.5fF + 2*1.5fF = 6fF
in1
in2
3mm
CN
CDN = 1.5 fF/mm
CDP = 2 fF/mm
CGN = 2 fF/mm
CGP = 2 fF/mm
3mm
out
in2
2mm
in1
CLOAD
2mm
12mm
6mm
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NAND Example: Delay
 In1-to-out delay
– tpull_down = 1.5k*6f + 3k*51f = 162ps
– tpull_up = 2.5k*(51f) = 127.5ps
out
RDRVN
Vo=VDD-VTN
CN
RDRVP
CLoad
RDRVN
Pull-Down
Pull-Up
out
CLoad
out
 In2-to-out delay
– tpull_down = 3k*51f =153ps
(CN predischarged)
– tpull_up = 2.5k(51f) = 127.5ps
RDRVN
CLoad
Vo=0
CN
Pull-Down
RDRVN
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Breaking Down Delay
 It is useful to break delay into 2 parts
– Delay due to self-loading
● Blue and red capacitances
– Delay due to gate loading
in1
in2
● Green capacitances
3mm
 Write delay as 2 parts as well
– Pull up
● RDRVP = 2.5k*(6/5) = 3K
● tdelay = RDRVPCSELF + RDRVPCGLOAD
CN
3mm
out
in2
2mm
in1
CLOAD
2mm
12mm
6mm
– 3K*15fF + 3K*36fF
– Pull down (in1)
● RDRVN = 1.5k
● tdelay = RDRVN (CN+2*CSELF) + 2RDRVNCGLOAD
– 1.5K*(6fF+2*15fF) + 1.5K*2*36fF
● Note the high self-loading delay
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Mixing Static CMOS & Transmission Gates
 Transmission gate switch logic can be made to satisfy gate



abstraction
Use static CMOS gates outputs to drive a transmission gate
switch network (conducting inputs)
Output of network drives a static CMOS gate
Example: a 2:1 Mux
selA
selAb
inA
Out1
Out
inB
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Transmission Gate Delay Example
 Delay depends on the gate that drives the switch
 Example
– Assume that only 1 path is selected
– The path is pulling up
– Delay of entire gate would be tDELAY1 + tDELAY2
● Focus on tDELAY1
tDELAY1
RDRVP(3mm)
tDELAY2
RTGP(2mm)
P:3mm
RTGN((2mm) Out1
RDRVN(1mm)
RTGP(2mm)
CINV
Out
N:1mm
CLOAD
RTGN((2mm)
Inverter
Transmission Gate
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Calculate the Capacitances
 Assume


– CDN = CDP= 1.5fF/mm, CGN = CGP= 2fF/mm
CINV = (diffusion) = (3u+2u)*1.5f + (1u+2u)*1.5f = 12f
CLOAD = (2*2u)*1.5f + (2*2u)*1.5f + (3u+1u)*2f = 20f
selA
3mm
selAb
2mm
inA
Cinv
1mm
inB
2mm
3mm
Out
Out1
2mm
2mm
1mm
CLOAD
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Example: Transmission Gate Delay
 Assume


– RN_DN=3kW-mm, RN_UP=6kW-mm,
RP_UP=7.5kW-mm, RP_DN=15kW-mm
RDRVP = 7.5k/3, RTGP = 7.5k/2 = 3.75k, RTGN = 6k/2 = 3k
tDELAY1 = 2.5k*12f + (2.5k+3.75k||3k)*20f = 113ps
2.5k
3.75k
3k
Out1
12f
Inverter
20f
Transmission Gate
Note: these are “equivalent” capacitances…
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Distributed RC Line
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Distributed RC Line
Assume: Wire modeled by N equal-length segments
For large values of N:
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Simulation-Based Parameter Extraction
 Typical simulation model
– This is a very basic model (with realistic input + load)
– Adjust the model depending on what you are trying to model
Previous
logic stage
Input
slope
Gate under
test
Next logic
stage
Output
load
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The “Flow”
 Hand design
–
–
–
–
–
Simple RC models provide intuition about circuits
Tradeoff analysis
Dominant effects
Reasonable starting point in the design process
For more information, run simulations and refine the model
 Simulate your design
– If the simulation results are way off, there is a bug somewhere
(check schematics, simulation files, your models)
– Don’t forget the corners
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Process Variations
 Not all devices (primarily
 Process variation causes
transistors to have different VT
and mobility, speeding up or
slowing down the devices
– Doping conc. (mobility)
– W/L sizing
– Oxide thickness
Fast
PMOS
transistors) are created equal
– Even if they nominally have
the same exact drawing
– Two on the same die can
differ, not to say different
wafers
Slow
Slow
NMOS
Fast
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More Corners (PVT Variation)
Process
Voltage
Temperature
cache
PMOS
Supply voltage (V)
Fast
Slow
70C
Temp
(oC)
Vmax: reliability & power
core
120C
Vmin: frequency
Slow
NMOS
Fast
 Typically, given corner parameters
Temperature
Time (usec)
Tmax: frequency & power
for devices
− Characterize effective parameters
across corners
Throttle
Time (usec)
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Delay and Transition Time
 Since the delay of a gate is approximated as RC elements, the
transition time is proportional to the same RC
 Transition (rise / fall) time is defined as time for a transition to
travel 10%-90% (20%-80% is also commonly used)
– Using ideal RC, the 10-90% is roughly 2.2RC
 For a gate (inverter) driving another gate,
– Transition time is roughly 2tDELAY
– Valid only for RC network
● Inductive network would propagate a much sharper transition
 Useful for modeling noise coupling
– Aggressor transition time determines injected noise
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Multi-Stage Gate Delay
 Static CMOS gates allows us to breakdown the total delay to be
the sum of each stage
ttotal   t n
– The R of the gate
– The C of the subsequent gate(s)
n
td5
td3
td1
in
Gate3
Gate1
td4
Gate5
out
Gate4
Gate2
Gate6
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Fan-In and Fan-Out
 Some commonly used terminology for gates

– Many definitions – some are more useful than others
Fan-In
– The number of inputs
– An indication of the input load that the gate presents to a
predecessor gate
● Because the series stack is roughly the number of inputs
● Later we will use Logical Effort to embed this concept
 Fan-Out
– The number of gates driven by the gate
– An indication of the loading of a gate (gate type dependent)
– Useful to normalize the loading to the gate capacitance of an
inverter with equal drive strength as the gate
● FO = CLOAD/CINV, where CINV = CO’(WP+WN) and RINV = RPULL_UP/DN
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Another Metric: FO4 Inverter Delay
 Measures quality of design across different technology
generations
d
Cadence 90nm technology:
FO4 = 33ps
Ring Osc Stage = 13ps
Reference:
Tutorial 2 (from 115C)
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