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ISSCC 2014 / SESSION 12 / SENSORS, MEMS, AND DISPLAYS / 12.8
12.8
A BJT-Based CMOS Temperature Sensor
with a 3.6pJ·K2-Resolution FoM
Ali Heidary1,2,3, Guijie Wang1,2, Kofi Makinwa2, Gerard Meijer1,2,4
Smartec, Breda, The Netherlands,
Delft University of Technology, Delft, The Netherlands,
3
Guilan University, Rasht, Iran,
4
SensArt, Delft, The Netherlands
1
2
This paper presents a precision BJT-based temperature sensor implemented in
standard CMOS. Its interface electronics consists of a continuous-time dutycycle modulator [1], whose output can be easily interfaced to a microcontroller,
rather than the discrete-time ΔΣ modulators of most previous work [2-4]. This
approach leads to high resolution (3mK in a 2.2ms measurement time) and high
energy efficiency, as expressed by a resolution FoM of 3.6pJK2, which is a 3×
improvement on the state of the art [4,5]. By employing chopping, dynamic
element matching and a single room temperature trim, the sensor also achieves
a spread of less than ±0.15°C (3σ) from -45 to 130°C.
The sensor’s basic operating principle is illustrated in Fig. 12.8.1. Under the
control of a Schmitt trigger (ST), a capacitor C is alternately charged by a current
I1 that is proportional-to-absolute-temperature (PTAT) and discharged by a
current I2 that is complementary-to-absolute-temperature (CTAT). The dutycycle D of the resulting oscillation is then given by I1/(I1+I2). To first order, this
is independent of the exact value of the ST’s threshold voltages. D is a linear
function of temperature if Iref= I1+I2 is temperature independent. In a CMOS
process, I2 can be derived from the base-emitter voltage VBE of a substrate PNP,
while I1 can be derived from the difference between the base-emitter voltages
ΔVBE of two appropriately biased PNPs. As shown in Fig. 12.8.1, D then varies
by about 30% over the desired temperature range: -45 to 130°C.
Figure 12.8.2 shows a simplified block diagram of the actual sensor. Substrate
PNPs Q1 and Q2 are biased at a 1:9 current density ratio, and an opamp (OP1)
forces the resulting voltage ΔVBE =VTln(9) across a resistor RPTAT to generate a
PTAT current IPTAT=ΔVBE/RPTAT (0.8μA at room temperature). Similarly, OP2 and
another resistor RBE convert the base-emitter voltage VBE3 of Q3 into a CTAT
current ICTAT=VBE3/RBE. These currents are then linearly combined such that the
capacitor C is charged by a current 3IPTAT-0.5ICTAT and is discharged by a current
ICTAT-IPTAT. To ensure accuracy over a wide supply range, all the associated
current mirrors/sources are cascoded. As in [3], the sum of the charging and
discharging currents, i.e., 2IPTAT+0.5ICTAT, is designed to have a slightly positive
temperature coefficient, which effectively compensates for the curvature in VBE3.
As shown in Fig. 12.8.1, this scheme ensures that D now varies from about 10%
to 90% over the desired temperature range [1].
An important source of error is the PTAT spread of VBE3 [1]. This can be
corrected by trimming the bias current and emitter area of Q3. The total trimming
range is about 10°C, with a worst-case step of about 50mK. Another source of
error is device mismatch, which causes the ratios between the various charging
and discharging currents to spread. The ratio RBE/RPTAT is set by using large
devices (RBE ~200kΩ) and careful layout, while the effect of opamp offset (and
1/f noise) is mitigated by chopping. Errors in the various current-mirror and
resistor ratios, as well as in the emitter area ratio of the substrate PNPs are
mitigated by DEM. Since the DEM switches around Q1 and Q2 carry their bias
currents, and so drop some voltage, Kelvin connections are used to accurately
sense ΔVBE [4]. The DEM and chopping state machines are self-clocked (by the
Schmitt trigger), and so no external clock is required. A full DEM and chopping
cycle corresponds to 8 oscillator periods.
The finite gain of OP1 and OP2 also causes errors in IPTAT and ICTAT, respectively.
In order to keep the resulting temperature-sensing errors below 50mK, the gains
of OP1 and OP2, must be greater than 90dB and 70dB, respectively. Moreover,
they must be able to handle input voltages (VBE) down to about 0.3V at 130°C.
Both requirements are met by implementing OP1 and OP2 as folded-cascode
amplifiers with PMOS input pairs, which draw 20μA and 7μA, respectively.
As shown in Fig. 12.8.3, the ST is based on two inverters in series with a positive
feedback path that controls the threshold voltages of the first one. When the ST’s
output is HIGH, M1 is bypassed by M6, and so its lower threshold (V1 in Fig.
12.8.1) is set by the threshold voltage of M2, i.e., VTH2. When its output is LOW,
M4 is bypassed by M5, and so its upper threshold voltage (V2 in Fig. 12.8.1) is
close to VDD-|VTH3|. The amount of positive feedback is determined by the relative
W/L ratios of M2,3 and M1,4. The large swing (~ VDD – 2V) at the ST’s input
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• 2014 IEEE International Solid-State Circuits Conference
ensures that its input-referred noise has negligible impact on the resulting dutycycle. Making C large (150pF), makes the oscillation frequency low enough (less
than 4kHz) to ensure that the error caused by the ST’s own switching time (a few
nanoseconds) is less than 50mK.
Only 8 cycles of the sensor’s duty-cycle-modulated output are necessary for an
accurate temperature measurement. As a result, the sensor is faster, and thus
more energy-efficient, than sensors based on discrete-time ΔΣ modulators,
which typically require hundreds of clock cycles to achieve the same thermalnoise-limited resolution [2-4]. Although accurately digitizing a duty-cycled signal
requires a counter driven by a high frequency clock, this can be done in a microcontroller or FPGA realized in nanometer CMOS, thus making the associated
power and area overhead negligible.
The sensor occupies 0.8mm2 and was implemented in a 0.7μm CMOS process.
It operates from supply voltages ranging from 2.9 to 5.5V, and draws 55μA at
3.3V. The sensor outputs a rail-to-rail square-wave, whose frequency varies
from about 0.5 to 4kHz over temperature and supply voltage. These outputs
were buffered and applied to an FPGA which digitized the high- and low-time
intervals, tH and tL, with the help of an internally generated 100MHz sampling
clock. The requirements on this clock are quite relaxed, since the sensor’s jitter
is in the order of a few tens of nanoseconds. To achieve an accurate result, 8
periods must be averaged, i.e. Davg1=Σ(tH/(tH +tL))/8. A simpler approach,
analogous to low-pass filtering the sensor’s output, involves summing the
various periods over 8 cycles, i.e. Davg2=ΣtH/Σ(tH + tL). However, this approach
does not completely cancel the DEM and chopping residuals, and is thus less
accurate.
A total of 15 devices in metal TO-5 packages were tested over the temperature
range -45 to 130°C. A linear fit shows that the duty-cycle can be expressed as
D=AT + B, where A=0.0046, B=0.30, and T is the temperature in degrees Celsius.
However, the residual curvature causes a systematic non-linearity of about
0.2°C. After batch-calibration (using the default trim setting), the sensors’
spread is less than ±0.2°C (3σ), as shown in Fig. 12.8.4 (top). The chips were
then trimmed by post-processing, rather than by definitively storing trim data in
their one-time programmable memory. A PTAT trim at 25°C only reduces the
spread to ±0.15°C (3σ), but is required to correct for the expected batch-tobatch spread of VBE3 [3]. Using the simplified average, i.e. Davg2, results in more
spread, especially at low temperatures (Fig. 12.8.4).
The sensor’s resolution was determined by logging the results of 40,000
measurements at a stable temperature (~25°C). As shown in Fig. 12.8.5 (top),
the sensor achieves a resolution of 3mK (rms) in a measurement time tm of
2.2ms (8 periods). This corresponds to a resolution FoM of 3.6pJK2. Averaging
over 100ms improves the resolution to 0.45mK (rms). In order not to degrade
the sensor’s intrinsic resolution, the sampling clock must be high enough to
minimize the effects of quantization noise. As shown in Fig. 12.8.5 (bottom),
reducing the sampling frequency from 100 to 20MHz increases the noise floor,
which translates into lower resolution: 5.5mK (rms) in 2.2ms.
The sensor’s performance is summarized in Fig. 12.8.6 and compared with that
of other energy-efficient precision temperature sensors. It can be seen from the
table that this design achieves the highest energy efficiency, as well as the
highest reported resolution for a BJT-based temperature sensor.
References:
[1] G.C.M. Meijer, et al., “A Three-Terminal Integrated Temperature Transducer
with Microcomputer Interfacing,” Sensors and Actuators, vol. 18, pp. 195-206,
June 1989.
[2] A. L. Aita, et al., “Low-Power CMOS Smart Temperature Sensor with a BatchCalibrated Inaccuracy of ±0.25°C (±3σ) from -70 ºC to 130 ºC,” Sensors J., vol.
13, no. 5, pp. 1840-1848, May 2013.
[3] K. Souri, et al., “A CMOS Temperature Sensor with a Voltage Calibrated
Inaccuracy of ±0.15°C (±3σ) from -55 °C to 125 °C,” J. Solid-State Circuits, vol.
48, no. 1, pp. 292-301, Jan. 2013.
[4] S. Shalmany, “A Micropower Battery Current Sensor with ±0.03% (3σ)
Inaccuracy from -40 to +85°C.” ISSCC Dig. Tech. Papers, pp. 1308-1313, Feb.
2013.
[5] M. Perrot, et al., “A Temperature to Digital Converter for a MEMS Based
Programmable Oscillator with Better than ±0.5ppm Frequency Stability,” J.
Solid-State Circuits, vol. 48, no. 1, pp. 206-207, Jan. 2013.
[6] Smartec BV, “Datasheet SMT 160-30 Digital Temperature Sensor,”
www.smartec-sensors.com, Nov. 2010. [online]
978-1-4799-0920-9/14/$31.00 ©2014 IEEE
ISSCC 2014 / February 11, 2014 / 11:30 AM
Figure 12.8.1: Operating principle.
Figure 12.8.2: Simplified sensor block diagram.
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Figure 12.8.3: Circuit diagram of the Schmitt trigger.
Figure 12.8.4: Measured spread of 15 samples after batch calibration (top);
ideal PTAT trimming (middle) and ideal PTAT trimming and simplified
averaging (bottom). Dashed lines indicate the ±3σ bounds.
Figure 12.8.5: FFT of sensor noise (40,000 conversions) (top); resolution vs.
measurement time (bottom).
Figure 12.8.6: Performance summary and comparison with previous work.
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Figure 12.8.7: Chip micrograph.
• 2014 IEEE International Solid-State Circuits Conference
978-1-4799-0920-9/14/$31.00 ©2014 IEEE