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TECHNOLOGY BRIEF
Low Voltage High-Speed Differential Logic Family
(D-3269)
Description:
A new differential logic family has been developed at Cornell University that achieves operation
speeds comparable to those of the current mode logic (CML) family while reducing voltage
requirements by up to 40% and power consumption by as much as 50%.
Scientific/Technical Merits:
Cornell’s new logic family was conceived as a low voltage alternative to CML. Current CML-based
logic gates rely on stacked differential pairs, and require stacks of 3 devices to implement functions
such as latch, AND gate, XOR gate, and multiplexers. For CML-based logic gates to achieve high
switching speed, sufficient voltage must be constantly maintained across the terminals of every device
in the stack, which requires bias voltages of 3.3V-5V.
In the new Cornell logic family, device stacking is reduced from three levels to two for all gates, and
the two levels share many topological features. They consist of single-level differential pairs that can
be connected in parallel instead of being stacked. The differential pairs drive emitter followers, which
can be connected in parallel or switched on and off. In contrast to CML, which performs the entire
logic operation in the current domain, Cornell’s new logic family initiates each logic operation in the
current domain using differential pairs but completes the logic operation in the voltage domain using
emitter followers. This innovation permits the power supply voltage to be significantly lower and
results in lower overall power dissipation. Below, the CML latch and a latch built using Cornell’s new
logic family are shown side by side.
VLS
_
VDD
VLS
VDD
+
+
RC
R1
R2
Rhold Q5
Q7
D
Q3
Q4
Q5
Q8 Rhold
Q
Q8
3rd
Transistor
Level
Q
CLK
Q3
Q4
CLK
D
Q1
Isw
2nd
Transistor
Level
1st
Transistor
Level
Q2
D
CLK
Q6
Q7
Q
Q6
Ib
Isw
Q
D
CLK
Q1
Q2
CLK
Q9
Q10
I1
Ihold
CML Latch
_
RC
New Latch
Office of the Vice Provost for Technology Transfer and Economic Development
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CLK
Competitive Advantage: Reducing heat generation in high-speed logic requires circuits that can attain
high switching speeds without consuming more power. One way to achieve this is by operating at
lower supply voltages. As already mentioned above, chips built using the CML logic family require
relatively high voltages (3.3V-5V). The logic family developed at Cornell achieves the high speed of
CML (50Gb/s or more, depending on specific technology) without CML’s high voltage requirements.
In tests, chips incorporating Cornell’s new logic family have demonstrated power reductions of up to
25-50% at voltages as low as 2V in Bipolar or BiCMOS technologies. Cornell’s low voltage, highspeed logic family offers particular advantages in systems featuring high circuit density, such as
microprocessors, multi-channel communication systems, high speed synchronous circuits, and
instrumentation circuits such as pseudo-random binary sequence generators (PRBS) and bit error rate
testers (BERT). Moreover, the lower supply voltages required by Cornell’s new logic are more
compatible with current semiconductor scaling trends, which can simplify the integration of highspeed logic cores with other parts of a system.
As a proof of concept, a PRBS chip was built using Cornell’s new logic gates. The table below
compares the results of tests of Cornell’s PRBS chip with all recently published results of tests of
comparable PRBS chips. The Cornell PRBS outperforms all other PRBS chips in nearly every
category, conclusively demonstrating the superiority of Cornell’s new family of logic.
Tech
Data
Rate
VDD
Power
Size
F.Schumann,
Siemens, 1997
Si
Bipolar
25 Gb/s
5V
2.3 W
1.1 x 0.86
mm2
M.G.Chen, TRW,
2000
GaAs
Bipolar
21 Gb/s
3.3 V
1.1 W
3.2 x 3.2
mm2
H. Knapp,
Infineon, 2002
SiGe
Bipolar
40 Gb/s
4.5 V
1.2 W
0.86 x 0.70
mm2
S. Kim, IBM, 2003
SiGe
BiCMOS
45 Gb/s
3.3 V
1.3 W
1.7 x 1.7
mm2
Kucharski,
CBCRL, 2004
SiGe
BiCMOS
50 Gb/s
2.5V
0.55 W
1.0 x 0.8
mm2
Author
Inventors:
Licensing Status:
Patents:
Publications:
Kevin Kornegay, Daniel Kucharski
Exclusive and nonexclusive licenses will be considered.
US patent no. 7,098,697
Kucharski, D.; Kornegay, K., "A 40 Gb/s 2.5 V 2/sup 7/-1 PRBS generator in SiGe using a low-voltage logic
family," Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International,
vol., no., pp.340-602 Vol. 1, 10-10 Feb. 2005
Kucharski, D.; Kornegay, K.T., "2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a
Low-Voltage Logic Family," Solid-State Circuits, IEEE Journal of , vol.41, no.9, pp. 2154-2165, Sept. 2006
For More Information, Contact:
Martin Teschl
Technology Commercialization and Liaison Officer
Tel. 607-254-4454
E-mail: [email protected]
Office of the Vice Provost for Technology Transfer and Economic Development
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