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Introduction to Analog-Digital-Converter Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: 31270-010, Belo Horizonte (MG), Brazil [email protected] http://www.cpdee.ufmg.br/~frank/ Agenda Introduction Characteristic Values of ADCs Nyquist-Rate ADCs Oversampling ADC Practical Issues Low Power ADC Design Copyright Sill, 2008 Analog Digital Converter 2 Introduction ADC = Analog-Digital-Converter Conversion of audio signals (mobile micro, digital music records, ...) Conversion of video signals (cameras, frame grabber, ...) Measured value acquisition (temperature, pressure, luminance, ...) Copyright Sill, 2008 Analog Digital Converter 3 ADC - Scheme Analog Digital Sample & Hold Quantization fsample Analog input can be voltage or current (in the following only voltage) Analog input can be positive or negative (in the following only positive) Copyright Sill, 2008 Analog Digital Converter 4 2. Characteristic Values of ADCs Which values characterize an ADC? What kind of errors exist? What is aliasing? Copyright Sill, 2008 Analog Digital Converter 5 ADC Values Resolution N: number of discrete values to represent the analog values (in Bit) 8 Bit = 28 = 256 quantization level, 10 Bit = 210 = 1024 quantization level Reference voltage Vref: Analog input signal Vin is related to digital output signal Dout through Vref with: Vin = Vref · (D02-1 + D12-2 + … + DN-12-N) Example: N = 3 Bit, Vref = 1V, Dout = ‘011’ => Vin = 1V · ( 2-2 + 2-3) = 1V · (0.25 + 0.125) = 0.375V Vin ADC Dout = D0D1…DN-1 Vref Copyright Sill, 2008 Analog Digital Converter 6 ADC Values cont’d VLSB : Minimum measurable voltage difference in ideal case (LSB – least significant Bit) = Vref / 2N Vin = VLSB (D02N-1 + D12N-2 + … + DN-120) Example: N = 3 Bit, Vref = 1V, Dout = ‘011’ => VLSB = 1V / 23 = 0.125V => Vin = 0.125V · ( 21 + 20) = 0.125V · 3 = 0.375V VLSB ΔV: Voltage difference between two logic level Ideal: all ΔV = VLSB VFSR : Difference between highest and lowest measurable voltages (FSR – full scale range) Copyright Sill, 2008 Analog Digital Converter 7 ADC Values cont’d SNR: Signal to Noise Ratio Ratio of signal power to noise power SNR Psignal Pnoise , SNR db Psignal 10log P noise ENOB: Effective Number of Bits Effective resolution of ADC under observance of all noise and distortions SINAD 1.76 ENOB 6.02 SINAD (SIgnal to Noise And Distortion) → ratio of fundamental signal to the sum of all distortion and noise (DC term removed) Comparison of SINAD of ideal and real ADC with same word length Copyright Sill, 2008 Analog Digital Converter 8 Ideal ADC Digital Output Dout 111 110 101 100 VFSR ΔV, VLSB 011 010 001 000 Vref 8 4 Vref 8 7 Vref 8 Analog Input Vin Copyright Sill, 2008 Analog Digital Converter 9 Further ADC Values Bandwidth: Maximum measurable frequency of the input signal Power dissipation Conversion Time: Time for conversion of an analog value into a digital value (interesting in pipeline and parallel structures) Sampling rate (fsamp): Rate at which new digital values are sampled from the analog signal (also: sample Errors: Quantization, offset, gain, INL, DNL, missing codes, non-monotonicity… Copyright Sill, 2008 Analog Digital Converter 10 Quantization Error ε 111 110 Dout 101 100 011 010 001 000 VLSB 2 7 Vref 8 VLSB 2 Copyright Sill, 2008 Vin Analog Digital Converter VLSB V LSB 2 2 11 Amplitude Quantization Error (3-Bit Flash) Error sample sample Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007 Copyright Sill, 2008 Analog Digital Converter 12 Offset Error offset 111 110 Dout 101 100 011 010 001 000 Vref 8 4 Vref 8 7 Vref 8 Vin Parallel shift of the whole curve E.g. caused by difference in ground line voltages Copyright Sill, 2008 Analog Digital Converter 13 Gain Error gain 111 110 Dout 101 100 011 010 001 000 Vref 8 4 Vref 8 7 Vref 8 Vin Corresponds to too small or to large but equal ΔV E.g. caused by too small or too large Vref Copyright Sill, 2008 Analog Digital Converter 14 Differential Non-Linearity (DNL) 111 1 DNL VLSB 2 110 Dout 101 100 1 DNL VLSB 2 011 VLSB 010 1 DNL VLSB 2 1 V VLSB 2 1 DNL VLSB 2 V 1.5VLSB VLSB 001 000 Vref 8 4 Vref 8 7 Vref 8 Vin Deviation of ΔV from VLSB value (in VLSB) Defined after removing of gain E.g. Caused by mismatch of the reference elements Copyright Sill, 2008 Analog Digital Converter 15 Integral Non-Linearity (INL) 111 1 INL VLSB 4 110 Dout 101 1 INL VLSB 2 100 011 010 001 000 7 4 Vin Vref Vref 8 8 8 Deviation from the straight line (best-fit or end-point) (in VLSB) Defined after removing of gain and offset E.g. caused by mismatch of the reference elements Vref Copyright Sill, 2008 Analog Digital Converter 16 Missing Codes 111 110 Dout 101 100 Missing Code 011 010 001 000 Vref 8 4 Vref 8 7 Vref 8 Vin Some bit combinations never appear Occurs, if maximum DNL > 1 VLSB or maximum INL > 0.5 VLSB Copyright Sill, 2008 Analog Digital Converter 17 Non-Monotonicity 111 110 Ideal curve Dout 101 100 011 Non-Monotonicity 010 001 000 Vref 8 4 Vref 8 7 Vref 8 Vin Lower conversion result for a higher input voltage Includes that same conversion may result from two separate voltage ranges Copyright Sill, 2008 Analog Digital Converter 18 Aliasing Measured data points (sample rate: fsamp) Reconstructed output signal Input signal (with fin) Too small sampling rate fsamp (under-sampling) can lead to aliasing ( = frequency of reconstructed signal is to low) Nyquist criterion: fsamp more than two times higher than highest frequency component fin of input signal: fsamp > 2·fin Copyright Sill, 2008 Analog Digital Converter 19 3. Nyquist-Rate ADCs How can Nyquist-rate ADCs be grouped? What is a dual slope ADC? What is a successive approximation ADC? What is an algorithmic ADC? What is a flash ADC? What is a pipelined ADC? What are the pros and cons of the Nyquist-rate ADCs? Copyright Sill, 2008 Analog Digital Converter 20 Nyquist-Rate ADCs Sampling frequency fsamp is in the same range as frequency fin of input signal Low-to-medium speed and high accuracy ADCs Integrating Medium speed and medium accuracy ADCs Successive Approximation Algorithmic High speed and low-to-medium accuracy ADCs Flash Two-Level Flash Pipelined Copyright Sill, 2008 Analog Digital Converter 21 Integrating (Dual Slope) ADCs Phase 1: Integration (capacitor C1) of Vin in known time Tload Qload = Vin / R1 · Tload Phase 2: Integration of reference voltage -Vref until Vout = 0 and estimation of time ΔT Qref = -Vref / R1 · ΔT = -Qload => Vin = Vref · ΔT / Tload Independent of R1 und C1! S2 C1 Vin D0 R1 D1 S1 Vout -Vref Integrator Copyright Sill, 2008 Comparator Analog Digital Converter Control logic Counter D2 D3 DN-1 22 Integrating (Dual Slope) ADCs cont’d Voltage Phase 1 Phase 2 Vin3 slope depends on Vin constant slope Vin2 Vin1 Tload Copyright Sill, 2008 ΔT1 ΔT2 Analog Digital Converter Time ΔT3 23 Integrating ADCs: pros and cons Simple structure (comparator and integrator are the only analog components) Low Area / Low Power Slow Time intervals are not constant Copyright Sill, 2008 Analog Digital Converter 24 Successive Approximation ADC Generate internal analog signal VD/A Compare VD/A with input signal Vin Modify VD/A by D0D1D2…DN-1 until closest possible value to Vin is reached Vin S&H VD/A Logic D0 D1 DAC Copyright Sill, 2008 Analog Digital Converter DN-1 Vref 25 Successive Approximation ADC cont’d V ref 2 Comparsion of VD/A with V ref Vin 2 V ref Vin 2 V Comp. w. ref 4 V V ref ref Vin Vin 4 4 Vin Comp. w. V ref Vin 4 S&H VD/A V ref Vin 4 Logic D0 D1 DAC Copyright Sill, 2008 3V ref 4 Analog Digital Converter DN-1 Vref 26 Successive Approximation ADC cont’d 111 7 Vref 8 110 110 VD/A 101 Vin 011 010 Vref 1. 2. 3. Iterations 011 010 001 8 101 100 100 4 Vref 8 111 001 000 final result P. Fischer, VLSI-Design - ADC und DAC, Uni Mannheim, 2005 Copyright Sill, 2008 Analog Digital Converter 27 Successive Approx.: pros and cons Low Area / Low Power High effort for DAC Early wrong decision leads to false result Copyright Sill, 2008 Analog Digital Converter 28 Algorithmic ADC Same idea as successive approximation ADC Instead of modifying Vref → doubling of error voltage (Vref stays constant) D0 D1 Vin S1 S&H DN-1 Shift register X2 S&H S2 Vref/4 -Vref/4 Copyright Sill, 2008 Analog Digital Converter 29 Algorithmic ADC con’t Start Vin Sample V = Vin, i = 1 V>0 S1 no X2 yes S&H Di = 1 Di = 0 V = 2(V - Vref/4) V = 2(V + Vref/4) i = i+1 no S&H S2 i>N -Vref/4 Vref/4 yes Shift register Stop D.A.. Johns, K. Martin, Analog Integrated Circuit design, John Wiley & Sons, 1997 Copyright Sill, 2008 Analog Digital Converter D0 D1 DN-1 30 Algorithmic ADC: pros and cons Less analog circuitry than Succ. Approx. ADC Low Power / Low Area High effort for multiply-by-two gain amp Copyright Sill, 2008 Analog Digital Converter 31 Flash ADC Vref Vin R/2 Over range R R D0 R R N (2 -1) to N encoder D1 R Vin connected with 2N comparators in parallel Comparators connected to resistor string Thermometer code R/2-resistors on bottom and top for 0.5 LSB offset DN-1 R R R/2 Copyright Sill, 2008 Analog Digital Converter 32 Some Flash ADC design issues Input capacitive loading on Vin Switching noise if comparators switch at the same time Resistors-string bowing by input currents of bipolar comparators (if used) Bubble errors in the thermometer code based on comparator’s metastability Copyright Sill, 2008 Analog Digital Converter 33 Flash ADC: pros and cons Very fast High effort for the 2N comparators High Area / High Power Recommended for 6-8 Bit and less Copyright Sill, 2008 Analog Digital Converter 34 Two-Level Flash ADC Conversion in two steps: 1. Determination of MSB-Bits and reconverting of digital signal by DAC 2. Subtraction from Vin and determination of LSB-Bits F.e. 8-Bit-ADC: Flash: 28=256 comparators, Two-level: 2·24 = 32 comparators gain amp Vin N/2-Bit Flash ADC N/2-Bit DAC MSB (D0 … DN/2-1) Copyright Sill, 2008 x2 N N/2-Bit Flash ADC LSB (DN/2 … DN-1) Analog Digital Converter 35 Two-Level Flash ADC: pros and cons Same throughput as Flash ADC Less area, less power, less capacity loading than Flash ADC Easy error-correction after first stage Larger latency delay than Flash ADC Design of N/2-Bit-DAC Currently most popular approach for highspeed/medium accuracy ADCs Copyright Sill, 2008 Analog Digital Converter 36 Pipelined ADCs Extension of two-level architecture to multiple stages (up-to 1 Bit per stage) Each stage is connected with CLK-signal Pipelined conversion of subsequent input signals First result after m CLK cycles (m - amount of stages) Stages can be different CLK Vin,0 Stage 1 D0 – Dk-1 Copyright Sill, 2008 Vin,1 Stage 2 Dk – D2k-1 Analog Digital Converter Vin,m-1 Stage m Dmk – DN-1 37 Pipelined ADCs: Scheme CLK Vin,i S&H x2k k-Bit ADC Vin,i+1 k-Bit DAC k Bits Vin,0 Stage 1 Vin,1 Vin,m-1 Stage 2 Stage m CLK Time Alignment & Digital Error Correction D0 D1 Copyright Sill, 2008 DN-1 Analog Digital Converter 38 Pipelined ADC: pros and cons High throughput Easy upgrade to higher resolutions High demands on speed and accuracy on gain amplifier High CLK-frequency needed High Power Copyright Sill, 2008 Analog Digital Converter 39 4. Oversampling ADCs What are the problems of the quantization noise? How does oversampling work? What is noise shaping? What is a sigma-delta ADC? Copyright Sill, 2008 Analog Digital Converter 40 Quantization Error ε (recap) 111 110 Dout 101 100 011 010 001 000 VLSB 2 7 Vref 8 VLSB 2 Copyright Sill, 2008 Vin Analog Digital Converter VLSB V LSB 2 2 41 Quantization Noise Quantization error ε with probability density p(ε) can be approximated as uniform distribution p(ε) VLSB / 2 p̂ p d 1 VLSB / 2 VLSB 2 Copyright Sill, 2008 VLSB 2 ε Analog Digital Converter pˆ 1 VLSB 42 Quantization Noise cont’d Quantization noise reduces Signal-Noise-Ration (SNR) of ADC Estimation of SNR with Root Mean Square (RMS) of input signal (Vin_RMS) and of noise signal (Vqn_RMS) SNR = Vin_RMS / Vqn_rms Vqn _ RMS 1/ 2 2 p d 1 VLSB 1/ 2 d VLSB / 2 VLSB / 2 2 VLSB 12 Every additional Bit halves VLSB → Vqn_RMS decreases by 6 dB with every new Bit F.e. Vin is sinusoidal wave → SNR = (6.02 N + 1.76) dB Copyright Sill, 2008 Analog Digital Converter 43 Quantization Noise cont’d Quantization noise can be approximated as white noise Spectral density Sε(f) of quantization noise is constant over whole sampling frequency fs Sε(f) S fs 2 fs 2 Quantization noise power P fs / 2 fs / 2 Copyright Sill, 2008 Analog Digital Converter VLSB 12 1 fs f S f 2 VLSB 2 df 12 44 Amplitude Quantization Error (3-Bit Flash, recap) Error sample sample Eugenio Di Gioia, Sigma-Delta-A/D-Wandler, 2007 Copyright Sill, 2008 Analog Digital Converter 45 Oversampling (OS) Quantized signal is low-pass filtered to frequency f0 elimination of quantization noise greater than f0 |H(f)| Vin(f) 1 H(f) fs 2 f0 2 f0 2 fs 2 f Oversampling rate (OSR) is ratio of sampling frequency fs to Nyquist rate of f0 OSR f s 2 f0 Copyright Sill, 2008 Analog Digital Converter 46 OS in Frequency Domain Average quantization noise f0/2 Copyright Sill, 2008 Oversampling f Power Power Signal amplitude Digital filter response f0/2 Analog Digital Converter f fs/2 = OSR·f0/2 47 Oversampling cont’d Quantization noise power Pε results to: fs / 2 f0 / 2 2 V 2 2 2 LSB 1 P S ( f ) H ( f ) df S df 12 OSR fs / 2 f0 / 2 Doubling of fs increases SNR by 3 dB Equivalently to a increase of resolution by 0.5 Bits F.e. Vin is sinusoidal wave SNR = (6.02 N + 1.76 + 10log [OSR]) dB Copyright Sill, 2008 Analog Digital Converter 48 OS signal reconstruction x[n] Oversampling - ADC 1V 0.66 V 0.33 V Nyquist -ADC Nyquist - ADC n 0.33 0.33 Oversampling 00000011111111110000000 5 1 2 VRMS _ Oversampling 7 02 5 12 7 02 24 VRMS _ Nyquist 0.332 0.332 2 Signal results from relation of “0”s and “1”s Copyright Sill, 2008 Analog Digital Converter 49 Noise Shaping (NS) Next trick: feedback loop Quantization noise signal is negative coupled with input Integrator Quantizer X E Y H(z) DAC Based on high gain of closed-loop at low frequencies: Quantization noise reduced at low frequencies Quantization noise is ”shaped” = moved to higher frequencies YX Copyright Sill, 2008 H 1 E X 1 H 1 H H 1 Analog Digital Converter 50 Noise Shaping cont’d Oversampling and noise shaping: Doubling of fs increases SNR by 9 dB Equivalently to a increase of resolution by 1.5 Bits F.e. Vin is sinusoidal wave SNR = (6.02 N + 1.76 – 5.17 + 30log [OSR]) dB up to fin = 100 kHz (and more) 1-Bit Quantizer (Comperator) 1-Bit DAC Copyright Sill, 2008 Analog Digital Converter 51 OS and NS in Frequency Domain Oversampling Average quantization noise f0/2 f Power Power Signal amplitude Digital filter response f0/2 f fs/2 = OSR·f0/2 Power Oversampling and noise shaping f0/2 Copyright Sill, 2008 fs/2 Analog Digital Converter f 52 Sigma Delta ADC Example Vin = 1.2 V 1.2 -1.3 3.7 -1.3 1.2 -0.1 3.6 2.3 vin t t dt vin t t 2.5 -2.5 2.5 2.5 1 0 1 1 Comparator DAC Vref = 2.5 V Copyright Sill, 2008 Analog Digital Converter 53 Sigma Delta ADC Example (Curves) 1Bit -Quantizer DAC CLK http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma_D.html Copyright Sill, 2008 Analog Digital Converter Integrator H(z) 54 Sigma Delta ADC: pros and cons High resolution Less effort for analog circuitry Low speed High CLK-frequency Currently popular for audio applications Copyright Sill, 2008 Analog Digital Converter 55 5. Practical issues What are the performance limitations of ADCs? What are the differences between PCBand IC-designs? Are there hints to improve the ADC design? What are S&H circuits? Copyright Sill, 2008 Analog Digital Converter 56 Performance Limitations Analog circuit performance limited by: High-frequency behavior of applied components Noise (analog ↔ analog, analog ↔ digital) Power supply coupling Thermal noise (white noise) Crosstalk Parasitic components (capacitances, inductivities) Wire delays Copyright Sill, 2008 Analog Digital Converter 57 Parasitic Component Example Effect of 1pF capacitance on inverting input of an opamp: Mancini, Opamps for everyone, Texas Instr., 2002 Copyright Sill, 2008 Analog Digital Converter 58 Noise Demands Examples Example 1: Vref = 5V, 10 Bit resolution VLSB = 5V / 210 = 5V / 1024 = 4.9 mV Every noise must be lower than 4.9 mV Example 2: Vref = 5V, 16 Bit resolution VLSB = 5V / 216 = 5V / 65536 = 76 µV Every noise must be lower than 76 µV Copyright Sill, 2008 Analog Digital Converter 59 PCB- versus IC-Design PCB: Printed Circuit Board, IC: Integrated Circuit Noise in PCB-circuits much higher than in ICs Influences of parasitics in PCB-circuits much higher than in ICs High-frequency behavior of PCB-circuits much worse than of ICs Wire delays in PCB much higher than in ICs High accuracy, high speed, high bandwidth ADCs only possible in ICs! Copyright Sill, 2008 Analog Digital Converter 60 Some Hints for Mixed Signal Designs For PCB and IC: Keep ground lines separate! Don’t overlap digital and analog signal wires! Mancini, Opamps for everyone, Texas Instr., 2002 Don’t overlap digital and analog supply wires! Locate analog circuitry as close as possible to the I/O connections! Choose right passive components for high-frequency designs! (only PCB) Copyright Sill, 2008 Analog Digital Converter 61 Sample and Hold Circuits S&H circuits hold signal constant for conversion A sample and a hold device (mostly switch and capacitor) Demands: Small RC-settling-time (voltage over hold capacitor has to be fast stable at < 1 LSB) Exact switching point (else “aperture-error”) Stable voltage over hold capacitor (else “droop error”) No charge injection by the switch Copyright Sill, 2008 Analog Digital Converter 62 6. Low Power ADC Design What are the main components of power dissipation? How can each component be reduced? What are the differences between power and energy? Copyright Sill, 2008 Analog Digital Converter 63 Power Dissipation Two main components: Dynamic power dissipation (Pdyn) Based on circuit’s activity Square dependency on supply voltage VDD2 Dependent on clock frequency fclk Dependent on capacitive load Cload Dependent on switching probability α Pdyn = VDD2 · Cload · fclk · α Static power dissipation (Pstatic) Constant power dissipation even if circuit is inactive Steady low-resistance connections between VDD und GND (only in some circuit technologies like pseudo NMOS) Leakage (critical in technologies ≤ 0.18 µm) Copyright Sill, 2008 Analog Digital Converter 64 Low Power ADC Design Reduction of VDD: influence on power (P ~ VDD2) Sadly, delay increases (td ~ 1/VDD ) Sadly, loss of maximal amplitude → SNR goes down Possible solutions: Different supply voltages within the design Dynamic change of VDD depending on required performance Highest Reduction of fclk: Dynamic Copyright Sill, 2008 change of fclk Analog Digital Converter 65 Low Power ADC Design cont’d Reduction of Cload: Cload depends on transistor count and transistor size, wire count and wire length Possible Solutions: Reduction of amount evaluating components Sizing of the design = all transistor get minimum size to reach desired performance Intelligent placing and routing Copyright Sill, 2008 Analog Digital Converter 66 Low Power ADC Design cont’d Reduction of α: Activity = possibility that a signal changes within one clock cycle Possible Solutions: Clock gating → no clock signal to inactive blocks High active signals connected to the end of blocks Asynchronous designs Copyright Sill, 2008 Analog Digital Converter 67 Which ADC for Low Power? If low speed: Dual Slope ADC Area is independent of resolution Less components Problem: Counter If medium / high speed: mixed solutions Popular: pipelined ADC with SAR Pipelined solutions allows reduction of VDD Long latency but high throughput Copyright Sill, 2008 Analog Digital Converter 68 Power vs. Energy Power consumption in Watts Power = voltage · current at a specific time point Peak power: Determines power ground wiring designs and Packaging limits Impacts of signal noise margin and reliability analysis Energy consumption in Joules Energy = power · delay (joules = watts * seconds) Rate at which power is consumed over time Lower energy number means less power to perform a computation at the same frequency Copyright Sill, 2008 Analog Digital Converter 69 Power vs. Energy cont’d Power is height of curve Watts Approach 1 Approach 2 time Energy is area under curve Watts Approach 1 Approach 2 time Copyright Sill, 2008 Analog Digital Converter 70 Power vs. Energy: Simple Example Vin VDD Vin VDD I I Flash 2L-Flash Shaded blocks are ignored Dissipation for one input signal: VDD I (each gray block) Delay Power Energy Flash 1V 1 µA 1 ns 4 µW 4 fJ 2L-Flash 1V 1 µA 2.5 ns 2 µW 5 fJ Copyright Sill, 2008 Analog Digital Converter 71 Low Power ADCs Conclusion There is no patent solution for low power ADCs! Every solution depends on the specific task. Before optimization analyze the problem: Which resolution? Which speed? What are the constraints (area, energy, VDD, Vin,…)? Which technology can be used? Think also about unconventional solutions (dynamic logic, asynchronous designs, …). Copyright Sill, 2008 Analog Digital Converter 72 Open Questions Is there another way to design low power ADCs? Is it recommended to reduce the analog part and put more effort in the digital part? How do I achieve a high SNR with low power ADCs? Is it better to have only one block with high frequency or many blocks with low frequency? How can asynchronous designs help me? How do I realize a low power ADC in sub-micron technologies? Copyright Sill, 2008 Analog Digital Converter 73 Basic ADC Literature [Azi96] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design”, Oxford University Press, 2002 P.M. Aziz, H. V. Sorensen, J. Van der Spiegel, "An Overview of Sigma-Delta Converters" IEEE Signal Processing Magazine, 1996 [Eu07] E. D. Gioia, “Sigma-Delta-A/D-Wandler”, 2007 [Fi05] P. Fischer, “VLSI-Design 0405 - ADC und DAC”, Uni Mannheim, 2005 [Man02] Mancini, “Opamps for everyone”, Texas Instr., 2002 [Joh97] D. A. Johns, K. Martin, “Analog Integrated Circuit design”, John Wiley & Sons, 1997 S. Tanner, “Low-power architectures for single-chip digital image sensors”, dissertation, University of Neuchatel, Switzerland, 2000. [All02] [Tan00] Copyright Sill, 2008 Analog Digital Converter 74 More Questions? Signal Reconstruction Continuous time (input signal): v(t) T /2 VRMS _ ct v (t ) 2 dt T T / 2 time Discrete (reconstructed by ADC): x[n] n x[n] 2 VRMS _ discrete i 0 n n RMS: root mean square Copyright Sill, 2008 Analog Digital Converter 76 For analog design, it is shown that a voltage supply reduction does not always lead to a power consumption reduction for several reasons: Threshold of MOS transistors. Loss of maximal amplitudes (SNR degradation). Limits of conduction in analog switches. Low speed of MOS transistors. Limited stack of transistors. Copyright Sill, 2008 Power Dissipation [mW/MS/s] Voltage supply reduction [Tan00] 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 Supply Voltage [V] Power consumption of 10-bit S-C 1.5 bit/stage pipelined ADCs in function of the voltage supply. [Tan00] S. Tanner, Low-power architectures for single-chip digital image sensors, dissertation, University of Neuchatel, Switzerland, 2000. Analog Digital Converter 77