Download Ensuring Power integrity

Design guidelines for
EMC of electronic devices
Summary
1.
Introduction
2.
Guidelines for signal integrity
3.
Guidelines for power integrity
4.
Guidelines for reduced radiated emission
5.
Reduction of I/O noise
6.
Spread-spectrum frequency modulation
2
May 17
Introduction
EMC should be taken into account at early design stage…
K. Armstrong, Advanced PCB
design and layout for EMC
3
May 17
Introduction
Why taking into account EMC for ICs ?
K. Armstrong, Advanced PCB
design and layout for EMC
4
Introduction
Which problems? Know your enemy
Power integrity
(PI)
Signal integrity
(SI)
ESD, EFT,
EOS
Radiated
immunity (RI)
Conducted
emission (CE)
Integrated circuits /
electronic applications
Radiated
emission (RE)
Conducted
immunity (CI)
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May 17
Design guidelines for EMC
Guidelines for signal integrity
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May 17
Guidelines for signal integrity
Signal integrity (SI) issue
Zc ; Tp
VL
VG
VL or VG
Vdd
Criterion for SI issue:
Overshoot
VIH
Undetermined
level
Undershoot
VIL
0
Ringing
t
if Tr is the rising or falling time of
a signal, SI issues due to the
propagation of the EM wave along
the transmission line arise if:
Tr  TP
Longer setting
time
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May 17
Guidelines for signal integrity
Signal integrity (SI) issue
K. Armstrong, Advanced PCB
design and layout for EMC
8
May 17
Guidelines for signal integrity
Ensuring Signal integrity – Rule 1
Cancel reflection coefficient at each line terminals by
impedance matching
L  0  Z L  Z C
Impedance matching of a
uniform transmission line with
constant characteristic
impedance Zc.
G  0  Z G  Z C

Vcc
Practical designs for a digital transmission:
Zc
Rs
Zc
Rpd
Rpd
Ct
Rs : serial resistor= Rdriver - Zc
Rpd : pull down resistor = Zc
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May 17
Guidelines for signal integrity
Ensuring Signal integrity – Rule 2
Control the characteristic impedance of transmission line (PCB track,
package) and avoid line discontinuities

Microstrip line configuration:
W
t
εr
I
Z C  
h
Ideal ground plane
87
 5.98h 
ln 

0
.
8
W

t
 eff  1.414 

Tp  ps / mm  3.34 0.475 r  0.67
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Guidelines for signal integrity
Ensuring Signal integrity – Rule 2

Example: consider the following PCB stack-up. A digital link between 100 Ω
driver and receiver is ensured by a microstrip line routed in layer 4.

Propose a value for the line width.
Driver circuit
Receiver circuit
Layer 1
t = 35 µm
Ground plane
t = 35 µm
FR4 insulating material Power plane
(εr = 4.5, tan δ = 0.02)
Microstrip line
0.38 mm
h= 0.7 mm hPCB = 1.6 mm
0.38 mm
Layer 4
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Guidelines for signal integrity
Ensuring Signal integrity – Rule 3
Ensure a controlled and short return current path.

Place a full ground plane in microstrip line.

Avoid slot in return plane (e.g. ground plane)

Keep a symmetry (avoid unbalance in the return current path)

Avoid routing of critical signals along board edge.
CORRECT
Microstrip line
BAD
Ground plane
Microstrip line
I
Return
current
Low frequency behavior
Microstrip line
Ground plane
with a slot
I
Ground plane
Return
current
I
Return
current
High frequency behavior
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Guidelines for signal integrity
Ensuring Signal integrity – Rule 4
If available, use on-chip techniques
to improve signal integrity
•
•
On-chip termination, programmable
output driver impedance
Pre-emphasis/De-emphasis,
equalization
5Gbps - Without pre-emphasis
(Xilinx)
5Gbps - With pre-emphasis
13
(Altera)
Guidelines for signal integrity
Crosstalk

Example: voltage measurement at 3 terminals of two 20 cm long
parallel PCB tracks.

The first line is excited by a pulse generator, the second is
terminated by two resistive loads.
Origin of effects
on both lines ?
Guidelines for signal integrity
Crosstalk
Trace 1 (emitter)
I1
d
Trace 2 (victim)
W
W I1’
h V
Parasitic return
current path
“Normal” return
current path
Z0, Td
R0
Vi
VS
LS
NEXT
R0
V NE 
Td
2
 CM
L  dV t  2Td 

 M  i
LS 
dt
 CS  CM
VFE 
Td
2
 CM
L  dV t  Td 

 M  i
LS 
dt
 CS  CM
CM
CS
LM
R0
R0
VNE
Crosstalk = near-field
coupling
εr
I2
Z0, Td
LS
CM
VFE
FEXT
Evaluate the crosstalk in the case study.
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Guidelines for signal integrity
Ensuring Signal integrity – Rule 5
Increase the isolation between emitter and victim lines

Increase the distance between traces (rule 3 W = “the separation between
traces must be 3 times the width of the trace as measured from centerline
to centerline of two adjacent traces”)
W
< 3W
W
t
h
(εr = 4.5)
Substrate
ground
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May 17
Design guidelines for EMC
Guidelines for power integrity
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May 17
Guidelines for power integrity
Power Distribution Network
Ensuring a stable power/ground voltage
reference (ΔVdd < 5% Vdd nominal)
Bulk capacitor
(Low frequency)
Power
source
Ground
reference
HF
capacitor
(ceramic)
Ferrite
Voltage
converter /
regulator 1 µF – 10 mF
100 nF – 1 nF
PCB – Power /
ground plane
Vdd
Vss
1 nF
Transistors, gates,
interconnects
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May 17
Package
and IC
Guidelines for power integrity
Power integrity (PI) issue
Power supply source
(regulator, DC-DC converter)
ΔVdd
PDN
Vdd
i(t)
Noisy Integrated
circuit
Vss
Circuit
Power supply
bounce
PDN
V  RPDN i  LPDN
IR noise
i
t
Delta-I noise
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May 17
ΔVss
Guidelines for power integrity
Power integrity (PI) issue

Example: Measurement of the power supply voltage fluctuation of a
digital circuit
Low frequency
contribution
High frequency
contribution
Switching
Switching
Switching
Noise with a large frequency content and
some major resonance modes
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Guidelines for power integrity
Ensuring power integrity – Rule 1
Maintain PDN impedance below the target impedance

Equivalent model of a PDN (the most basic model…)
PDN
Circuit
Vdd
ZPDN
ΔVdd
Power supply voltage bounce:
Vdd  f   Z PDN  f   I IC  f 
IIC
gnd
 Ensuring power integrity relies on the control of a low impedance of the PDN.

A target impedance ZT can be defined as a design objective:
ZT 
Vdd max
I average
ZPDN
Zt
Target frequency
range
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Frequency
May 17
Guidelines for power integrity
Ensuring power integrity – Rule 2
Reduce interconnect parasitic (mainly inductance) of power and ground
connections

Use traces as wide as possible for Vdd and Vss connections

i.e. use power and ground planes

Be careful of the common impedance of Vdd and Vss connections (finite
impedance, even for ground plane):
Single point grounding with
serial circuits
Régulateur
VDD
L1
Circuit 1
VSS
VDD
Circuit 2
Direct grounding to a
reference ground plane
VDD
Circuit 3
VDD
Régulateur
L2
VSS
L3
Circuit 1
VDD
Circuit 2
V1  L1
dI 1  dI 2  dI 3
dt
V2  V1  L2
I2+ I3
dI 2  dI 3
dt
I3
V3  V2  L3
Circuit 3
VSS
L1
Plan de masse
dI 3
dt
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May 17
I1
VSS
VSS
VSS
I1+I2+ I3
VDD
L2
I2
L3
I3
Guidelines for power integrity
Ensuring power integrity – Rule 2
2.1) Use shortest interconnection to reduce the serial inductance
•
•
•
Inductance is a major source of resonance
Each conductor acts as an inductance
Ground plane modifies inductance value (worst case is far from ground)
Reducing inductance
decreases SSN !!
Lead: L=0.6nH/mm
Bonding: L=1nH/mm
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May 17
Guidelines for power integrity
Ensuring power integrity – Rule 2
2.1) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
Die of the IC
Long
leads
bonding
Far from ground
PCB
Short
leads
Flip chip package:
L up to 3nH
Die of the IC
balls
Close from ground
Requirements for high speed microprocessors : L < 50 pH !
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May 17
Guidelines for power integrity
Ensuring power integrity – Rule 2
2.2) Use enough Vdd/Vss pairs
Case 2 : Texas Instruments
OMAP3630 (Application processor)
Case 1 : Micron T46H64M16LF
Mobile LP DDR SDRAM
515 I/O pins, 110 power supply
pins, 80 ground pins
60 I/O pins, 8 power supply
pins, 7 ground pins
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May 17
Guidelines for power integrity
Ensuring Power integrity – Rule 3
Add decoupling capacitor to reduce power supply bounce as
close as possible from noise source (current demand)

Principle:
Voltage
regulator
Local charge
tank
Voltage
bounce v(t)
Decoupling
capacitor
IC
Vdd
Vss
Vdd
PCB
Vss
In time domain
i t   Cdec
i(t)
In frequency domain
dvt 
dt
V  f   Z Cdec I  f 
Large capacitors reduce
PDN impedance.
Large capacitors react
rapidly to charge demand.
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May 17
Guidelines for power integrity
Ensuring Power integrity – How choosing decoupling capacitor ?

If ideal capacitor, only one decoupling capacitor per power domain would
be enough:
I  tr
Cdec 
Vdd max
• Cdec: the minimum capacitor able to provide
a current to the circuit without any large
voltage fluctuations.
• ΔVddmax : max allowed voltage fluctuation
• ΔI : current peak absorbed by the circuit
• tr : rise time of the current peak
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May 17
Guidelines for power integrity
Ensuring Power integrity – How choosing decoupling capacitor ?

Case study 2 : decoupling of FPGA power supplies.

Two power domains: Core domain (1.2 V) and I/O domain (3.3 V)

Transient current estimation:


Core domain: Ipeak = 2 A during 10 ns

I/O domain: 196 I/Os, typ. rise/fall time = 2 ns, typ. load = 20 pF
Propose a budget of decoupling capacitors
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May 17
Guidelines for power integrity
Ensuring Power integrity – How choosing decoupling capacitor ?

Case study 2 : decoupling of FPGA power supplies.

Recommendations from the manufacturer:

Power domain
Recommended decoupling capacitors
Core
1x 100 µF, 5x 4.7 µF, 1x 470 nF
I/O
4x 100 µF, 4x 4.7 µF, 6x 470 nF
Plus all the recommendations about PDN routing and capacitor
placement !
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May 17
Guidelines for power integrity
Ensuring Power integrity – Real decoupling capacitors

Impedance profile in frequency domain:
X7R 50 V ceramic capacitors
100 µF electrolytic capacitor
On which frequency range are these
decoupling capacitors really efficient ?
,
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May 17
Guidelines for power integrity
Ensuring Power integrity – How choosing decoupling capacitor

Methodology to optimize the choice of decoupling capacitors:
Board model
Regulator model
Circuit(s) model
Define Zt
PDN without decoupling model
Define freq. range of decoupling
Fmin  Fmax
Compute ZPDN
YES
If ZPDN(f) > Zt for f in [Fmin;Fmax]
NO
Add capacitor(s) and/or change
capa values
Power integrity OK – Decoupling
budget
Capacitors model
May 17
Guidelines for power integrity
Ensuring Power integrity – How choosing decoupling capacitor

Example: decoupling of a 16 bit microcontroller (dspic33F).

The circuit produces a significant amount of noise over the range 1 – 500 MHz.

We select Zt = 2 Ω.
IC Current (1 Ω probe)
Z PDN (VNA measurement)
Board + IC without decap
ZT
With 6×100 nF
decap
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May 17
Design guidelines for EMC
Guidelines for reduced radiated
emission
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May 17
Guidelines for reduced radiated emission
Radiated emission – basic mechanisms

Radiated emissions come from interconnects excited by a transient
current or voltage. They become parasitic antennas.

Two basic radiated mechanisms:
 Dipole antenna (electric)
 Loop antenna (magnetic)
 Low impedance load (power supply, I/O
loaded by low impedance
 H field proportional to surface S
Magnetic
field
Circuit
VSS
 high impedance load (I/O loaded by
high impedance)
 E field proportional to length l
Electric field
Circuit
I
Clock
VDD
Length l
Surface S
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May 17
High Z load
Guidelines for reduced radiated emission
Reducing radiated emission – Rule 1
Reduce parasitic antenna (length or surface) to reduce differntial and
common mode radiation

Identify current loops on PCB and reduce their surface.

Place decoupling capacitors as close as possible to IC pins.

Use power or ground plane to reduce current loop surface.

Reduce the length of interconnects which carry high frequency signals.
Circuit
Circuit
VDD
VSS
Id
VDD
Decoupling
capacitor
VSS
Id
Smaller loop  Reduced
radiated differential mode
Large loop  High
radiated differential mode
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May 17
Decoupling
capacitor
Guidelines for reduced radiated emission
Reducing radiated emission – Rule 2
Control the current return path to reduce common mode
Example 2: one differential
output buffer with a non
symmetrical routing
Example 1: one Vdd pin but
two Vss pins
IVdd = IVSS1+IVSS2
Power
Circuit
VSS2
VDD
VSS1
Differential buffer
IVdd
D-
IVss1
IVSS2
I+
D+
GND
Ic
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May 17
I-
I+ ≠ IParasitic
coupling
Guidelines for reduced radiated emission
Reducing radiated emission – Rule 3
Use a “good” ground plane(s) to shield noisy interconnects

Use coplanar or stripline configuration to shield noisy interconnect.

A “good” reference plane is equipotential at any point !

Connect two reference plane witth same potential by vias regular interval
less than λ/20 !
Correct connection
between two planes with
same potential
Stripline configuration
Ref plane
line
GND
d

20
via
Ref plane
GND
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May 17
Guidelines for reduced radiated emission
Radiated emission – Case study – Student project

Basic digital applications routed on a 2 layer board with the auto-router
function of the board design tool. Only one 100 nF decoupling capacitor
for all the application.

Measurement of radiated emission in TEM cell.
Limit CISPR25
42
Guidelines for reduced radiated emission
Radiated emission – Case study – Student project

Numerous EMC design rules violation: large power-ground loops, long
fast clock interconnect, return path not ensured by a ground plane…

Change the placement & routing of the board by starting to place Vdd/Vss
and fast clock, add a ground plane on both side.

Design rule violation examples:
Large loop
CMOS
inverter
Vdd
connection
Vss
connection
43
“High speed”
clock source
Equivalent surface of
fast clock interconnect
Guidelines for reduced radiated emission
Radiated emission – Case study – Student project
Top layer
Effect of placement & Routing improvement
(still one 100 nF decoupling capacitor)
-30 dB
Bottom layer
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May 17
Design guidelines for EMC
Reduction of I/O noise
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May 17
Reduction of I/O noise
Rule1: As I/Os are one of the most contributor to radiated or conducted
emission, reduce I/O noise
 Reduction of the fast rate of I/O current.

Minimize the number of simultaneous switching lines (bus coding)

Reduce di/dt of I/O by controlling slew rate and drive
Tr1
Tr2
SR & Drive
control
Emission
level
1/Tr2
46
f
1/Tr1
May 17
Reduction of I/O noise
Reduce I/O noise – Case study

Example: I/O buffer with Drive and slew rate control options: Full or
reduced drive, high and limited slew rate.

Impact of I/O options on timing waveform:
Rise time = 2 ns
Rise time = 8.6 ns
Full Drive – High slew rate
Reduced Drive – High slew rate
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May 17
Reduction of I/O noise
Reduce I/O noise – Case study

Impact of I/O options on timing waveform and output drive current:
What is the more « emissive » option ? The less emissive ?
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May 17
Reduction of I/O noise
Reduce I/O noise – Case study

Comparison of conducted emission (1 ohm method)
49
Reduction of I/O noise
Reduce I/O noise – Case study

Comparison of conducted emission (1 ohm method)
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May 17
Design guidelines for EMC
Spread-spectrum frequency
modulation
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May 17
Spread spectrum frequency modulation
Frequency modulation

Frequency modulation spreads the spectrum of a signal

Example : sinus clock at Fc = 100 MHz vs modulated sinus clock:
Carrier frequency Fc = 100 MHz
Reduction of narrow
band RF energy
Modulation frequency FM = 1 MHz
Frequency excursion dF = +/- 5 MHz
Spread spectrum over B
 Modulation index md = 5


df
S FM t   cos C t 
cos M t 
FM


S FM t   cosC t  md cos M t 
Carson rule:
B  2  FM  md  1
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May 17
Spread spectrum frequency modulation
Rule1: Reduce noise from clock or PWM signals by using Spread
Spectrum Frequency Modulation (SSFM)
Principle:
Unmodulated clock (carrier)

Freq. modulation ΔF
Clock in
Clock out
Tc
Modulant
Tc+/-dt
Frequency Modulated clock
+/- dt
t
TMod
dP
Modulated
clock
B
Unmodulated
clock
53
Carson rule applies also (for
fundamental frequency):
B  2  Fmod  md  1
What is the amplitude
reduction?
Spread spectrum frequency modulation
Emission improvement

The reduction of spectrum amplitude depends on:

Parameters of the modulation (md and Fm)

The modulant waveform (selection of a waveform that makes the
spectrum as flat as possible)

Receiver bandwidth RBW:
P
RBW
dP
P
unmodulated
Measured
SSFM signal
EMI receiver
SSFM
B
B
P
f
 B 
dPdB   10 log 

 RBW 
RBW
54
B
f
Measured
SSFM signal
f
Spread spectrum frequency modulation
Case study – Class-D amplifier MAX9768


Two output modulations:

Classic PWM mode

Filterless modulation mode
Three operating modes:

Fixed frequency (300 or 360 kHz)

SSFM (Fc = 300 kHz, df = +/- 7.5 kHz)

External clock (1 to 1.6 MHz)
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May 17
Spread spectrum frequency modulation
Case study – Class-D amplifier

Observe the effect of the internal SSFM on the fundamental frequency of
the common-mode noise which propagates along the speaker cable. Use
a narrow RBW.

Observe the effect of the internal SSFM on the spectrum of the commonmode noise which propagates along the speaker cable. Use a narrow
RBW.

EN55022 recommends the following RBW:

•
9 kHz from 150 kHz to 30 MHz
•
120 kHz from 30 MHz to 1 GHz
What is the effect of the internal SSFM on the conducted emission?
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May 17
Spread spectrum frequency modulation
Case study – Class-D amplifier

How could you improve the conducted emission reduction ?

Identify the optimal waveform to reduce the conducted emission.

Validate it on the MAX9768 class-D amplifier.
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May 17