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Development of low-mass, high-density,
hybrid for the silicon microstrip sensors
in high track density environment
A. Clark, D. Ferrere, M. Weber, S. G. Sevilla (Univ. of Geneva)
K. Hara (Univ. of Tsukuba)
Y. Ikegami, T. Kohriki, S. Terada Y. Unno (KEK)
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Introduction
SLHC
x10 higher luminosity of LHC
Impact to silicon microstrip region
Radiation damage
Occupancy
sensor
Short strips
2.4 cm
Long strips
9.7 cm
n-in-p
short strip
module ?
readout hybrid ?
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Integration concepts
Stave
Tight cooling contact, Low-mass, Automatic assembly, …
Hybrid glued to sensors. These glued to bus tape. This glued to
cooling substrate.
Module
• modularity
production, QA, repairs, etc. ➡ parallel tasks
• reparability and replaceability
• possibility of Z-overlapping
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Module
Current SCT barrel module
Double side module
Sensor size
12cm x 6cm
Strip length
12cm
p-in-n 768 strips (80um pitch)
1 hybrid (wrap-round)
with 12 ABCD3T ASICs
bridging over the sensors
01/10/2009 Y. Ikegami, KEK
Next SCT module
Double side module
Sensor size
10cm x 10cm
Strip length
2.4cm
n-in-p 1280 strips (74.5um pitch)
4 hybrids (separated)
with 20 ABCN ASICs each
bridging over the sensors
RD09, Florence
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Wire bonding scheme
A direct wire bonding scheme between sensors and FE chips will
be adopted to eliminate pitch adaptors. The maximum fanning
angle amounts to 16 degrees.
We have confirmed by making a wire bonding test module.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Thermal FEA simulations
(Geneva)
• Detailed FEA simulations ➡ thermal performance
3D model (ANSYS, Abaqus)
• Parameters under study:
power/chip
cooling temperature
convection/radiation (gas temperature)
thermal grease thickness
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Thermal test module
We have been investigating thermal property of module
with a thermal test module, in order to validate thermal
FEA simulations.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Super-Module
Insert modules into a frame: Super-module
• Super-module contains cooling piles, power cables, optical fibers
and monitoring cables.
2 proposals for module integration into cylinders:
• Lateral insertion (KEK): Installation of the Super-Modules, cylinder
by cylinder
• End-insertion (Geneva): Barrel structures can be assembled before
the Super-Modules are integrated.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Circuit Diagram of Hybrid
The hybrid is loaded with 20 FE ASICs (ABCN), each having 128 readout
channels.
The first hybrid was developed by Univ. of Liverpool. In order to shorten a
production period, several functions of hybrid were limited.
KEK hybrid provides the full specifications operation of ABCNext chips.
• redundancy operation
two sets of bus lines
bypass scheme for dead chip
• various powering schemes
individual powering for Vcc (2.2V) and Vdd (2.5V)
voltage regulator for Vcc
two types of shunt regulator for serial powering application
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Circuit Diagram of Hybrid
The hybrid is loaded with 20 FE ASICs (ABCN), each having 128 readout
channels.
The first hybrid was developed by Univ. of Liverpool. In order to shorten a
production period, several functions of hybrid were limited.
KEK hybrid provides the full specifications operation of ABCNext chips.
• redundancy operation
two sets of bus lines
bypass scheme for dead chip
• various powering schemes
individual powering for Vcc (2.2V) and Vdd (2.5V)
voltage regulator for Vcc
two types of shunt regulator for serial powering application
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Front-end ASIC
ABCNext front-end ASIC (250 nm IBM CMOS6 technology)
Binary architecture, 128 channels
Analog blocks:
Preamplifier, shaper, discriminator (differential threshold)
Individual threshold trimming correction per channel
Internal calibration circuit
Positive and negative signal polarities
Linear voltage regulator on-chip, shunt regulator
Digital blocks:
Pipeline memory length of 6.4 µs
Derandomizer buffer (42 events length)
Two-clocks schema to allow different readout rates
(40/80 MHz)
Block diagram of the ABCN
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Layout of Hybrid Layers
Layer 1 (front side)
Layer 2 (inner)
Layer 3 (inner)
Layer 4 (back side)
L1 and L2 include the main circuit patterns for ASICs with redundancy lines.
L3 and L4 are mainly for the power distribution and grounding, respectively.
To 01/10/2009
evaluate grounding
scheme, analog and digitalRD09,
ground
can be separated.
Y. Ikegami, KEK
Florence
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Hybrid design rule
Front side
136mm x 28mm
0.260
0.165
Back side
Hybrid after mounting FE chips, R C components
and a 0.8mm pitch miniature connector at the right end.
Min. Line Width
Min. Gap
Min. Via-hole
Min. Thr.-hole
0.1mm
0.09mm
0.1mmΦ
0.3mmΦ
Taiyo Industrial Co., LTD
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Hybrid construction
• The hybrid backed with a 400 um thick and 112 mm wide
carbon-carbon sheet is designed to bridge over the silicon
sensor avoiding any interference to the sensor surface.
• The carbon-carbon bridge having large heat conductivity of
670W/m/K transfers the generated heat to the heat sink located
at the legs of the bridge.
• The total weight (excluding electrical components) is 4.25 g,
having 0.00425 X0 equivalent radiation lengths.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Button Plating I
also called pads-only plating or spot plating,
limiting an area of the via- and through-hole plating
The total weight of bare FPC is 1.91g.
The weight considerably decreased to
1.91g from 3.09g by button plating.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Button Plating II
Our target for through-hole diameter is the
minimum of 0.3mmΦ (standard 0.6mmΦ).
We ordered 4 sheets (8 pieces/1sheet), as
first lot. We obtained one good flex circuit
out of 32.
A major problem is come form
misalignment of layer stacking.
We ordered one more sheet w/o button
plating.
We obtained
3 good
01/10/2009
Y. Ikegami,
KEK flex circuits.
Improvement by the maker has been
performed, we obtained 10 good flex
circuits in the second lot.
We can receive the stable supply of flex
circuits w/ button plating.
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DAQ system
We have two DAQ systems.
• Modified current SCT DAQ system
Reuse the current resources
However, the data transfer rate is limited to 40MHz.
• New NI DAQ system (Geneva)
NI PXI-6562
6 channels digital WF generator/analyzer
200/400 Mbps per channel SDR/DDR
LVDS signals, per-channel direction control
Software:
LabVIEW 8.6
configuration files through XML (+schema)
scripted generation and multi-record acquisition
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Electrical Tests Results I
Gain [mV/fC]
Gain [mV/fC]
Gain uniformity
Geneva
KEK
The average gain is about 100mV/fC.
Quite uniform distributions were obtained in two sites.
There was no difference by having button plating or not.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Electrical Tests Results II
ENC [e]
Geneva
ENC [e]
Uniformity of Noise (ENC)
KEK No.2
The average ENC is about 400e.
Quite uniform distributions were obtained in two sites.
There was no difference by having button plating or not.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Electrical Tests Results III
2500
KEK, 81uA
KEK, 140uA
KEK, 198uA
Jan, 81uA
Jan, 140uA
Jan, 198uA
Michal, 81uA
Michal, 140uA
Michal, 198uA
ENC [e]
2000
1500
1000
500
Detector capacitance
0
0
5
10
15
20
Cin [pF]
• In order to investigate a change of ENC with a detector capacitance, we
connected external capacitances with the input of amplifiers, and measured
ENC.
• The first stage of amplifier current was changed into 81uA (red), 140uA
(green) and 198uA (blue).
• ENC
measurements
were performed at three RD09,
sitesFlorence
independently and the
01/10/2009
Y. Ikegami, KEK
results were in agreement.
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Test Module Preparing
The characteristics of the readout ASIC are evaluated with
different length microstrip sensors connected to the input of the
ASIC.
Wire bonding is completed soon and noise study will be started.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Module Program
• Geneva and KEK produce 4 modules each
n-in-p sensors 10cm x 10cm
KEK hybrids (flex circuit x62)
ABCNext 250 nm chips
• Common design and close assembly procedures and jigs
• Main objectives:
prove functionality
mechanical precision not a primary target
focus on electrical/thermal performance
• Module test-box:
single and 4-modules test-boxes (Geneva)
• Irradiations
Module to be irradiated at CERN PS
comparison performance pre and post-irradiation
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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Summary
• We have fabricated a low-mass, high-density,
hybrid which provides the full functionality of
the ABCNext full chips.
• The weight of flex circuit considerably
decreased to 1.91g from 3.09g with button
plating.
• The electrical tests on the hybrid level are
mostly completed.
• The module tests are planned to start soon.
01/10/2009 Y. Ikegami, KEK
RD09, Florence
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