Download Integrated circuit for high-frequency ultrasound annular array

Integrated Circuit for High-Frequency Ultrasound Annular Array
James R. Talmanl, Steven L. Garverick2, Geoffrey R. Lockwood3
I
The Cleveland Clinic Foundation.
'
Case Westem Reserve University, Queens University
Abstract
An integrated circuit capable of focusing a high-frequency
ultrasound annular array is presented. It uses a novel unitdelay architecture to accomplish focusing of the array with a
single control voltage. System measurements for a 5-element
array indicate excellent pulse fidelity with a dynamic amplitude range of 60 dB at 50 MHz. This is the highest frequency
single-chip ultrasound beamformer that has been demonstrated to date.
Introduction
High-frequency ultrasound (10-100 MHz) is attractive because of its superior resolution for intra-vascular imaging of
the coronary arteries [I]. Single-element transducers have
been developed for this application but they have limited
depth of field [2]. The use of dynamically focused arrays in
high-frequency ultrasound applications has been limited due
to the need for high speed circuitry with lirge dynamic range.
For example, a conventional digital beamforming system
operating at 50 MHz would require A D converters with
high-resolution (12 bits) and high sampling rates (500 MS/s),
beyond the current state of the art [3].
Even if this technical challenge could be overcome, it would
still be necessary to attach multiple RF coaxial cables to the
miniature array. One solution to this problem is to multiplex
the array signals and perform off-chip synthetic-aperture focusing [4]. However, this method is susceptible to motion
artifacts when used in a moving catheter. Beamforming on
chip solves this problem, and has been demonstrated at IO
MHz using asynchronous sampling combined with an analog
FIFO [SI. However, the method is dificult to implement at
higher frequencies due to the need for accurate wideband
sample-and-hold circuits. Furthermore, the die area must be
small for insertion in a catheter and compatibility with the
miniature high-frequency array, on the order of I mm2.
The approach used in this paper addresses these problems by
delaying and adding the array signals on an analog integrated
circuit mounted adjacent to the array, thereby avoiding motion artifacts and eliminating the need for multiple RF cables.
Architecture and Design
Figure 1 shows the unit-delay architecture using identical
analog variable delay cells to accomplish focusing of a 5element.planar annular array. It is suitable for integration
because. it does not require predetermined absolute delays on
each channel. Rather, it exploits the excellent matching of
0-7803-7842-3l031$17.00 0 2003 IEEE
components available on an IC. In the configuration shown,
the array is focused at an axial distance ofz=az/(2ss), where
a is the radius of the central element of the array, s is the
speed of sound, and r is the delay of each block. Control
voltages allow adjustment of gain and delay.
----- ---- ---_
I
I
sum
vm
vm.,
---,-----1 a t e p t r d cinvit
v,
Vm."
Figure 1. Matehed-Cell focusing architecture for khanor1 planar annular array. VTcc adjusts preamplifier gdn, VGAINl
and VGA,N,
adjust gain.
and VDEuyadjusts delay. The solid dot indicates summalion.
A.
RC-CR Delay
A simplified schematic of a delay cell is shown in Figure 2.
The circuit is a first-order, fully-differential, all-pass filter.
For sinusoidal input voltage, e.g. v, = A cos(o I), the output
voltage is a delayed version of the input voltage, given by
v,
- 2 lan.'(wRC))
= A cos (01
For small values of o R C , e.g. nit3 or less, the delay is approximately independent of frequency and is equal to 2RC.
Thus, the phase response is approximately linear for delays
corresponding to a phase shift of 45 degrees or less (e.g. 2.5
ns at 50 MHz). The delay can he easily changed by varying
the value of R or C. To obtain longer delays, while maintaining linear phase response, each delay block in Figure 1 consists of a cascade of 7 RC-CR delay cells.
Figure 2. BuNerred RC-CR delay circuit.
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IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE
477
B.
Delay Cell
A schematic of the delay cell is shown in Figure 3, in which
all transistors are NMOS and the substrate is connected to the
negative power supply. Device dimensions are indicated in
units of lambda, which is equal to 0.2 micron.
Figure 3. Schematic of delay cell. All dimensions arc in units of lambda
(0.2 micron). Substrate is connected to nrgativc power mpply.
The input signal drives the differential amplifier formed by
MI-M4. The RC-CR circuit consists of M7 and M8 operating in triode, and capacitors C l and C2, constructed using
two poly layers. M5 and M6 are source followers with low
output impedance (150 Ohm), M9 and MI0 are used to vary
the gain of the delay cell, and MI l-Ml4 bias the differential
amplifier and source followers. The supply voltages are f 3V
and the delay cell draws 2 mA, divided equally between MIM2 and M5-M6. Signals from other channels are summed
into the delay cell in the form of differential current, as indicated by ii. Thick-oxide devices (150 angstrom) are distinguished from the standard devices (75 angstrom) by a thicker
gate electrode. All control devices are implemented with
thick-oxide devices for greater breakdown voltage and improved large-signal linearity. The -3 dB bandwidth of the
delay cell buffer (not including the RC-CR circuit) is 1.2
GHz. It would be extremely difficult to obtain this perfomance with an opamp having the same area.
amplifier. C l and C2 compensate the CMFB, which has a
low-frequency gain of 100 and -3 dB bandwidth equal to
approximately 300 kHz. MI 5-23 provide level shifting using
a delay cell with the gain control and delay circuits removed.
V-to4 conversion is accomplished by M24-M28, in which
M26 and M27 are biased at one-half the value of current carried by M28.
Figure 4. Schematic of prcnmplifler, level shifter, sod V-10-1 c~nvirter.
Substrate ir cooanted to negstiw power supply. N-well mnnraioni are
-to positive pawer supply.
Experimental Results
Figure 5 shows a photograph of the CMOS integrated circuit
that implements the architechxe shown in Figure 1. It was
fabricated using the TSMC 0.35-micron, double-poly, fourmetal process through the MOSIS facility at the University of
Southern California. The active area of the preamplifiers and
delay cells is approximately 0.5 mm2.
C. Preamplifier
Figure 4 shows a simplified schematic of the preamplifier,
including V-to4 conversion and associated circuitry. Substrate and well connections, omitted for clarity, are all connected to the negative and positive power supplies respectively. Bias voltages Vel, Ver. and Ve3 are provided by current mirrors that are not shown on the schematic. MI-M6
form a variable gain differential amplifier biased at 0.5 mA.
The gain can be adjusted from approximately 1 to IO by controlling the value of Vc. The overall gain-bandwidth product
of the amplifier is approximately 900 MHz. M7-MI4 provide common-mode feedback (CMFB) for the differential
Figure 5. Die photograph. Si is 2 mm by 2 mm.
478
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Figure 6 shows the experimental setup used to characterize
the response of one delay cell. The delay cell under test is
placed between two other delay cells in order to mimic the
source and load conditions present when it is used in a cascade of delay cells. RF source-follower buffers are included
on the IC to drive 50-ohm test equipment without suffering
excessive loss of signal. The circuit is driven by the swept
RF output from a network analyzer. A 1 :I RF transformer is
used to convert from differential to single-ended signals. By
displaying the ratio of input to output signals on the analyzer
the responses of the RF buffers, transformers, and external
cables are normalized out of the measurement, leaving only
the response of one delay cell. The loading of the delay cell
by the RF buffers adds some extra delay, but simulations indicate it is negligible.
A
MATCHED
CABLES
from an axial ultrasound point source. Interconnections are
kept the same on all 5 channels by using 5 identical cables.
Additional cables introduce differential delays between channels to emulate the signals from an ultrasound target. Three
sets of cables were made having values of T equal to 6 ns, 9.3
ns, and 12 ns It 20 ps. The length of the longest cable, corresponding to a delay of 48 ns, was IO m.
A
FI.IU.~W(YW
Figure 7. Amplihtdc and phase response of one delay cell with delay
q u a l to 2.4 ns. In both cases, the dashed curve rep-nb
the calculated
respore ofthe RC-CR circuit with pansitin. The measured and esleuhted amplitude responses are both normalid to 0 dB at 50 MHz The
0.4 m delay ofthe hufler b subtncted from the phase raponre.
Figure 6. Experimentalsehtp for measuringdelay cell characteristics
Figure 7 shows the measured amplitude and phase response
of one delay cell that was adjusted for a maximum delay of
2.4 ns. The dashed line indicates the theoretical frequency
response of an RC-CR circuit with C and R equal to 0.25 pF
and 4100 Ohms, respectively. These values are approximately optimum in terms of gain flatness for this value of
delay when parasitic effects due to load capacitance from MI
and M 2 (13 ff) and finite source impedance for M5 and M6
(150 Ohms) are taken into account. The agreement between
theory and experiment is excellent, indicating that the amplitude response is dominated by the RC-CR component of the
delay cell, i.e. the amplitude response of the buffer is negligible. The minimum measured delay of one delay cell is 0.86
ns. Simulations indicate that 0.4 ns is due to the buffer.
Therefore, the minimum delay of the RC-CR circuit is 0.46
ns.
A.
System Measurements
The experimental setup used to test the IC is shown in Figure
8. A broadband pulse centered at 50 MHz with 4 dB fractional bandwidth of approximately 25 % (44 MHz to 57
MHz) is used to emulate an ultrasound target. A power splitter is used to obtain 5 synchronous signals for the 5 inputs
"""
"-
I-,
Figure S. Experimental setup used for testing the IC.
Figure 9 shows a comparison of input and output pulses when
the value of T is adjusted to 12 ns, corresponding to a delay of
1.7 ns per delay cell. The amplitude of the pulse is 30 mVpp.
The solid line is the measured output pulse and the dashed
line is the measured input pulse, mathematically delayed and
scaled according to the values of small-signal delay and gain
of the circuit. The latter quantities are measured with a c
w
excitation at the center 6equency of the pulse. This procedure avoids errors due to subjective scaling and delaying of
the input pulse, thereby providing a fair comparison. Slight
widening of the output pulse is observed as a result of fmite
bandwidth in the delay cells, but the overall agreement is
excellent.
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479
For ideal focusing, the output amplitude with all 5 inputs present simultaneously should he equal to the sum of the 5 output amplitudes due to each channel taken separately. This
ideal focusing gain was measured at an extremely small input
signal level (ImVpp), and the extrapolated result is indicated
by the solid line in Figure 10. A series of input-output pulse
comparisons were made as in Figure 9 for all three sets of
cables and the results are displayed graphically in Figure 10.
50
1
1
’100
’150
1
200
of identical analog variable delay cells constructed from an
all-pass RC-CR circuit. The axial focusing range, which is
proportional to the ratio of maximum to minimum delay
available from one delay cell, is approximately one octave
with 85 % efficiency. This is the highest frequency singlechip ultrasound beamfonner that has been demonstrated to
date.
I
3w
250
Time (n.1
Figure 9. Input-output pulse comparison for Srhannel lofusing experiment when % is equal to 12 ns.
At minimum delay (T equal to 6 ns) and small signal levels
the 5 channels are summed together by the IC with essentially
ideal focusing gain. The output saturates at large signal levels primarily due to the RC-CR circuits in the last r block in
Figure 1, where the signal is largest. The output 1-dB compression amplitude is 750 mVpp, which is 60 dB larger than
the noise voltage present on the output of the IC. At the largest value of delay ( r equal to 12 ns) the focusing gain is approximately 85 % of the ideal focusing gain, as indicated by
the initial slope of the response.
The discrepancy in output amplitude at large delay is due to
imperfect matching between delay cells, resulting in destmctive interference between channels. However, the difference
between the input and output pulses is slight, as indicated in
Figure 9. Mismatches between delay cells are probably due
to differences in threshold voltage and DC offsets. These
errors represent a larger fraction of the control voltage at larger delays, where smaller control voltages are used, resulting
‘in poorer matching of delay cells. Thus, the maximum delay
available from the circuit is actually limited by the matching
between delay cells rather than by phase distortion considerations. Matching’could be improved significantly by using ac
coupling and bener layout techniques.
Conclusions
An integrated-circuit suitable for focusing a high-frequency
ultrasound annular array operating at 50 MHz has been demonstrated. The focusing architecture consists of a collection
480
w m g . Imp*
0h”r
(vpp,
Figure 10. Input-output pule comparison for 5 s h m n e l focusing experiment when % is equal lo 6 ns, 9.3 ns, and 12 ns. The solid PUN^
repmrnts ideal focusing. The dashdot C U N ~repmerits a SPICE dmQlation afthe ioput-output response when is q u a l to 12 os.
References
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