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EMCal project
TRU (Trigger Region Unit)
status Sept ‘08
Norbert Novitzky
8/3/2017
1
Outline
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EmCal
– General overview
Trigger
– Requirements ( design goals, key parameters ):
– Schematics ( tower to CTP )
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Trigger mapping
TRU board
Trigger in TRU
L0 latency
STU board
Hierarchical trigger fro EMCal
Our participation
Status
– Tests, what are done
– Remaining tasks
– Time schedule
Future activities
8/3/2017
2
EMCal in ALICE
Opt. fibers
Back plate
Acceptance
EMCal
PHOS
DF
110°
100°
Dh
1.4
0.24
Rinteraction
4.3m
4.6m
Led-scintillator
1/3 super module: 48x8 (384) towers.
Characteristic
Value
Moliere radius
3.2cm
# Towers
12672
Ambient temperature
18°
Light yield (APD)
3.3e/MeV
Preamplifiers
1V/pC, 15ns
Shaper
200ns, G-2
Dynamic lin. Range
14 bit
8/3/2017
1 (super) module
EMCal
PHOS
Modules
10
5
Towers
1152
3584
FEE
36
112
TRU
3
8
STU/TOR
(for all modules)
1
1
Tables are showing general
information about the EMCal
detector in ALICE. Because
of the similarities with PHOS
detector, some information
are compared with the PHOS
detector.
3
The EMCAL will provide L0 and L1 trigger signals.
The L0 must be provided within 800ns to CTP, where it is decided with other
detectors. The main calculation for L0 is don in TRU level.
The L1 is decided in STU. It is more complicated calculation, but first it is needed to
transfer the data from TRUs. This procedure start only when the system
receive the L0 from CTP (via RCU boards).
Other L0
detectors
29xTRU
2x2 data 135ns
12x
FEE
12x
FEE
t=0
[collision] 12x
FEE
TRU
STU
TRU
TRU
RCU
8/3/2017
L0 signal
600ns
Data
Start of data
1400ns
L0 from CTP
1200ns
L0 800ns
L1 calculation
L1 6200ns
End of data
1915ns
RCU
CTP
(central
trigger
processor)
L0 from CTP
1200ns
4
This figure shows the
path for L0 and L1
trigger signals from
super modules to the
CTP (central trigger
processor)
High-speed link
Ethernet cable
CTP
Level-0
Level-1-L
Level-1-M
Level-1-H
JET
Vo
LTU
multiplicity
TTC
5
•The L0 is generated in TRU
(Trigger Region Unit)
•The L1 is generated in STU
(Summary Trigger Unit)
Level-1 global decisions in STU f(nxn)
STU
High-speed link
Ethernet cable
16 x TRU
16 x TRU
Max 12 m
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
TRU
1 Super module
192 x FEE
Level-0
local-decisions in TRU (4x4)>x
8/3/2017
Max 12 m
TRU
TRU
TRU
TRU
TRU
TRU
HLT
192 x FEE
Fake Altro trigger data
RCU
DAQ5
In this figure we can follow the signal from towers in super module, through the
front-end electronics, TRU module until it reach the STU.
1x STU
STU
Summary
Trigger
32 x TRU
384 x FEE
TRU Trigger region
8 x 48 towers = 384
1 TRU =
8 x 12 (2x2) = 96 signals Analogue FOR cables
96 (2x2)
1 FEE card:
32 APD in 8 towers
8 x analogue OR 2x2
from 12 FEE
1 TRU =12 FEE = 1 SM in z
~5-30cm
Max ~12m
FPGA
FPGA
Virtex-5
Virtex-5
4x4 groups
1 FEE
1 FEE
x (2x2)
18xFEE
8
(2x2)
8 x (2x2)
96 ADC
24 8 16 0
f
z
100 ns
100
nsns
100
12 bit @40MHz
8 x (2x2) analogue
48 x 8 towers
3 1
1 5
Towers
2x2
1 RCU branch A
Level-1Level-1
JET High pT
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23 7
CSP
numbering
1 FEE = 32 inputs,
8 output for TRU
1..9
10,11,12
1 RCU branch B
Level-0
RCU
1 RCU partition:
6
TRU board
Power regulators
LVDS High speed
control link (to
STU)
Prom
10 Test
pins
LVDS
bus
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Inputs from FEE – 112 channels
(but only 96 will be in use)
GTL bus
7
Trigger (TRU)
Hierarchy of the trigger in EMCal:
• The 2x2 sum of the towers from FEE->TRU (112 channels as input in one TRU)
• In TRU we create an other 2x2 sum of input channels, what mean now we have
4x4 sum for towers. Then we apply a digital threshold. (69 groups)
1 Tower
2x2
2x2 = 1 TRU chan.
4x4 for trigger
• The data from TRUs go to STU.
 L0: create an OR from every TRU (quick process)
 L1 : more complicated, using every TRU data, but it is done in STU
Requirements
L0
800 ns
8/3/2017
L1
6.2 ms
L2
88 ms
8
FEE
TRU
ADC
305 ns
135 ns
Bx t=0
580 ns
345 ns
600ns
640 ns
Level-0 Algorithm
40 MHz
40 MHz
Reading the data,
analog sum (2x2)
Convert the
incoming signal De-serialize the
to a digital signal
data
(12 bit)
170ns
STU
69 parallel
processes
Xilinx Virtex-5
Process
Time
Data in FEE
135ns
ADC process
170ns
De-serialize
40ns
L0 Algorithm in TRU
235ns
STU calculation (for L0)
40ns
Cables
~178ns
8/3/2017
max. 800 ns
Maximum time
for calculation 235 ns
CTP
~ 5 m = 22 ns
~ 35 m = 154 ns
20 MHz NRZ Trigger
• Every 4x4 calculation will run in parallel
processes in the FPGA.
• It creates the 4x4 group and check, if the
energy reach a certain threshold or not.
Every 4x4 group can have different threshold.
• The limit to reach the CTP is 800ns. The
table shows, how much time is needed to the
sub-processes and how much time is left for
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the calculation
STU (Summary Trigger Unit)
T38-B39
T0-B1
V0 interface
DDL interface
DCS interface
L0 in
TTCRq
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T0-B1 = Top is input 0, Bottom is input 1
4 TRU inputs
T34-B35
T32-B33
T30-B31
T28-B29
T26-B27
T24-B25
T22-B23
T20-B21
T18-B19
T16-B17
T12-B13
T10-B11
T8-B9
T6-B7
T14-B15
T36-B37
T2-B3
Trigger
outputs
4 TRU inputs
T4-B5
32 TRU inputs
STU
The STU has 40 input (for EMCal we will use 32) of high-speed link.
The board also contain an FPGA (Virtex-5, same what we have on TRU)
For generating the L0 signal it will create an OR from every TRU. If one has an
L0 signal, then it will send it to CTP.
After that it will create also a L1 trigger signal :
• L1 Gamma (is the same procedure, like in TRU 4x4 regions)
• Low pT jets
• Medium pT jets
• High pT jets
Below subregion delimitation, 4x4 fast OR  8x8=64 towers
Row/ 0
col
1
2
3
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92
1
5
9
13 17 21 25 29 33 37 41 45 49 53 57 61 65 69 73 77 81 85 89 93
2
6
10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 70 74 78 82 86 90 94
3
7
11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 71 75 79 83 87 91 95
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Numbers are the readout order and not the ADC channel number
Total: 204 subregions
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FPGA program (basic)
There are two main languages in use: VHDL and Verilog
The basic component of the program is the CLOCK. Every calculation, every
signal is based on this clock. (in TRU it is a 40MHz clock, or we will use the LHC
clock ~40.08 MHz)
The next is to match the pinout map with the correct chip pins. Every FPGA has
different pinout map (we are using Xilinx Virtex-5 LX110 BGA1153).
After that the compilation can find the correct way. If you miss the pin, you will not
get anything.
The pinouts for
our FPGA (what
is in use)
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FPGA program (basic)
The start of the program is definition of the ports.
We need to define the signal, what we will use:
• IN or OUT signal
• The signal is std_logic (standard logic). We
can also define it as a vector
State mashine
A very useful tool in hardware
language. Here as a very simple
example is a street-light.
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Our participation in TRU
1. The production of 38 TRU boards. (including 2 prototypes)
1. First test of the TRU prototypes before the full production.
(Dong, Jo, Hans, Norbert)
a) First power up
b) Start to program the FPGA (also Prom)
c) Test pattern for ADCs
d) Test of High speed link and LVDS control (with Olivier)
e) 2 remaining problem before full production:
I. GTL bus communication
II. Actel refreshing (not necessary)
8/3/2017
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Test, what we had done
• First power up of the board (Problem 1)
 All of the starting problems was solved
• The power regulators gave the right values (Problem 2)
 Some small changes must be made
• Programming the FPGA via Xilinx cable: (Problem 3)
 Directly – tested
 From the flash (prom):
1. Serial programming (~15 seconds)
2. Parallel programming (~2-3 seconds)
• The test pins are working fine, the LEDs are also ok.
• Fake Altro test
 The readout of the trigger data with the GTL bus
Conclusion
The design of the TRU board is good, there is no need to change it.
Ready for full production.
8/3/2017
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Test of ADCs
The ADCs do the conversion from analog signal to digital (12 bit) signal. After
that the FPGA can handle the data.
The ADC is working with 40MHz, it can sample the incoming data every 25ns.
After that it provides 12 bit digital signal from data.
Sampling points (every 25ns)
40MHz – frame clock
It’s the start and end of the
8/3/2017
data.
240 MHz clock – data clock
In every rising and falling edge is one bit
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Test of ADCs
First the testing of the FPGA features. For testing we can use:
• Logic Analyzer (10 test pins = 10 channels)
• ChipScope – built-in logic analyzer inside FPGA
First thing to do: test the ADCs(12 bits in 8 channels)
The part of the program initializes all the ADCs. You need to write to register
few data to initialize the completely.
After that we setup the test patterns:
• Sync: 101010101010 (~240MHz clock)
• Deskew: 111111000000 (~40MHz clock)
40MHz clock – frame clock
240MHz clock – data clock
ADCs 8 channels = 1 chip
Deskew test pattern data
8/3/2017
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TRU-STU test
First test with slow control:
(2 inputs, 2 outputs links)
We had to solve some issues with
the correct pins in FPGA. We solved
it. As far as I understood, it will be
not used in final setup.
They want to use the black-plane to
operate with the board.
Second test was the high-speed link.
(1 input (40MHz clock from STU, later the
LHC clock), 3 output links)
We were sending 450 words in packet,
instead of 96. We solved also some lastminute issues with program. 4 inputs on
STU were tested, worked properly. For
further test more time is needed:
• Test all inputs (compilation time
increases)
• Test with few TRU at once.
(synchronization)
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Short term plan
• Actel refresh – it protects the FPGA from SUE (single upset events)
 Dong is working on that now
 This test will be good to be done, but not necessary.
Long term plan
• After full test of the prototype, we need to start the full production. Ordering the
missing parts, sending it to the companies.
• Further test with STU-TRU setup.
• Writing the final FPGA code for the trigger (with Jo, and maybe Dong)
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Orders
Resistors and capacitors: ~1000 CHF
Connectors:
~1000 CHF
Chips:
~2000 CHF
ADCs:
• SILICA AVNET (FR): 23'964 CHF
• AVNET EMG (CH): 24’311 CHF
• DIGI-KEY (US):
33’538 CHF
• SPOERLE (CH):
34’730 CHF
delivery: about 16/02/09
delivery: about 09/02/09
delivery: from stock (to be
checked before ordering)
delivery: within 12 weeks
(about 12/02/09)
After the components we need to order the boards (2 are already at Cern), and
the mounting. This I don’t know how much will cost.
8/3/2017
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Backup
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First power up of board (Problem 1)
The power supply values needed (INPUT values):
• 4.0V @ 3.3 A
• 4.2V @ 3.5 A
• 3.3V @ 3.0 A
If we are not using
the backplane, to
turn on the board
we need to put a
jumper on ST1.
At first power up we discovered a capacitor
(C126) was mounted inversed and making to
short circuit. The silk screen shows the plus
sign on the wrong side. To be corrected in the
mounting files.
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Testing the volgates (Problem 2)
On the board there are several voltage regulators:
Digital Power
ADC powers (must be enable from FPGA):
• Q2 –
1.0V output
• IC31 – 3.3V output
• Q1 –
2.5V output
• IC32 – 1.8V output
• IC33 – 3.3V output
• Q3 –
2.5V output
• Reg1 – 2.5V output
The Q2 must be corrected:
•The TPS74410 is switched to TPS74401
•The R68 and R64 must be switched
•The C222 need to be changed to 100pF
•The bias pin 6 should be connected to 3.3V
IC32:
•Same TPS7701
•R81 and R80 must be switched
•The pin 6 should be connected to 3.3V
•The C227 need to be changed to
8/3/2017
100pF
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More setup for TRUs (Problem 3)
There are several options how to use the TRU. The main switch for programming the
FPGA is the SW1:
Here the R242 and R241 should be
removed.
This switch determine how should
be the FPGA programmed (Prom –
parallel or serial, Actel…)
The configuration on
silkscreen is not correct for
the parallel programming.
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Programming the FPGA (Problem 3)
The R124 must be removed to
be able to program the FPGA
from PROM or ACTEL. It is an
active low signal, should be
connected to the ground
The R71 must be
removed for Actel
programming (not yet
tried)
To program the FPGA from PROM:
Remove the R22
(C240 is not needed)
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To disable the clock
CLKOUT R18 must be
removed.
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