Download VLSI Circuit Design

Introduction to VLSI Circuit Design
Problem set #3
(Due date: Nov. 10, 2008(中午12pm))
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1. A method for reducing interconnection resistance in the polysilicon lines is to use
silicide material deposited on top to form polycide. This process can reduce the
nominal sheet resistance from 20 to 2 or even less. For the same purpose,
silicide material is also deposited on top of source of silicide can be achieved on
polysilicon gates and source and drain regions of MOS transistors. Discuss how
such deposition can be achieved without causing electrical shorts between the gate
and source or drain of an individual transistor.
2. Exercises 3.7 on page 155
3. Exercises 3.8 on page 155
4. Explain why substrate and well contacts are important in CMOS.
VDD
5. The following figure presents a simple CMOS layout (assuming p-well process on
n-substrate).
(a). Study the layout, and from it produce a circuit diagram.
(b). Explain the nature and purpose of the circuit.
(c). Draw the cross section along the a-a’ line (
).
n+
m
as
p+ active
k
output
A
a’
a
VS
S
p+
m
as
k
B
C