Download Modeling Techniques for substrate noise coupling

Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
Analysis of Modeling Techniques for Substrate Noise Coupling
By Vincent Mui
Abstract
This paper presents an overview and comparison of several prevalent techniques for substrate noise
coupling in integrated circuits. A brief review of substrate noise knowledge and its effect is described to
give the reader some ideas on the importance of the techniques for substrate noise coupling. The earliest
technique, Finite Difference Mesh Method is presented. Three other current techniques are also analyzed.
Eventually, some techniques for the noise reduction are proposed, and the future trends of substrate noise
coupling techniques are discussed.
I.
Introduction
As the complexity of mixed digital-analog designs increases, and the area of the current technologies
decreases, substrate noise coupling in integrated circuits becomes a significant consideration in the design.
Since the substrate noise between the on-chip analog and digital circuits can corrupt low-level analog
signals, it can impair the performance of both analog and digital signals in the integrated circuit. In order to
determine the amount of coupling between the sensitive nodes and noisy nodes, modeling techniques for
substrate noise coupling should be generated. During the last decade, several substrate noise coupling
techniques have been developed. There is no perfect modeling technique existing in the IC design world.
Therefore it is good to analyze and compare the differences and trade-offs between them.
In this paper, the source of substrate noise is addressed, and the modeling techniques are discussed and
analyzed. Section II provides a brief background of the substrate noise and its effect on how to influence
the performance of digital circuits and analog circuits. Sections III to VI introduce the properties of
modeling techniques for substrate noise coupling, including the Finite Difference Mesh method, Boundary
Element method, Preprocessing Analytical method and Simple Resistive Marcomodel method. Section VII
summaries the trade-off and differences between the modeling techniques in clear tabular format. Section
VIII suggests some guidelines and design techniques for the substrate noise coupling reduction. Section IX
draws a conclusion and discusses the future flows of the substrate coupling.
II.
Substrate Noise Fundamentals
A. Parasitic Effect of Substrate [3]
The parasitic material of substrate influences the behavior of a circuit design. For example, the
capacitance of the substrate delays signal transmissions to different locations of the device. The
current flowing to the ground through the substrate leaves a voltage drop, which affects the device
operation.
In addition, the substrate is not a perfect isolation between devices, leading to
unwanted “cross-talk” in integrated circuits.
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
As illustrated in Fig.1, a parasitic RLC circuit on a capacitor is introduced when the substrate is
connected with bonding wires. This affects integrated devices in the circuit. For instance, a
typical bonding inductance of 4nH together with 10pF capacitance has a resonant frequency of
800MHz, which is a source of instabilities and oscillations.
Physical Structure
Polysilicon
Equivalent RCL Model
Bonding Wire
Oxide
Diffusion
(Substrate Contact)
Substrate
Fig.1: Parasitic effect on a capacitor made of two polysilicon layers
In the common silicon substrate, the phenomenon of the cross-talk occurs if a sensitive cell, like analog
portions of the integrated circuits, is presented along this parasitic path. It is perturbed by the noisy signal,
so that the substrate is used as a parasitic return path for signals carrying relevant information shown in Fig.
2. Also, the cross-talk problem arises in any substrate coupled regions such as the collector of an npn
transistor or a bonding pad changes state.
Noise Source
Oxide
Forward signal path
Substrate
Contact
Metal
V(f)
Well
Signal
Receiver
Signal
Source
Cws
Parasitic Path to AC Ground
Parasitic Return Path
Perturbed
Cell
f = freq. of noise
P Substrate
Substrate
Fig. 2: Substrate as a parasitic return path
Fig. 3: Substrate as a parasitic path to AC ground
Furthermore, the substrate can also drive AC noise to the ground when the least resistive path is followed
and the noise flow is determined by the distribution of substrate contacts to AC ground. In Fig.3, the
presence of a backside contact produces a vertical current.
Besides this, there are lots of parasitic
capacitances existing at every node in a circuit. Cws is the capacitance between the substrate and a well
which can provide a channel for noise to go into the substrate. When the well contact is connected to a
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
digital supply, noise on the supply may be coupled to the substrate through the junction capacitance C ws.
Consequently, the substrate behaves as a noise vehicle and channel.
B. Substrate Noise Coupling Effects in Mixed-Signal Integrated Circuits [4]
The lesser power consumption and lower cost of single chip solutions motivates technology improvements
in mixed signal (analog and digital) designs.
However, the mixed signal design is characteristically
plagued by coupling noise problems in the common substrate. As depicted in Fig.4, being capacitively
coupled to the substrate through junction capacitances and interconnected bonding pad capacitances, the
digital switching node causes fluctuations in the underlying voltage. Thus, a substrate current pulse flows
between the surrounding substrate contacts and the switching node.
Analog
Digital
R
Vg
Vin
Cdigit_sub
Noise Coupling
Substrate
Fig.4: The Substrate Noise Coupling Problem
Even worse, variations in the backgate potential voltage of sensitive transistors in the analog portion will
happen if the fluctuations spread through the common substrate. The variations in the backgate voltage
induce noise spikes in its drain current and voltage because of the junction capacitances and the body effect
of the sensitive transistors in the analog portion. It can impair the performance of the integrated circuit, and
even totally corrupt the functionality of the system. Recently, substrate noise has begun to plague fully
digital circuits due to further advances in chip miniaturization and innovative circuit design. The effects of
substrate noise may cause critical path delays, thus other paths may become critical as a result of the
increase in generalized delay. Localized delay degradation may cause clock skews and glitches.
As a result, it is very important to develop some methodologies and modeling techniques for substrate noise
coupling in both pre-layout and post-layout stages in order to determine the amount of coupling required
between the sensitive nodes and noisy nodes. There are several current techniques to simplify on the
physical equations and allow for efficient substrate coupling analysis when circuit simulators or other
general-purpose simulators are used.
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
Modeling Techniques for Substrate Noise Coupling (Section III and VI)
III.
Finite Difference Mesh Method [4]
The Finite Difference Mesh Method is the earliest technique developed for substrate noise coupling. It
employs the discretization technique to assume the substrate as layers of uniformly a doped semi-conductor
of varying doping density outside the diffusion regions. As illustrated in Fig.5a, using a finite difference
operator, nodes are defined across the entire substrate volume. The electric field vector between adjacent
nodes is also approximated. Discretizing on the substrate volume results in a mesh circuit consisting of
nodes interconnected by branches of capacitors and resistors in parallel, shown in Fig.5b, the values of
which are determined from process parameters - dielectric constant, sheet resistivity or doping density.
Node j
Node j
Wij
dij
Node i
hij
Node i
Cij
Gij
Figure 5a: A control volume in the box integration
Figure 5b: Capacitances and Resistances around a
technique.
mesh node in the electrical substrate mesh.
Ignoring magnetic fields and using the identity   (xa) = 0, Maxwell’s equations can be written as:
J 
1

(  E )  
Eij 
where
D
=0
t
where D =
 E ; and
J=

(  E )  0
t
1
E ; and it gives,

(1)
Vi  V j
(2)
hij
 is the sheet resistivity,  is the dielectric constant, and E is the electric field intensity vector. In
this stage, a simple box integration technique should be utilized to solve the above equation, since the
substrate is spatially discretized. From Gauss’ law, it gives
 E  k
and
k

Si
(3)
'

where
 ' is the charge density of the material. From the divergence theorem,
EdS   kd
(4)
i
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Analysis of Modeling Techniques for Substrate Noise Coupling
where Si is the surface area of the cube and
ECE1352 Analog IC I
i is the volume of the cube shown in Fig.5a. The left hand
side of the equation (4) can be approximated as

Si
EdS 
E
ij
 S ij   Eij  wij d ij  k   i
j
(5)
j
Modifying the equation (3) and (4), it provides
E  k 
1
i
E
ij
 wij d ij
(6)
j
Substituting the equation (6) and (2) into (1), it results
[ G
ij
(Vi  V j )
 Cij (
j
where Gij = (wij x dij) /


Vi  V j ) ]  0
t
t
 hij and Cij =  (wij x dij) / hij as modeled with RC circuit elements shown in Fig.
5b. The above result shows that the areas of contact and diffusion are represented as equipotential regions
in the resulting three-dimensional RC mesh and treated as ports in the multiport network.
For 3D substrate noise coupling simulations, a marcomodeling can be used, and an admittance parameter
matrix Y(s) of a linear circuit should be formed as follows:
......
 y11 ( s ) y12 ( s )
 y (s) y (s)
......
22
 21
......
......
......

......
......
......
......
......
......

......
 yn1 ( s ) yn 2 ( s )
y1n ( s ) 
y2 n ( s ) 
...... 

...... 
...... 

ynn ( s ) 
V1 ( s ) 
V ( s ) 
 2 










Vn ( s )

i1 ( s ) 
i ( s ) 
2 










in ( s )
In order to solve the above matrix Y(s), Asymptotic Waveform Evaluation (AWE) should be utilized
because AWE can use a few dominant zeros and poles to efficiently approximate the time domain response
of large liner circuits.
Based on the Reference [4], each AWE approximation y ij(s) consists of a partial
fraction expansion:
yij ( s ) 
q
kij,l
s p
l 1
 d ij
ij ,l
where dij is any direct coupling between the input and output, p ij is complex poles, kij is complex zeros, and
q is the number of poles in the approximation. This macromodeling technique can be applied to simulate
noise coupling in VLSI chip, instead of conventional device circuit simulators.
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
This Finite Difference Mesh Method’s solution accuracy depends highly on the resolution of discretization.
In addition, it is necessary to use fine grids to accurately approximate the non-linearity of the electric field
intensity. In such two cases, the size of the resulting finite difference mesh matrix, with an increasing
number of ports and fine grids, becomes too large to solve. There are three suggested methods for RC
model network reduction:
1) use a moment-matching method to reduce an RC mesh model,
2) use a coarse grids to reduce the overall number of grids,
3) ignore substrate capacitances, and consider the substrate as a purely resistive mesh.
Even though the above methods may reduce RC matrix, the finite difference method generally has a huge
sparse matrix because it consists of discretzing the entire substrate and applying different equations at each
node, due to the usage of a purely numerical calculation technique. Consequently, the Finite Difference
Mesh method can be utilized to determine reduced order substrate models.
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
IV. Boundary Element Methods [5], [6]
Dr. R. Gharpurey and Dr. R. G. Meyer have developed the boundary element methods using the Green’s
function for efficient calculation of substrate macromodels in the last decade. The marcomodels can be
included in circuit simulators such as SPICE, in order to predict the effects of substrate noise coupling and
to allow optimization of the layout to minimize these effects.
For the electrostatic case, capacitance Cij between contacts i and j are defined as the ratio of the charge on
contact j to the potential of contact i, or Cij = Qj /  . By Stokes’ Theorem,
Cij 
1

 E  nˆ ds
S
where E is the electric field in the medium and
n̂ is the unit outward normal vector to the surface S.
Similarly, the resistance between contacts is defined as
1


1 i
    E  nˆ ds   
 Q j
s


1
ij
Rij  Y
where  is the medium conductivity. In both the capacitive and resistive cases, the potential satisfies the
Laplace equation. Thus, they can be interchanged freely. Moreover, substrate susceptance is typically
much smaller than the conductance below 5GHz.
Therefore, it may be ignored and all substrate
impedances may be considered as purely resistances. First of all, the Poisson’s equation is used:


 2  
(7)
where  is the electrostatic potential. For the resistive substrate case, the above Poisson’s equation can be
reduced to
 2 = 0. Applying the Green’s function to (7) gives the electrostatic potential at an
observation point r, due to a unit current density injected at a source point, r’, defined as
 (r )    (r ' )G (r , r ' )d 3 r '
(8)
V
where V is the chip’s volume region, as well as G(r, r’) is the Green’s function satisfying the boundary
conditions of the substrate. The electrostatic potential of a contact is calculated as the result of averaging
all internal contact partitions. Based on (8), the potential of the contact i can be obtained as
i 
1
Vi 
Vi

Vj
(9)
 j Gdv j dvi
where Vi and Vj are the volumes of contacts i and j respectively, and pj is charge distribution on j.
pj = Qj / Vj is chosen over j, and substitutes it into (9), and it gives,
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Analysis of Modeling Techniques for Substrate Noise Coupling
i 
Qj
ViV j
 
Vi
Vj
ECE1352 Analog IC I
Gdv j dvi
(10)
By considering (10) for all combinations of contacts and the solution to (8) for each contact pair, the
following coefficient-of-potential matrix equation [P] can be generated:
  PQ
Q  c
and
(11)
where c = P-1 is called coefficient of induction matrix. For a contact i, the capacitance to ground Ci and all
mutual capacitances Cij are defined as
N
Ci   cij
where Cij = cij,
j 1
and N is the size of matrix c.
Based on the above fundamental of the boundary’s conditions, the
electrostatic Green’s function in a multi-layer substrate can be derived.
When there are multiple substrate layers, each with a different conductivity, the Green’s function can be
applied to the layered-media boundary conditions since these Green’s functions can include any effects due
to possibly finite extent of the substrate and vertically-varying conductivity.
Z
 constant
b
Y
Z=0
Z= -dN
p = (x’, y’, z’)
q = (x, y, z)
X
Y
a1, b2
a2, b2
a1, b1
Contact 1
a2, b1
a3,b4
a4,b4
X
:
N
:
:
Z= -d1
d
1
a3,b3
Contact 2
Z= -d
0
a4,b3
1
a
Fig. 6b: Two equipotential contact coordinates
on the surface of the substrate
=0
Fig. 6a: Geometry of multi-layer doping substrate
As depicted in Fig. 6a, the substrate is formatted as a dielectric and is characterized by several layers of
varying dielectric constants k, where k is the layer number in the substrate. Assume that the bottom of the
substrate is in contact with an ideal ground-plane and the substrate is purely resistive and lossy-dielectric.
A typical substrate example with two surface contacts is shown in Fig.6b, including the point charge q = (x,
y, z = 0), and observation point p = (x’, y’, z’ = 0), with dielectric permittivity N. The Green’s function
involves an infinite series of sinusoidal functions


G (r , r ' )  G0 | zz '0   f mn C mn cos(
m 0 n 0
mx
mx'
ny
ny '
) cos(
) cos(
) cos(
)
a
a
b
b
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(12)
Analysis of Modeling Techniques for Substrate Noise Coupling
where
f mn is given by
f mn 
Also
ECE1352 Analog IC I
1  N tanh(  mn d )  N
ab N  N  N tanh(  mn d )
(13)
 mn is given by  mn  (m / a) 2  (n / b) 2
.
Table 1. The values of the parameters Cmn in (12) based on different conditions
Parameters
Values
Conditions
Cmn
0
m=n=0
Cmn
2
m = 0 or n = 0, but m  n
Cmn
4
m, n > 0
According to the above relationship,
 N and N
2
  k  ( k 1 /  k )   k
   
 k  (1   k 1 /  k ) k
where
 k = tanh(  mn x (d – dk)), k
can be derived from the following equation:
( k 1 /  k  1) k
   k 1 


1  ( k 1 /  k  1) k2  k 1 
= 0,
 k = 1.0, and k [1, N].
(14)
For m = n = 0 at the surface, it gives
G = (1/abN) x (N / N)
(15)
where
0    k 1 
  k  ( k 1 /  k )
   ( /   1)d 1   
k
 k   k 1 k
  k 1 
when
k = d,  k = 1.0, and k [1, N].
Consequently, all the parameters in (12) can be solved. From (12), a further expression can be derived for
the average potential at contact i due to the charge on contact j:
i 
Qj
Si S j
 
Si
Sj
G ( s j , si )ds j dsi ,
Using the relationship in (11), it gives
 ij 
i
Qj

1
Si S j
 
Si
Sj
G ( s j , si )ds j dsi
(16)
where Si and Sj are the surface areas of the contact i and j respectively. pij is the entry of matrix P.
Substituting (12) and (15) into (16) and integrating, an explicit formula for pij can be obtained:
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Analysis of Modeling Techniques for Substrate Noise Coupling
N

ECE1352 Analog IC I

a 2 b 2 f mn C mn
 ij 
 
(ab N  N ) m 0 n 0 m 2 n 2 4
[sin( m
a2
x
[sin( m
b2
x
a
b
)  sin( m
a1
)] [sin( m
a
(a 2  a1 )( a 4  a3 )
)  sin( m
b1
)] [sin( m
b
(b2  b1 )(b4  b3 )
a4
b4
a
b
)  sin( m
)  sin( m
a3
b3
a
b
)
(17)
)
where (a1, a2) and (b1, b2) are the x- and y-coordinate of contact i and (a3, a4) and (a3, a4) are the x- and ycoordinate of contact j shown on the Fig. 6b. Modifying the second term of (17), it shows:


 k
m 0 n 0
where kmn =
mn
cos(m
a1, 2  a3, 4
a
) cos(m
b1, 2  b3, 4
b
)
(18)
a 2 b 2 f mn C mn
. Furthermore, the contact coordinates, (a1, a2) and (b1, b2), can be substituted
m 2 n 2 4
by the substrate dimensions with ratios of integers p, q, and (18) becomes
P 1 Q 1
K pq   k mn cos(m
m 0 n 0
p
q
) cos( m )
P
Q
(19)
When the substrate dimensions and the ratios of the contact coordinates are integral ratios, the twodimensional discrete cosine transform (DCT) of a series k mn can be used to compute (19). The DCT can be
calculated very efficiently by the use of the fast Fourier transform. In addition, the DCT needs to be
derived only once for a given substrate structure since the value of kmn is solely dependent on the properties
of the substrate in z-direction. As a result, the calculation of pij only requires a simple DCT, and only
matrix P needs to be calculated and inverted. [7]
The major advantage of the Boundary Element Method is that it is not dependent on discretization, which
differs from the Finite Difference Mesh Method. This method dramatically reduces the size of the matrix
to be solved, because it is limited by the fact that the impedance matrix is inverted, and P is fully dense.
Moreover, the speed of this technique is several times faster than techniques using a purely numerical
approach, and the matrix P can be computed to high accuracy by choosing large P and Q, without a major
penalty in set-up time. The Boundary Element Method can offer results that are within 10% of the actual
answer, even though it is erroneous to assume that a port has a constant current density across it.
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Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
V. Preprocessing Analytical Method [8]
The previous two substrate coupling techniques, the Finite Difference Mesh Method and Boundary
Element Method can only be utilized after layout extraction and do not provide a priori insight to the
designer. The following two methods, the Preprocessing Analytical Method, and Simple Resistive Method,
can provide some insights to circuit designers in the early stage of design.
In a pre-processing stage, precomputed z parameters are used to develop a preprocessing analytical method
for substrate noise coupling. This approach is then used in an extraction stage to find out point-to-point
impedances. First of all, three assumptions are made. Current density across ports is uniform, ports are
equipotential, and the effects of chip edge are ignored. As deprived in Fig.7a, two square ports are on top
of the substrate separated by a distance, d. Characterizing the electrical interaction, the matrix equation
between two ports is given as follows:
 zii

 z ji
zij 

z jj 
ii 
i 
 j

vi 
v 
 j
where zii is the potential observed at point i when a unit current is injected into point i, while point j is
floating due to zero current. zjj is the potential at point j due to a unit current injected at point j. z ij = zji is
the potential at one point when a unit current is injected at the other. z ii and zjj are constant because of
ignoring the effects of the edges in the lateral plane. z ij is a function of only the distance d between the two
points. As zij is inversely proportional to d, it gives:
zij (d )  k0 
k
k1 k 2
 2  ... ...  mm
d d
d
zii  K1
z j  K2
zij  z ji
where the constants, K1, K2, ki, and the polynomial order, m can be determined by first precomputing the
actual parameters using curve fitting techniques on data points obtained by a 3-D numerical simulator.
i
j
d
I
1
2
P epitaxial layer
RI-III
P+ buried layer
RI-II
III
4
3
II
RII-III
P substrate
P+ channel stop implant
Fig.7a: Two points substrate impedance ports
separated by distance, d
- 11 -
Fig.7b: Determining resistive coupling
between ports using point-to-point
impedance
Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
For multiple ports on the surface, large ports should be discretized into smaller ports, illustrated in Fig.7a,
due to the assumption of uniform current density across the port. Using the above preprocessing analytical
model, an admittance and impedance matrix can be formed. The impedances for the ports I, II and III
shown in Fig.7b can be calculated as follows:
 y11 y12 y13 y14 
y y y y 
 21 22 23 24 
 y31 y32 y33 y34 


 y41 y42 y43 y44 

 z11 z12 z13 z14 
z z z z 
 21 22 23 24 
 z31 z32 z33 z34 


 z41 z 42 z 43 z 44 
1
RI-II = (y13 + y23)-1 ; RII-II = (y34)-1 ; RI-III = (y14 + y24)-1
The preprocessing analytical method is the simple substrate noise coupling technique that can be developed
in preprocessing stage. It is used in the extraction process to evaluate point-to-point impedances rapidly.
This approach requires to be computed only once for a given process because the resulting data can be
stored in libraries and then used in the real-extraction of different integrated circuit again. On the other
hand, only the ports that connect the substrate to the wells, contacts, or devices are necessarily discretized
so that the resulting matrix in the network is much smaller. The computation of this approach is faster than
the Finite Difference Mesh Method and Boundary Element Method. The trade-off of this approach is that
the accuracy is relatively low.
- 12 -
Analysis of Modeling Techniques for Substrate Noise Coupling
VI.
ECE1352 Analog IC I
Simple Resistive Macromodel Method [9]
Recently, some journals have explored a similar idea of a scalable marcomodel for substrate noise coupling
in heavily doped substrates. It is called the Simple Resistive Marcomodel method. Based on a physical
understanding of the current flow paths, this approach requires only four parameters which can be extracted
from simulations or measurements. The Simple Resistive Macromodel method is a simple and accurate
method, and can provide a clear picture about the substrate noise coupling to IC designers in the early
stages of the design.
source
sensor
x
P+
P+
G2
W1
W2
G1A
G1B
Back plane = GND
Fig. 8: Marcomodel for the substrate when the back plane is ground
According to current flow lines between a source point and a sensor point from a device simulator, a typical
heavily doped substrate can be modeled as a resistive network as depicted in Fig. 8[10]. In this circuit, G 2
(= 1/R2) is the cross coupling conductance, while G1A (= 1/R1A) and G1B (= 1/R1B) are conductances from
the source and the sensor, respectively. From the experimental results, R 2 decreases as the separations
between the source and the sensor decreases; otherwise, R 2 increases rapidly for larger separations. R1A
and R1B are independent of the separation and remain constant. Note that the back plane is either grounded,
connected to ground through an impedance, or left floating.
In order to obtain a Y-parameter matrix for the equivalent circuit of the heavily doped substrate, an ac
voltage is applied at one port and the currents are measured with other port connected to ground. Assume
that sizes and shapes of the contacts are the same, then it gives: G2 = G1A = G1B. The following two-port Yparameters for the substrate macromodel is shown:
 y y  G  G2
Y   11 12    1
 y 21 y 22   G2
 G2

G1  G2 
In order to determine G1 and G2, a Z-parameter matrix is used, and it gives:
- 13 -
Analysis of Modeling Techniques for Substrate Noise Coupling
z z 
1
Z   11 12   Y 1  2
G1  2G1G2
 z 21 z 22 
ECE1352 Analog IC I
G2 
G1  G2
G
G1  G2 
 2
Let ∆ = (G12 + 2G1G2) be the determinant of the Y-parameter matrix. z11 is a constant ξ because it is the
impedance of contact one to the substrate, with all other contacts flowing. Thus, the constant ξ can be
extracted from simulations. This gives
z11 
G1  G2

G  2G1G2
2
1
1
 G12  2G1G2  (G1  G2 )  0

Rearranging the above equation,
G1 ( x) 
1
1
 G2 ( x ) 
1  4 2 G22 ( x))
2
2
where G1 and G2 can be determined from simulators and measurements, and they are dependent of the
separations between the source and sensors. Based on the linear dependence on the semi-plot of G2, it
provides a relationship between G2 and the separation x.
G2 ( x)  e   x
where  and  are constants determined from simulations and measured data.
Consequently, there are only two contact points required to obtain relatively accurate results, so the
accuracy of  and  can be improved with more data and a nonlinear least-square fit.
The main
shortcoming of this method is that it can only be used on the heavily doped substrate. Moreover, the
operating frequency must be below 2-3GHz because the substrate can only be modeled as the equivalent
circuit as illustrated in Fig. 8. In general, the Simple Resistive Marcomodels Method is a simple technique
and provide fairly accurate results. Significantly, it can provide good insights regarding the substrate noise
coupling to IC designers in the early stages of the design.
- 14 -
Analysis of Modeling Techniques for Substrate Noise Coupling
VII.
ECE1352 Analog IC I
Summary and Trade-off of Substrate Noise Coupling Technique
Table 2. The summary and trade-off between advantages and limitations in different substrate noise coupling techniques
Techniques
Accuracy
Difficulty
Simulation
Procedure
Generality
Assumption made
Time
Stage
Finite
Difference
Mesh Method
Good
1)depends
highly on the
resolution of
discretization
Hard
1) large mesh
matrix size
Long
1) huge
matrix
sparse size
Post-layout
extraction
lightly and
heavily
doped
substrate
1) substrate consisting of
purely resistive mesh
2) ignoring the magnetic
field
Boundary
Element
Method
(using
Green’s
function)
Excellent
1) within 10%
of the actual
answer
2) offers
accurate
verification of
designs up to
approximately
2000 devices)
Hard
1)
cumbersome
mathematics
2) requiring
millions of
floating point
multiplications
Quite Long
1) matrix
size
relatively
smaller than
Finite
Difference
2) DCT can
be used as
an efficient
solver.
Post-layout
extraction
1) optimizes
the layout to
minimize the
substrate
effect
lightly and
heavily
doped
substrate
1) constant current density
across a port
2) normal field must be zero
at the top and edges of
substrate boundaries
3) substrate is purely
resistive and lossy-dielectric
Preprocessing
Analytical
Method
Relatively low
Simple
1) computed
only once for a
given process
Short
Preprocessing
lightly and
heavily
doped
substrate
1) equipotential port
2) uniform current density
across ports
3) a homogeneous substrate
4) ignoring the effects of the
chip edge
Simple
Resistive
Macromodels
Method
Relative Good
1) improved
by more input
data
Simple
1) only 3
parameters (,
, ξ) required
from 3
different
simulations
Short
Pre-layout
1) can be
utilized to
guide the
placement of
components
before layout
extraction
heavily
doped
substrate
1) treated as a resistive
network
2) for low frequency
3) back plane connected to
ground
- 15 -
Analysis of Modeling Techniques for Substrate Noise Coupling
VIII.
ECE1352 Analog IC I
Substrate Noise Coupling Reduction Techniques [11]
Some bad side effects of substrate noise are mentioned in Section II, the following section provides brief
descriptions of some design techniques and guidelines for noise-aware physical design, in order to reduce
substrate noise coupling effects. In order to minimize the coupling of substrate noise, three different
aspects should be taken into account. I) the amount of noise generated in the digital circuitry, II) the
sensitivity of the analog circuitry to noise, and III) the transfer of the noise from the digital portion of the
chip into the analog section. By minimizing these three areas, the substrate noise can be reduced. There
are four common methods to achieve the above three specifications.
1) Guard Ring
The guard ring is commonly utilized in the prevention of the substrate noise in the IC design. [12]
The ring is a surface region heavily doped with the
Bands
majority-carrier dopant and is intended to form a
Digital
Noise
Faraday shield around any sensitive devices, which
need to be protected from the substrate noise. A typical
Analog
Circuit
layout of guard bands is shown in Fig. 9. The structures
Guard Ring
of the guard ring are around the noisy and sensitive
Fig. 9: Guard bands layout
circuitry, and usually separate the digital circuits from
the analog circuits.
2) NWELL Trench
NWELL trenches can be used in between the noisy and sensitive circuitry to block the substrate current
flowing near the surface of the substrate.
3) Supply Bounce Reduction
A cross section of a package cavity with bond wires
Bond
Wire
connecting the chip to the package traces is depicted in
Fig. 10. This inductance of the package and bond wires
can lead to supply bounce.
Package
The supply bounce can Trace
cause the voltage drop between the board supply and
the chip so that the digital power and ground can be
very noisy.
There are two methods to minimize this
bad effect: i) a separate power and ground are used in
the analog portion of the chip to isolate the more
sensitive analog circuitry from the digital supply noise.
- 16 -
CHIP
PACKAGE
Fig. 10: On-chip supply bounce due to the voltage
drop across bond-wire package inductance
Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
ii) lower package parasitic inductance can be accomplished through multiple or shorter bond wire
connections. This is a very effective solution, but it is expensive due to the extra package costs.
4) Floorplanning
When the space in the circuit is available, careful
Low amplitude
analogue circuits
Medium amplitude
analogue circuits
floorplanning can be used to reduce the effect of the substrate
noise coupling. During floorplanning, specific well-isolated
areas can be allocated to noisy circuits as illustrated in Fig.11.
It means that the further the sensitive and noisy circuits are
apart, the less substrate noise coupling can affect the
High Amplitude analogue circuits
Low
speed
digital
circuits
performance of the circuit. Minimum distance requirements
P+ Guard Rings
High speed
digital
circuits
Digital Output Buffers
can be computed based on the overall noise spectral energy
produced by such circuits and the maximum levels of spurious
energy tolerated by sensitive circuits. [13]
Fig 11:Good Floorplanning to reduce the
effect of the substrate noise coupling
As with design trade-off, modifying a design to obtain better noise rejection may have an associated cost
due to extra die areas, more package pins, and more expensive packages.
IX.
Conclusion
Nowadays, the trend for IC design is high system complexities, short delay time and small die areas. These
systems may consist of analog, digital and even RF circuitry on the same substrate, so modeling the
substrate noise is very difficult because of the heterogeneity in functionality and spurious signals in the
mixed signal devices. However, substrate noise can reduce the performance and impair the functionality of
circuits, so substrate noise coupling becomes a significant consideration in the high-speed design. Based
on several techniques introduced in this paper, there are three common trends for the development of
substrate noise coupling techniques: i) simple modeling, ii) modeling methods for high frequency and iii)
pre-layout. Simple substrate coupling techniques are good for IC designers due to extremely short design
cycle. Only a few experiments need to be done for the parameters of modeling techniques. In addition, the
demand for high frequency methods is increasing because the operating frequency of IC communication
system is increasing. Consequently, modeling techniques as well as modeling equivalent circuits for high
frequency should be explored and developed.
Finally, designers would prefer that substrate coupling
analysis is performed before circuit layout extraction in order to eliminate the time consumption for
redesigning the circuits if substrate noise problems appear in the layout extraction.
- 17 -
Analysis of Modeling Techniques for Substrate Noise Coupling
ECE1352 Analog IC I
X.
Reference
[1]
Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd
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[2]
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[4]
Nishath K. Verghese and David J. Allstot, “Rapid Simulation of Substrate Coupling Effects in
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[8]
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[9]
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[10]
Anil Samavedam, Aline Sadate, Kartikeya Mayaram, “A Scalable Substrate Noise Coupling
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[11]
Edoardo Charbon, Ranjit Gharpurey, Paolo Miliozzi, Robert G. Meyer and Alberto SangiovanniVincentelli, Substrate Noise, Boston: Kluwer Academic Publishers, 2001
[12]
Shigetaka Takagi, Nicodimus Retdian Agung, Kazuyuki Wada and Nobuo Fujii, “Active Guard
Band Circuit for substrate noise suppression”, IEEE International Symposium on Circuits and
Systems, ISCAS 2001, Vol.1, pp.548-551, 2001
[13]
Raminderpal Singh, “A Review of Substrate Coupling Issues and Modeling Strategies”, IEEE
Custom Integrated Circuits Conference, pp.491-499, 1999
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Robert F. Pierret, Field Effect Devices, 2nd, Massachusetts: Addison-Wesley Publishing Company,
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[15]
Sedra and Smith, Microelectronic Circuits, 4 th Edition, New York: Oxford University Press, Inc.,
1982
- 18 -