Download Representations of any two different signals

Operational Amplifiers
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Outlines
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Ideal & Non-ideal OP Amplifier
Inverting Configuration
Non-inverting Configuration
Difference Amplifiers
Effect of Finite Gain and Bandwidth
Large Signal Operation
DC Imperfections
Integrators & Differentiators
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Operational Amplifiers
• Components of electronic circuits
– Passive components (resistors, capacitors,
inductors)
– Electronic devices (diodes, transistors)
• OP Amp
– Not electronic device
– Treat as the basic circuit element because
• Well defined, almost ideal terminal characteristics
• Commercially available, widely used circuit building
block
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OP Amp Circuit Symbol
Inverting input
Non-inverting input
With dc
power supplies
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Function of OP Amp
• Differential-input, single output amplifier
– OP amp responds ONLY to the difference signal
v1
v3  A  v2  v1 
v2
Open-loop gain
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Characteristics of Ideal OP Amp
• Infinite input impedance
– NO input current
• Zero output impedance
– Ideal voltage source at the output
• Infinite open-loop gain A
– Closed-loop configuration ONLY
• Infinite bandwidth
• Zero common-mode gain
= infinite common-mode rejection
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Equivalent Circuit of Ideal OP Amp
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Amplifier Configurations
Negative
feedback
Inverting
configuration
Non-inverting
configuration
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Equivalent Circuit of Inverting
Configuration with Ideal OP Amp
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Virtual Short Circuit Between Two Inputs
vO  A  v2  v1 
vO
v2  v1 
A
Due to the infinite gain assumption,
vO
v2  v1 
0
A
Hence,
v1  v2
• DO NOT physically short terminals 1 &2
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Closed-Loop Gain of
Inverting Configuration
vO R2
G

vI R1
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Input/Output Resistances
vI vI
vI
Ri   
 R1
ii
i1 vI / R1
Ro  0
• High Ri to get max. overall gain
High R1
Impractically high R2 to get high G = -R2/R1
• Low Ri
Smaller gain & not efficient
Solution is in Example 2.2
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Effect of Finite Gain A
• Drop the assumption of “virtual short circuit”
vO
v1  
A
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G For Finite Gain A …
 R2 
  
R1 

G
 1  R2 
1  1  
 A  R1 
R2
lim G  
A 
R1
(extreme case)
To minimize the effect of finite A, make
by selecting the resistors satisfying
1  R2 
  1    0
A
R1 
 R2 
A  1  
 R1 
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Weighted Summer
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Weighted Summer with
Coefficients of Both Signs
 Rc 
 Ra  Rc 
 Ra  Rc 
 Rc 
vO  v1     v2     v3    v4  
 R1  Rb 
 R2  Rb 
 R4 
 R3 
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Closed-Loop Gain of
Non-Inverting Configuration
Ri  
Ro  0
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Effect Of Finite Gain A
• With finite gain
vO
vId 
A
• Closed-loop gain becomes
vO

vI
1  R2 / R1 
G

 1  R2 / R1  
G
1 
1


 
A


 A
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Voltage Follower/Buffer
• Unity-gain amplifier (G = 1) by making
R1   and R2  0
• In the ideal case, it becomes that
Rin   and Rout  0
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Two Different Signals
• Any two signals can be factorized to two different
modes
Differential-Mode Component:
Common mode input signal:
vId  v2  v1
vIcm
1
 v1  v2 
2
Representations of any two different signals
vId
v1  vIcm 
2
vId
v2  vIcm 
2
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Equivalent Circuit
Of Two Input Signals
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Common/Differential Mode Gains
v1
v2
vO  A1v1  A2v2
A1 
vO
v1
A2 
v2  0
vO
v2
v1  0
Alternative representation:
vO  Acm vIcm  AdmvIdm
Acm  A1  A2
Adm   A2  A1  / 2
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Common Mode Rejection Ratio
(CMRR)
Adm
CMRR  20  log
Acm
(dB)
• Why does not use open-loop OP amp?
– Because closed loop gain is (1) finite, (2)
predictable, and (3) stable.
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Ideal OP Amp.
• Common mode rejection property
– Ignores any common signal of two inputs.
• Gain of input 2 is equal to the inverse gain of input 1
A1  A2
Common mode gain:
Acm  A1  A2  0
Differential mode gain:
Adm   A2  A1  / 2  A2
Hence, ideal OP amp has infinite CMRR:
CMRR  
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Difference Amplifier
 R2 
 R2  R4 
  v2


vO      v1  1  
 R1 
 R1  R3  R4 
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Common Mode Gain
vO  R4  R2 R3 
1 

Acm 
 
vIcm  R3  R4  R1R4 
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Differential Mode Gain
With the conditions for the perfect common-mode
rejection:
R3  R1 and R4  R2
The circuit becomes the difference amplifier satisfying:
vO  Adm v2  v1 
R2
Adm 
R1
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Differential Input Resistance
vid  v2  v1  R1iI  R3iI
Rid  R1  R3
Rid  2R1 , with th e condition of R3  R1
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Instrumentation Amplifier
• Problem of a single OP amp difference
amplifiers
– Require high resistance R1 in order to get high
input impedance
– Results in extremely high resistance R2 in order to
get high differential gain
• Solution
– Buffering the two input terminals using voltage
followers
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Circuit For Instrumentation Amp.
vO 
R4  R2 
1  vId
R3  R1 
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Disadvantages Of Previous Design
1. Common mode signal is amplified at the first
stage
•
•
OP amp. saturation OR
Reduced overall CMRR
2. Require perfect match between two OP amps
A1 and A2
3. Require perfect match between two resistors
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Modified Circuit
R4  R2  R2 ' 
vId
vO  1 
R3 
2 R1 
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Properties Of Practical OP Amps
• Finite gain
• Limited bandwidth
• Finite (non-zero) common mode gain
– Finite CMRR
• Finite input resistance
• Non-zero output resistance
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Freq. resp. of open-loop gain of OP Amp
A0
A( s ) 
1  s / b
(Corner frequency)
(Unity-gain bandwidth)
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Frequency Response of Inverting
Amplifiers
From slide 16
 R2 
  
 G0
 R1 
G( s) 


 1  G0
1  R2 


1  
1 
1  

t

 A( s)  R1 

s

R2
R1
DC gain:
G0 
Corner Freq:
3dB 
t
1  R2 / R1
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Non-Linear Distortion of
Large Signal Operation
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•
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Output voltage saturation
Output current limits (about ±20 mA)
Slew rate
Full-power bandwidth
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Output Voltage/Current Limits
• See Example 2.5 in page 94 for exact understanding
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Slew Rate Limiting
• Maximum rate of change possible at the output of the
real OP amp.
dvO
SR 
dt
(V / s)
max
• Distinct from the finite bandwidth limiting the
frequency response. (linear distortion)
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Step Response to Voltage Follower

vO (t )  V 1  e t t

When V is sufficiently small
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Full Power Bandwidth
vI  Vˆi sin t
dvI
 Vˆt cos t
dt
Non-linear distortion when
Full power bandwidth:
Vˆt  SR
SR
fM 
2Vˆo ,max
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DC Imperfections
• Offset Voltage
– 1 ~ 5 mA
– Depends on Temerature
• Input Bias and Offset Currents
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CKT Model with Offset Voltage
• Data sheet specifies
– Typical VOS
– Max. VOS
– Temp coefficient: μ
V/°C
– No polarity (not
known a priori)
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Offset Voltage Effect
• Output signal is shifted by DC voltage (Vo)
– Reduced allowable signal swing
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Applying Coupling Capacitor
• Cannot amplify DC or low frequency signal
components
• Form STC high-pass filter with 0  1 / CR1
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Input Bias & Offset Currents
Input bias current:
I B1  I B 2
IB 
2
Input offset current:
I OS  I B1  I B 2
For BJT, IB = 100 nA & IOS = 10 nA
For FET, pA
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DC Output Voltage
Due to Bias Currents
Problem:
Limit R2
 Limit closed loop gain
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Solution
By setting
R3  R1 R2
Output voltage becomes
VO  I OS R2
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Conclusion
• In order to minimize the effect of the bias currents,
make
R3 = [dc resistance at inverting terminal]
ac coupled amplifier
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Inverting Configuration with
General Impedances
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