Download Electronic System Level Design BACKGROUND OBJECTIVES

Hauptseminar im Sommersemester 2012
Electronic System Level Design
OBJECTIVES
In this seminar, we will cover:
- Programming and description languages
- Embedded systems and architectures
- SoC (System-on-Chip) design
- Compiler and code generation
- Logic synthesis
Electronic System Level Design is a widespread
buzzword through the industry targetting embedded
systems. The challenge of ESL is the synthesis of
parallel hardware-architectures from an algorithmic
system description, formulated in either high-level
programming languages, such as C or C++, but also
to use special
Algorithm
high-level
ALGORITHM
hardware
description
languages,
such as
Protocol
SystemC.
Library
Moreover,
the usage of
Directives
special tools,
as, for
RTL
example,
Implementation
the Matlab &
Simulink HDL
backend
round off
state-of-the-art
methodologies
for embedded
system design. GATES
Operation
scheduling
Data path
design
Cycle
timing
Control
path design
RTL generation
Existing
logic
synthesis
Area
An ever growing market for consumer products as
well as medical image processing are demanding
energy efficient and very powerful hardware
solutions providing a high degree of parallelism.
As a consequence, the process of hardware design
was moved from development on the gate level to
the register transfer level (RTL) with hardware
description languages, such as Verilog and VHDL over
the last decades. With the progress from large scale
integration to very large scale integration (VLSI)
the strcutures on modern integrated circuits have
become very small so that it is possible to integrate
whole systems, consisting of several different
components, in a single chip. To enable design and
testing of such a system on a chip (SoC) withing a
relatively short time to market a much higher level
of abstraction must be used. This means that rather
the algorithms describe the system instead of the
actual hardware implementation.
METHODOLOGY
Resource
allocation
BACKGROUND
Frames / Second
ORGANIZATION
The participation in this seminar is recommended for students having completed the 4th semester.
Proof of participation (”Schein”) will be granted for students having participated in the seminar sessions and
having successfully given an oral report and prepared an accompanying script of the presentation.
To participate, please contact Moritz Schmid ([email protected]) before April 17th 2012.
Lecturers:
Credits:
Date and Location:
Dr.-Ing. Frank Hannig, Moritz Schmid
2.5 ECTS credits
17th April 2012, 02.122
TECHNISCHE FAKULTÄT