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µBITS
µBITS
Micro Blind Interactive Touch Screen
Chris Page
Peter Gimeno
Christina Williams
Greg Weatherford
Christopher Howard
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Purpose
 To give the blind the capability to interface
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with a computer and the internet.
To create a pin bed that can display scrolling,
Braille characters, ASCII characters, a few
Japanese characters and simple
monochromatic images.
To create a pin bed that is compact and more
portable than current Braille books.
With a flexible I/O interface capable of USB
and PS/2
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Presentation Overview
 Requirements and Standards
 Block Diagram
 Digital Design Process
 Software
 Analog Design Process
 Interface between D/A
 Schedule/Division of labor
 Cost
 Questions, Comments?
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Product Overview
 A three dimensional display board.
 Designed for use by the blind.
 Capable outputting multiple character sets
 Flexible I/O interface
 Integrated Keyboard Support (USB or
PS/2)
 Software designed to support up to a
320x240x8 pin display.
 Compact
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Initial Requirements –
Environmental Standards
 Operation at standard room
temperatures.
 Safe for end user operation.
 Compliant with FCC standards.
 Safe for pacemaker users.
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Initial Requirements Performance Standards
 CPU Capable of image/video
decoding.
 512Kb of frame backing/character
lookup memory. (Was 2Mb)
 3Mb of CPU memory. (Was 4Mb)
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Initial Requirements –
Interface Standards
 P/S 2 keyboard input
 Pin Grid Output
 2 General purpose I/O inputs
 Capable of supporting USB, IDE, Digital
Cameras, serial, and many other popular
input methods.
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Block Diagram
Future I/O Expansion
P/S 2 Input
Memory
512Kb SRAM
Frame Buffer and
Character Lookup
Table
Memory
3Mb SRAM
FPGA
Display Driver
I/O Controller
Analog
Display Driver
Pin Grid
Processor
CY7C67200
50 MHz
GCC programmable
Future Expansion
Power supply
DC –DC
converters
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Nesting Diagram
CPU Board
(CIB)
Digital Power
Supply
FPGA Board
(PGGU)
PGGU VRAM
Board
(VRAM)
Pin Grid Driver
Board
(PGD)
Analog Power
Supply
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Board Features
 IDE/GPIO interface
 Direct RAM communication with FPGA
 Serial Debug Interface
 LED Status Indicators
 Overcurrent and Undervoltage CPU Protection
 HSSI
 2 independent USB data and power busses
 Prominent Reset Button
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Design Demo
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Digital Progress
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Determined Specification Details
Part selection
Schematic Capture
Schematic Review
Layout
 Board Manufacturing
 Board Electrical Test
 Board Population
 Board Operational Testing
 Software
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Proposed Software Diagram
CPU
FPGA HDL
Encoder
SRAM
Receiver
SRAM
Driver
Image
Processing
Font
LUT
Decoder
VRAM
Driver
USB
Driver
USB
Driver
(serial)
(HID)
PS/2
Driver
Braille
LUT
Data
USB HID
Device
(Keyboard)
(computer)
SRAM
PS/2
Keyboard
Display
Driver
Display
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SRAM Timing Diagram
QuickTime™ and a
TIFF (LZW) decompressor
are needed to see this picture.
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PS/2 Timing Diagram
QuickTime™ and a
TIFF (Uncompressed) decompressor
are needed to see this picture.
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PS/2 Receiver Flowchart
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VRAM Driver Flowchart
QuickTime™ and a
TIFF (Uncompressed) decompressor
are needed to see this picture.
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SRAM/FPGA Data Transfer
 128 addressable bytes
 Byte 0 is command byte
 Byte 127 is status byte
 Bytes 120-126 are pin grid display mode
registers.
 Bytes 1-10 are Data bytes
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Current Digital Issues
 Communication Protocols
 HDL Way Behind Schedule
 NO PROJECT SOFTWARE HAS BEEN
WRITTEN YET!
 Data Representation
 Group Communication
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Analog over view
 Progress
 Design
 Prototype Design Details
 Ideas that didn’t work
 Problems/solutions
 Current problems
 Future Goals
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Analog Progress
Tested pin elevation techniques
Designed three character Braille board
Cut Braille board on Laser cutter in ITLL
Chose and modified power supply for
Braille board
Designed schematic for Braille board
Tested Design
Begin building three character Braille
board
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Failed Idea: High-Z DeMUX
Decoder
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Outputs
FPGA
Decoder
1
Z
Decoder
0
Z
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Z
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Requires a high refresh
rate for even small
designs
Solenoids are limited to
roughly a 30 Hz refresh
rate
For 100 pins, this would
take over 3 seconds to
refresh each pin
Since the pin is only
active for this brief
refresh period, gravity
does becomes an issue
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Promising Design: M&M (MUX
Memory)
 More complex then
Outputs
Clock
DEMUX
FPGA
Reset
Pin Grid
Memory
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Current
Driver
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High-Z DeMUX
design
Memory will allow
pins to remain
elevated
Eliminates possible
problems with
surrounding pins
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Analog Design (LPBB): Actual Pin Board
Design
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Pin 6 - Capitalization
Pins 2, 3, 4 – Full
Character
0.200”

0.02” to 0.05”
0.20”
Distance between each Braille
module = 0.6”
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(From PDR) We are looking to modulize each
2x3 section.
We did not modulize
because we are dealing with
a low amount of characters
(only 2-3 char.)
(From PDR) The pins will meet Braille
specifications.
We did not meet the Braille
specifications but we
accomplished to be off only
be approx. 0.05” between
characters.
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Analog Design : First Prototype
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Will be a 2x3 board. (one Braille character)
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Need to test board dimensions.
Will use magnetic elevation (ME).
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Need to know wrapping to current ratio.
Size of pins needed.
Will use one of the pin addressing designs.
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Depends on if High Z MUX will perform as expected
within a reasonable cost.
Will not be connected to FPGA, will simulate
FPGA output.
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Analog Design : Prototype
Checklist
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Pin has to elevate to correct height.
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Record winding to current ration for correct height.
Pin has to stay elevated at correct height for
specific amount of time.
Touching our display will not cause harm to the
person.
Measured operating characteristics of each
solenoid
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Up to 12V
0.3 to 1 Amp
30 Hz or less
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Analog Design : Current
Design
 Can display 5 Braille characters
 Uses magnetic elevation (ME)
 Due to the size of the solenoids, a multi level
design was used
 Uses Direct Pin Addressing
 Has yet to be connected to the FPGA
 Can still be operated manually
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Analog Schematic
For the 3 character Braille board
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Analog Components
For the 3 character Braille board
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Power supply, can supply up to 20 A @ 5V
Voltage Regulator
 560  1/4 Watt resistor
 1.1K  1/4 Watt resistor
 2N3055 Power transistor
2N2222A NPN transistor 600mA @6V DC continuously
18 Solenoid actuators. 10 ohms, .3A @2.3V continuously
Plastic board to hold the assembly, 4 layers.
2 of 0.13” bolts to hold assembly together.
10 of 0.13” nuts to hold the levels in place on the
assembly
18 of 0.025” sewing pins with flat tops.
18 1K  1/8 watt resistors to current limit the FPGA
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Voltage regulator, Single pin
for the 3 Character Braille board
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Analog Design : Issues that
have been Addressed
 Layout Board
 Record list of manufactures and stores needed.
 Solenoids will be purchased rather then made
 Begin tests of layout board
 Looked specifically at:
 Pin addressing
 Pin Board Layouts / Designs
 People contacted for input or design issues
 Lucy Pao – CU
 Gagandeep Lamba – CU
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Analog Design : Issues to be
Addressed
 Programming the FPGA
 Learning Verilog and programming a PS/2
interface
 Building the ‘Blow Out’ Circuitry between the
FPGA and the Pin Board
 Safety precaution to prevent damage to FPGA
I/O ports
 Practical 3D designs
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Analog Ideas that didn’t work
 Using a capacitor to make the actuator
have more current for the first ms. The
time period is too long, the cap would
have needed to be too big.
 Magnetic pin elevation
 Memory Metal pin elevation
 Bimetallic pin elevation
 Bobbin and drill for wrapping coils.
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Analog Problems/ Solutions
Problems
Solutions
The actuators would move around inside the
plastic sheet so much that they would become
un-square and the pin wouldn’t come out.
Cut the board out of a thick sheet of
plastic to hold the actuators in place.
The Pins on the actuators don’t always come up
without help from the user
Build the 3 character Braille only board
so that the pins can never fall more than
10% out side of the actuator.
How do we keep the magnetic pins from
interfering.
Use an actuator solenoid
A 1watt resistor for each actuator takes up to
much space
Design a Voltage regulator to lower the
voltage one final time.
It is difficult and time consuming to uniformly
Purchase Actuator solenoids.
wrap 400 turns of 36 Gauge wire in less than 0.16”
diameter
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Future Goals
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Interface three character Braille board to the Ps/2
keyboard
Test three more possible methods of 3-D pin
elevation
 Magnetic pins with Aluminum collars
 Linear motors
 Drop pins through coils.
Choose elevation method then design 100 pin board.
Purchase parts for 100 pin board
Build 100 pin board
Interface 100 pin board to CPU board
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Analog Design : Next Steps
(Prototype and Beyond)
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Layout Board
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Record list of manufactures and stores needed.
Wrapping solinoids.
Begin tests of layout board
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Looking specificly at:
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Lisa Pao - CU
NIST Researchs of Tactile Board
 Scrolling
 Pin addressing
Current Contacts to work with us
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-
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Interface between Digital and
Analog
 Progress
 Ideas
 Future Goals
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Interface progress
 Tested Mux matrix idea (did not work)
 Learning Verilog to program firm ware
for interface.(in progress)
 Come up with possible design
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Analog Design : Ideas for
Implementation
 Pin Addressing
 High-Z MUX Decoder
 Not very compatible with our design
 Direct Pin Addressing
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Serial to Parallel conversion
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Accepts serial
data from one I/O
port on the FPGA
which would then
be used to send
the correct voltage
to multiple pins.
We would still
need many S to P
chips to address
all the pins in the
100 pin bed.
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Interface Future Goals
 Select components for S to P idea
 Build S to P prototype and test it.
 Assemble final S to P interface for 100
pin bed.
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Schedule and Division of labor
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Cost Estimate
 FPGA development board: $175
 Computer PCB: $350
 PCB components $300.00
 Three character Braille pin bed $30.00
 100 pin bed $200.00
 Digital-Analog Components: $50
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Questions, Comments?