Download Keysight 1GC1-4266 DC-12 GHz Packaged Divide-by

Keysight 1GC1-4266
DC-12 GHz Packaged
Divide-by-4 Prescaler
Data Sheet
Features
–– Wide frequency range:
0.2 to 12 GHz
–– High input power
Sensitivity:
On–chip pre– and post–amps
-15 to +10 dBm (1 to 8 GHz)
-10 to +8 dBm (8 to 10 GHz)
-5 to +2 dBm (10 to 12 GHz)
–– Pout: +0 dBm (0.5 Vp–p)
–– Low phase noise:
-153 dBc/Hz @ 100 kHz offset
–– (+) or (-) Single supply bias
with wide range:
4.5 to 6.5 V
–– Differential I/0 with on–chip
50 Ω matching
–– Available in RoHs compliant,
16 pin 3 mm x 3 mm QFN SMT
package w/integral heat sink
02 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
Description
The 1GC1-4266 is a packaged GaAs HBT MMIC prescaler which offers DC to 12 GHz
frequency translation for use in communications and EW systems incorporating high–
frequency PLL oscillator circuits and signal–path down conversion applications. The
differential I/O compatible prescaler provides a large input power sensitivity window,
low phase noise and is packaged in a 3 mm x 3 mm 16-pin QFN SMT package.
Absolute maximum ratings1
(@ TA = 25 °C, unless otherwise indicated)
Symbol
Parameters/conditions
Min.
Max.
Units
VCC
Bias supply voltage
+7
Volts
VEE
Bias supply voltage
-7
Vcc – VEE
Bias supply delta
0
+7
Volts
VLogic
Logic threshold voltage
Vcc-1.5
Vcc- 1.2
Volts
Pin(CW)
CW RF input power
+10
dBm
VRFin
DC input voltage
(@ RFin or RFin ports)
Vcc ± 0.5
Volts
Top2
Pkg heatsink operating temp.
-40
+85
°C
Tst
Storage temperature
-65
+165
°C
Tmax
Maximum solder reflow temp.
(Max. 3 cycles @ 30 sec/cycle)
260
°C
Volts
1. Operation in excess of any parameter limit (except Top) may cause permanent damage to the device.
2. MTTF > 1 x 106 hours @ Top ≤85 °C. Operation in excess of maximum package pin operating
temperature (Top) will degrade MTTF.
–– Package type:
Quad Flat - No pins (SMT QFN)
–– Package dimensions:
3.0 mm x 3.0 mm
(0.118 x 0.118 in)
–– Package thickness:
0.90 ±0.10 mm
(0.035 ±0.0039 in)
–– Pin pitch: 0.5 mm (0.0197 in)
–– Pin width: 0.20 mm (0.008 in)
03 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
DC specifications/physical properties1
(TA = 25 °C, VCC – V EE = 5.0 volts, unless otherwise listed)
Symbol
Parameters/conditions
1
Min.
Typ.
Max.
Units
VCC – VEE
Operating bias supply difference
4.5
5.0
6.5
Volts
|ICC | or
|IEE |
Bias supply current
34
40
46
mA
VRFin(q)
VRFout(q)
Quiescent DC voltage appearing at all RF ports
VLogic
Nominal ECL logic level
Vcc
Vcc-1.45
Vcc-1.32
Volts
Vcc-1.25
Volts
1. Prescaler will operate over full specified supply voltage range. VCC or V EE not to exceed limits specified in Absolute maximum ratings section.
RF specifications
(TA = 25 °C, Z0 = 50 Ω, VCC - V EE = 5.0 volts)
Symbol
Parameters/conditions
ƒin(max)
Maximum input frequency of operation
ƒin(max)
1
ƒSelf-Osc.
Pin
Min.
Typ.
12
14
=
Minimum input frequency of operation (Pin -10 dBm)
Output self-oscillation frequency
0.2
2
Max.
Units
GHz
0.5
3.4
GHz
GHz
@ DC, (square-wave input)
-15
>-25
+10
dBm
@ƒin = 500 MHz, (sine-wave input)
-15
>-20
+10
dBm
ƒin = 1 to 8 GHz
-15
>-20
+5
dBm
ƒin = 1 to 10 GHz
-10
>-15
+5
dBm
ƒin = 10 to 12 GHz
-5
>-10
+1
dBm
RL
Small-signal input/output return loss (@ ƒin < 10 GHz)
15
dB
S12
Small-signal reverse isolation (@ ƒin < 12 GHz)
30
dB
φN
SSB phase noise (@ Pin = 0 dBm, 100 kHz offset from
a ƒout = 1.2 GHz carrier)
-153
dBc/Hz
Jitter
Input signal time variation @ zero-crossing
(ƒin = 10 GHz, Pin = -10 dBm)
1
ps
Tr or Tf
Output transition time (10% to 90% rise/fall time)
70
ps
@ ƒout < 1 GHz
-2.0
0.0
dBm
@ ƒout = 2.5 GHz
-3.5
-1.5
dBm
@ ƒout = 3.5 GHz
-4.5
-2.5
dBm
@ ƒout < 1 GHz
0.5
Volts
@ ƒout = 2.5 GHz
0.42
Volts
@ ƒout = 3.5 GHz
0.37
Volts
ƒout power level appearing at RFin or RFin
(@ ƒin 10 GHz, unused RFout or RFout unterminated)
-50
dBm
ƒout power level appearing at RFin or RFin
(@ ƒin 10 GHz, both RFout and RFout terminated)
-30
dBm
P feedthru
Power level of ƒin appearing at RFout or RFout
(@ ƒin = 12 GHz, Pin = 0 dBm, referred to Pin (ƒin))
-30
dBc
H2
Second harmonic distortion output level
(@ ƒout 3.0 GHz, referred to Pout (ƒout))
-25
dBc
Pout
1
|Vout(p-p)|4
PSpitback
1. For sine–wave input signal. Prescaler will operate down to DC for square–wave input signal. Min. divide frequency limited by input slew rate.
2. Prescaler can exhibit this output signal under bias in the absence of an RF input signal. This condition can be eliminated by use of the Input
DC offset technique described on page 3.
3. Fundamental of output square wave’s Fourier Series
4. Square wave amplitude calculated from Pout
04 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
Applications
The 1GC1-4266 is designed for use in high frequency communications, microwave
instrumentation, and EW radar systems where low phase–noise PLL control circuitry or
broad–band frequency translation is required.
Operation
The device is designed to operate when driven with either a single–ended or differential
sinusoidal input signal over a 200 MHz to 12 GHz bandwidth. Below 200 MHz the prescaler
input is “slew–rate” limited, requiring fast rising and falling edge speeds to properly divide.
The device will operate at frequencies down to DC when driven with a square–wave.
Due to the presence of an off–chip RF–bypass capacitor inside the package (connected to
the VCC contact on the device), and the unique design of the device itself, the component
may be biased from either a single positive or single negative supply bias. The backside of
the package is not directly connected to any DC bias point on the device.
For positive supply operation, VCC pins are nominally biased at any voltage in the +4.5 to
+6.5 volt range with pin 8 (VEE ) grounded. For negative bias operation VCC pins are typically
grounded and a negative voltage between -4.5 to -6.5 volts is applied to pin 8 (VEE ).
1. N/C pins can be left open, but it is recommended to connect
these to RF/DC ground.
2. Pin17 is the center heat slug this must be connected to RF/DC
ground. Use filled vias to prevent solder voids.
3. Discrete parallel plate capacitor or equivalent: 250 VWDC,
+/- 10% capacitance tolerance
Figure 1. 1GC1-4266 simplified schematic
05 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
AC–Coupling
All RF ports are DC connected on–chip to the VCC contact through on–chip 50 resistors.
Under any bias conditions where VCC is not DC grounded, the RF ports should be AC
coupled via series capacitors mounted on the PC–board. Only under bias conditions
where VCC is DC grounded (as is typical for negative bias supply operation) may the RF
ports be direct coupled to adjacent circuitry or in some cases, such as level shifting to
subsequent stages. In the latter case the package heat sink may be “floated” and bias
applied as the difference between VCC and VEE.
Input DC Offset
If an RF signal with sufficient signal to noise ratio is present at the RF input pin, the
prescaler will operate and provide a divided output equal the input frequency divided
by the divide modulus. Under certain “ideal” conditions where the input is well matched
at the right input frequency, the component may “self–oscillate”, especially under small
signal input powers or with only noise present at the input This “self–oscillation” will
produce a undesired output signal also known as a false trigger.
To prevent false triggers or self–oscillation conditions, apply a 20 to 100 mV DC offset
voltage between the RFin and RFin ports. This prevents noise or spurious low level signals
from triggering the divider.
Adding a 10K Ω resistor between the unused RF input to a contact point at the VEE
potential will result in an offset of ª25 mV between the RF inputs. Note however, that the
input sensitivity will be reduced slightly due to the presence of this offset.
An input DISABLE pin is also provided to allow the prescaler input pre-amp to be locked
into either a logic “High” or “Low” state, thereby preventing false triggers.
Assembly Techniques
Independent of the bias applied to the package, the backside of the package should
always be connected to both a good RF ground plane and a good thermal heat sinking
region on the PC–board to optimize performance. For single–ended output operation,
the unused RF output pin should be terminated into 50 Ω to a contact point at the VCC
potential or to RF ground through a DC blocking capacitor.
Figure 2 shows the package/PCB assembly diagram for single–ended or differential
input frequency operation through 12 GHz. For positive supply operation, VCC is typically
biased to a positive voltage between +4.5 and +6.5 volts and VEE is grounded. For
negative supply operation, VEE is typically biased between –4.5 to –6.5 volts and VCC is
grounded. In either case, the supply contact to the package bias pin(s) must be capacitively bypassed (0.01 mF, recommended) to provide good bias stability, input sensitivity
and low input power feed through. The bypass capacitor should be located as close as
possible to the package pin.
In general, AC coupling capacitors are recommended on the RFin and RFout connections
to the package. For positive supply operation, VCC is positively biased resulting in a
positive DC voltage appearing at RFin or RFout. In this case a AC coupling cap is required.
For singulated package dimensions of the 3 mm x 3 mm QFN package, refer to Figure 3.
The QFN SMT package is compatible with industry standard solder-reflow attach
processes.
06 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
~0.01 μf Monoblock
SMT AC Coupling
Capacitor
(4 places)
Positive supply
VCC (+4.5 to
+6.5 volts)
~0.01 μf Monoblock
SMT VCC Bypass
Capacitor
OPTIONAL VPwrSet pin connection
Multi-layer,
VIPPO*, RF
and DC
Ground VIAs
0.0 Ω SMT Resistor
~0.01 μf Monoblock
SMT AC Coupling
Capacitor (4 places)
VEE
(Gnd)
w/pin connected to GND:
HIGH Pout Assembly (0.0 dBm [0.5 Vp–p]
@ ICC = 58 mA)
w/pin NOT connected to GND:
LOW Pout Assembly (-6.0 dBm [0.25 Vp–p]
@ ICC = 40 mA)
Optional VPwrSel
0.0 Ω SMT Resistor
A.
Negative supply
(Gnd)
VCC
0.0 Ω SMT Resistor
Multi-layer,
VIPPO*, RF
and DC
Ground VIAs
OPTIONAL VPwrSet pin connection
w/pin connected to VEE:
HIGH Pout Assembly (+00 dBm [0.5 Vp–p]
@ IEE = -58 mA)
w/pin NOT connected to VEE:
LOW Pout Assembly (-6.0 dBm [0.25 Vp–p]
@ IEE = -40 mA)
VEE
0.0 Ω SMT
Resistor
(Gnd)
~0.01 μf Monoblock
SMT Bypass Capacitor
VEE
(-4.5 to -6.5 volts)
Optional VPwrSel
0.0 Ω SMT
Resistor
B.
Figure 2. 1GC1-4266 Assemby diagram A.) Single-supply, positive-bias configuration B.) Single-supply, negative-bias configuration
1. Supply bypass capacitors should be positioned as close as possible to the package supply pin.
2. V EE MUST be grounded (positive supply configuration) or biased to a negative supply (negative supply operation.) V PwrSel connections are optional
depending on the output power and supply current requirements of the application.
3. The package backside grounding pad MUST be soldered to a good RF ground trace and thermal heatsinking area on the PC board to achieve optimum
forward and reverse isolation. The package backside grounding pad is NOT DC connected to the device DC ground.
4. For single–ended output operation the unused RFout or RFout Pin should be terminated in 50 Ω to VCC or to ground through an AC coupling capacitor
(positive supply operation) or to ground (negative supply operation) to achieve optimum input sensitivity and reverse "Spitback" performance.
5. PCB ground paddle should incorporate multi-layer, “Via In Pad Plated Over (VIPPO)* RF and DC grounding vias.
07 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
Top view
Bottom view
3.00
.118
1.75
.068
1.75
.068
3.00
.118
0.24
.009
Side view
0.90
.035
0.50
.020
1. Dimensions in millimeters
2. Side of pin is not plated (bare copper alloy, max burr 0.15 mm)
3. Permanently mark-part number and date code (4x4 number,
year, work week)
Figure 3. Package and dimensions
Moisture Compatibility
Injection mold components like the 1GC1-4266 are moisture-sensitive. The product is
tested to the Moisture and Reflow Sensitivity Level 3A as per IPC/Jedec J-STD-020 and
must be mounted within 168 hours of opening the shipping container. Store and handle
parts for reflow and for rework per IPC/Jedec J-STD-033B.
Tape and Reel
The 1GC1-4266 is available in tape and reel format to facilitate automatic pick and place
manufacturing. Figure 4 shows the tape dimension for the 1GC1-4266 packaged solution.
08 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
Reel
Tape
User
Feed
Direction
CoverTape
0.30
4.001
8.00
±0.10
Ø1.50 0
Ø1.50 min.
2.00 ±0.053
A
1.75 ±0.10
R 0.30
0.10
5.50 ±0.053
3.30
R 0.25
3.30
A
1.10
Section A–A
Scale 10x
Figure 4. Assembly diagram (Single-supply, positive-bias configuration shown)
RoHS Compliance
This part is RoHS compliant, meeting the requirements of the EU Restriction of Hazardous
Substances Directive 2011/65/EU, commonly known as RoHS.
Six substances are regulated: lead, mercury, cadmium, chromium VI (hexavalent chromium), polybrominated biphenyls (PBB), and polybrominated biphenyl ethers (PBDE). RoHS
compliance requires that any residual concentration of these substances is below the
Directive’s maximum concentration values (MCV): cadmium 100 ppm by weight and all
others 1000 ppm by weight.
ESD and Handling Precautions
GaAs MMICs in either chip or SMT packages are ESD sensitive. ESD preventive measures
must be employed in all aspects of storage, handling, and assembly.
MMIC ESD precautions, handling considerations, die attach and bonding methods are
critical factors in successful GaAs MMIC performance and reliability.
Keysight application note, “GaAs MMIC ESD, Die Attach and Bonding Guidelines” provides
basic information on these subjects.
Additional References
PN #18, “HBT Prescaler Evaluation Board”
12.00 ±0.30
09 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
(VCC - VEE = +5 volts, TA = 25 °C)
10
0
ISupply (mA)
Input power, Pin (dBm)
20
-10
-20
-30
-40
0
2
4
6
8
10
12
Input frequency, ƒin (GHz)
14
16
Figure 5. Typical input sensitivity window
SSB phase noise (dBc/Hz)
-3
(TA = 25 °C)
0
1
2
3
4
5
6
VCC - VEE (volts)
7
8
9
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
-1.6
-1.8
-2.0
Figure 6. Typical supply current and V Logic vs. supply voltage
Pin = 0 dBm, Fcarrier = 6.0 GHz
2
Pout (Pin = 0 dBm), dBm
-23
-43
-63
-103
-123
-143
(VCC - VEE = +5 volts, TA = 25 °C)
0
-2
-4
-6
-8
-10
-163
10
100
1K 10K 100K
Offset from carrier (Hz)
1M
10M
Figure 7. Typical phase noise performance
Unterminated RFout port
Both RFout ports terminated
0
2
4
6
8
10
12
Input frequency, ƒin (GHz)
0
0.5
1
1.5
2
2.5
3
Input frequency, ƒin (GHz)
Figure 8. Output power vs. output frequency, ƒout (GHz)
(VCC - VEE = +5 volts, Pin = 0 dBm, TA = 25 °C)
PSpitback (dBm)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
50
45
40
35
30
25
20
15
10
5
0
VLogic - VCC (volts)
Supplemental Data
14
Figure 9. Typical “Spitback” power P(ƒout) appearing at RF input port
3.5
4
10 | Keysight | 1GC1-4266 DC - 12 GHz Packaged Divide-by-4 Prescaler - Data Sheet
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This data sheet contains a variety of typical and guaranteed performance
data. The information supplied should not be interpreted as a complete
list of circuit specifications. Customers considering the use of this, or
other Keysight Technologies GaAs ICs, for their design should obtain the
current production specifications from Keysight. In this data sheet the
term typical refers to the 50th percentile performance. For additional
information contact Keysight at [email protected].
The product described in this data sheet is RoHS Compliant and RoHS
Process Compatible with a maximum temperature of 260 °C and a
maximum of 3 temperature cycles.
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© Keysight Technologies, 2016
Published in USA, September 16, 2016
5992-1802EN
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