Download Power Two Xilinx(TM) LX240 Virtex-6(TM)

Reference Design
SLVA408 – April 2010
Power Two Xilinx™ LX240 Virtex-6™ Devices
This reference design is intended to help designers wishing to use two of the new Virtex-6 LX240 FPGA
along with DDR memory and other optional circuitry in their designs. It provides nine rails of lower voltage
with an input of 12 volts. The use of PTH T2 modules provides a high-performance solution for good
transient response and tight regulation while conserving valuable board space.
1
Introduction
This reference design is for powering the new Virtex-6 LX240 from a 12-V bus. It uses the Texas
Instruments PTH family of modular power solutions to save design time and space as these parts take
advantage of both sides of the board. This design uses the following parts for each rail:
• PTH08T240 for 1-V core or VCCint rail 1
• PTH08T240 for 2.5-V for the VCCaux rail 2
• PTH08T230 for 1.5-V for the VCCO DDR3 rail 3
• TPS51200 for DDR active termination for 1/2 VCCO rail 4
• PTH08000 for 1.8-V Ethernet Phy rail 5
• PTH08000 for 3.3-V for I/O SFP rail 6
• PTH08T220 for 1-V, low-noise GTP core rail 7
• PTH08T220 for 1.2-V GTP termination rail 8
• PTH08T240 for 3.3-V FMC connector rail 9
• TPS3808 SVS Reset for sequencing
2
Power Requirements
The power requirements for the XC6VLX240T are listed in the following table.
For more information and other reference designs, visit www.ti.com/processorpower and
www.ti.com/xilinxfpga
Core, I/O
Pin Name
Voltage (V)
Imax (mA)
Tolerance
Sequencing Order
Core
VCCint
1/0.9
10000
±5
1
I/O
Vcco
1.2/1.5
1.8/2.5
6000
±5
1
I/O
VCCaux
2.5
1500
±5
Timing Delay
VCCint, Vaux, Vcco:
0.20 to 50 ms
See how T2 modules can help reduce the amount of onboard capacitance required:
http://focus.ti.com/analog/docs/turbotranssearch.tsp?familyId=561
See the complete SVS Reset offering at:
http://focuswebapps.ti.com/general/docs/sitesearch/searchdevice.tsp;jsessionid=WE4XG1UP3N1SJQC1JAVR3KQ?p
artNumber=TPS3808
View the online information on DDR termination at:
http://focus.ti.com/docs/prod/folders/print/tps51200.html
Xilinx, Virtex-6 are trademarks of Xilinx in the United States.
SLVA408 – April 2010
Power Two Xilinx™ LX240 Virtex-6™ Devices
Copyright © 2010, Texas Instruments Incorporated
1
Power Requirements
www.ti.com
A/T
VS1
12V@128W
#1 Sequence Voltage ( First on)
PTH08T240W
1.0V@10A
Eff. 83%
5kO
1V@3A
TPS3808G0.9
1V SVS
15ms
Delay
Vcc 5V
5.1V
VS2
VCC to
SVS
A/T
2.5V@2A
Vc c 5
A/T
PTH08T230W
1.5V@6A
Eff. 87%
VL1
VS4
5.1V
VREF
A/T
PTH08000W
[email protected]
Eff. 88%
PTH08000W
[email protected]
Eff.92%
VCC LDO
TPS51200 -DDR3
0.75 @3A
Eff. 60%
TPS51200Requires
one per each Virtex 6
DDR3 VTT
0.75V@2A
I/O Ethernet Phy.
1.8V@1A
I/O SFP etc,
3.3V@1A
1V@6A
GTP Core
Rocket I/O
Low noise
5mV ripple
1.2V@6A
GTP Termination
Rocket I/O
Low noise
5mV Ripple
A/T
PTH08T240W
3.3V@4A
Eff.92%
FMC Connector
3.3V@3A
12V@1A
2
DDR3 VDD,
VCCO
A/T
PTH08T220W
PTH08T230W
1.2V@16A
1.2V@6A
Eff. 85%
87%
VS8
/Reset(All other voltages)
A/T
PTH08T220W
1.0V@16A
Eff. 83%
VS7
I/O Ethernet Phy.
VCCAUX
A/T
VS5
VS6
TPS3808G25
2.5V SVS
5ms
Delay
1.5V@2A
UVLO
16.9K
Note 3
From SVS2.5V
/Reset(All other voltages)
V
Core
VCCINT
/Reset
#2 Sequence control logic high
PTH08T240W
2.5V@10A
Eff. 90%
VS3
Power Down
Control
Virtex 6 x2 Input Power
FMC Conector
(1)
The sequence for V6 power is VCCINT (1 V), VCCAUX (2.5 V), and VCCO (1.5 V and 2.5 V). All rails
including 3.3-V rail must be last to power up.
(2)
A/T = auto track function
(3)
The power-down sequence is VCCO ( 1.5 V) power down first, VCCAUX (2.5 V) power down second. UVLO
resistor (16.9 kΩ) (1.5 V) VCCO detects input voltage droop to 8 V. VCCAUX (2.5 V ) is second detected
input voltage droop to 4.3 V.
Power Two Xilinx™ LX240 Virtex-6™ Devices
Copyright © 2010, Texas Instruments Incorporated
SLVA408 – April 2010
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