Download design project outline - Department of Electrical and Computer

A. Szeto
Fall 2002
EE 530 - DESIGN PROJECT OUTLINE
EE530 has been designated the capstone design course for analog electronics in the ECE Depa rtmen t. This course
focuses heavily on the design process using both analytical paper and pencil techniques and computer aided design using
ma inly SPICE. A sm all class size (under 30 students) will permit discussion and oral presenta tions on the design of a
fundame ntal linear integrated circuit compon ent -- the operational amplifier.
Textbooks:
Analy sis and Design of Analog Integrated Circuits, 4 th Edition, Paul R. Gray, Paul J. Hurst, Stephen
H. Lewis, and Robert G. Meyer. John Wiley & Sons, 2001.
SPICE, 2nd Edition, G. W. Roberts & A. S. Sedra, Oxford Univ. Press, 1997. (or equivalent reference)
GENERAL ORGANIZATION OF COURSE
[1]
The class will be divided into design teams of 2 or 3 students each for the entire semester. Each team will design
an operational amplifier consisting of the input, gain, and output stages. Each member of the team will be expected
to work collabora tively in this design effort.
[2]
Each design team will choose their own approach for meeting the performance specifications.
[3]
Four typed design re ports (briefly described below) w ill be required through out the se mes ter. The f irst three rep orts
will be a group effort and receive a group grade. The fourth report will be an individual effort and graded on an
individual basis. Detailed instructions for each report will be forthcoming.
[4]
Although each team member will have different abilities and preferences regarding the various design tasks
involved, every team mem ber is expected to con tribute equa lly to the over all effort because every team mem ber
will receive the sam e grade for the first thr ee repo rts. Stude nts who fail to coope rate and s hare in the w orklo ad w ill
be reported to me.
[5]
One graded oral progress report (5-7 minutes long) o f the design will be required of every student during the
semester. A representative from each design team will present a report of their work on the day that the written
report is due.
_________________________
DESIG N ASS IGNM ENT #1 -- GA IN ST AGE :
(Due Wednesday, October 2, 2002 - Week 5)
Using the transistors that have been already specified in PSPICE and described on p. 123, 130, 132, 147, and 156-158
of the text (N PN, La teral PNP , Substra te PNP , N-cha nnel JF ET, P- chann el JFET , and CM OS), d esign a CE high g ain
stage with an active loa d. This will be the primary gain block of your op amp. [Hint: Study Chapt. 4, Sec. 3 of the Gray
and M eyer Tex t.]
The specific DC voltage level at the input node of this stage and its input impedances must be coordinated with the
differential input stag e. It will be therefore necessary to do some conceptual "pre-designing" of the differential input stage
as part of your effort to design this middle gain stage.
Specifications:
Submit for Grading:
Minimum voltage gain (with a 100kS load to ground) of 1200
Maximum quiescent 2 mA collector current in the main transistor
Input impedance greater than 1 MS
V out @ 0 V DC, V C C = +15V and V EE = -15V
DC Trans fer curve (V out vs. V in) of the gain stage
Transfer curve dVout/dV in vs. V in of gain stage with 0.1mV input resolution
Bode plot of the gain stage (phase and gain on same page)
Circuit diagram and description of the gain stage
Complete hand & PSPICE calculations of the Av, R in, R out, Q pt., etc.
4-page description of circuit operation plus design rationale.
_________________________
p. 2
DESIG N ASS IGNM ENT #2 -- OU TPU T ST AGE : (Due Wednesday, October 23, 2002 - Week 8)
Specifications:
Submit for Grading:
Able to source/sink at least 20 mA of output current into R L of 650S
R out (output stage only) = 50 to 100 S with Vout = 0 VDC ± 70 m V. R in $ 200KS
Output voltage swing within 2.0 volts of DC supplies
Voltage gain $ 0.9 when Vout at 2V and -2V (check by plotting dVout/dV in vs V in)
Quiescent DC output voltage established at 0 VDC ± 70 mV
Max. tra nsistor size of 500% . 110m W max . power d issipation o f gain + ou tput.
DC Transfer curves (dVout/dV in vs. V in) of the ou tput stage alone & th e gain + o utput.
Bode plots of output stage alone and Gain+Output stages combined.
8V output step response of the Gain+output stage. Give the rise time.
Circuit diagrams of the output stage alone and Gain+Output comb.
Hand calculations that support the gain & output stage design
4-page description of how the output stage works & rationale.
Com plete SP ICE Pe rform ance S pecification s for entire circuit.
_________________________
DESIG N ASS IGNM ENT #3 -- DIF FER ENT IAL INP UT S TAG E: (Due Wednesday, November 20, 2002 - Week 12)
Specifications:
Submit for Grading:
Diffe rentia l R in > 20 MS
Common Mode input range of ± 12V. CMRR $ 100 dB with Vout at 0VDC.
Differential voltage gain $ 100 into a "dummy" gain stage load.
DC coupling of input stage to the gain & output stages
DC Trans fer curve (V out vs. Diff. V in) of the input stage alone
into a "dummy" gain stage load.
DC Transfer curve of the whole op amp with pure CM V in from -15V to +15V.
Bode plots of the input stage alone (gain and phase on same page)
Bode plot of the whole op amp (no fdbk) with Vout at 2V and -2V.
Circuit diagram of the input stage alone and combined with the gain and output stages
Comp lete hand and PSPICE calculations of A vDM & A vCM, CMR R, R in, R out, and Q pt.
5-page description of the input circuit operation & design rationale.
_________________________
DESIG N ASS IGNM ENT #4 -- CO MPLE TE O P AM P: (Due Wednesday, December 11, 2002 - Week 15)
For this part of the project, design the necessary DC bias circuits for all three stages, integrate the thre e sta ges, and
incorporate internal freq uen cy co mp ens ation to pe rm it a sta ble clo sed loop g ain of unity.
Specifications:
Submit for Grading:
Overall differential voltage gain > 100,000 with a 2 kS load
R id > 20 MS; CMRR $ 100 dB; Slew Rate $ 3 V/:S
Open loop R out of whole op amp # 150 S with Vout at 0 VDC.
Open loop unity gain $ 1.5 MHz with compensation
Frequency compensation for unity closed loop gain with a response peak # 2dB and
oversh oot #20% with Vout at +2 VDC
Max . total diffused resistance of 140KS and total chip capacitance of 50 pF.
Maximum total op amp quiescent power dissipation of 180 mW.
Cur rent o verlo ad pr otec tion s et for ±25 mA (grad uate stud ents only)
Overall differential transfer (Vout vs. V in and dV out/dV in vs. V in) curves.
Overall common mode transfer curve.
Open loop Bode plot (phase and gain) of the compensated op amp with V out at 2V and -2V.
Bode plot with maximum designed negative feedback.
Small signal step response of op amp with unity closed loop gain.
Slew Rate of op amp with unity closed loop gain.
Circuit diagram of the whole op amp with node numbers & component values.
AC and DC hand PSPICE analyses of A v, R in, R out, & bandwidth of the compensated
open loop op amp.
6-page description and design rationale for your whole op amp.
p. 3
HOW TO START SIMULATING CIRCUITS WITH SPICE
Step 1 --
Using a WEB browser, obtain your PSPICE Evaluation DOS Version by downloading it from the Dr. Szeto's Web
site (http://kahuna.sdsu.edu/engineering/electrical/faculty/andrew_szeto.html) by clicking on the EE530
box. You will need two blank formatted diskettes to store the files after unzipping them. For simulating large
circuits, you will need to use one of the five specially designated PCs in E202 that carry the full-sized DOS (nonWindows and copy protected) PSPICE for simulating up to 200 transistors.
Step 2 --
Use a text editor (not a word process or) and generate your circuit ne tlist. Check that each node is mentioned
at least twice (i.e., each nod e has two circuit eleme nts attached).
Step 3 --
Include in your PSPICE ne tlist the complete spec ifications for your various tran sistor models. A netlist ready
file called 'model.def' can be downloaded from Dr. Szeto's Web site. Click on the 'EE530' box.
Step 4 --
In your netlist, verify that the substrate capacitance of all LPNPs and the gate capacitance of a ll JFETs have
been modeled c orrectly (i.e., specify 4th node of BJT and CMOS ).
Step 5 --
Obtain a DC input-output transf er curve (with the ".DC" command) using an input step size equal to 0.01V
divided by your expected AC gain. Limit your analysis to about 2000 steps, and use a step size small enough
to yield a smooth output curve.
Step 6 --
Based on your inpu t-output transfer curve, apply the n ecessary input DC bias (V BIAS) to establish an appropriate
Q pt. for your circuit.
Step 7 --
Perform the desired a nalyses (e.g., transient, slew rate, or step responses, ga in and phase plots, e tc.).
Step 8 --
Always include the ".OP" and ". PROBE" commands in your input files so that you can check for active mode
operating conditions for your transistors and so that PSPICE will sa ve your data files for easy p ost analysis
plotting.
If you desire off-campus access to SDSU Computers, go to BAM 116 and obtain a student account and the SDSU Remote Access software.
To download software, you also will need pkzip and either a WEB browser or ftp software.
WHAT TO DO IF YOUR PSPICE SIMULATION BOMBS!!
Step 1 --
Check all your DC node voltages (PSPICE's Sm all Signal Bias) to determ ine the Q-points of all transistors. Are
they properly biased ?? To properly DC bias your circuit, run a .DC analysis with your DC input voltage varying
from its lowest probab le value to its highest (see S tep 5 above).
Step 2 --
Look (under PSPICE's Operating Point Information) at the $ and DC voltages an d currents of all transistors to
determine if any are in saturation or cut-off. Remember, excessively low or high quiescent currents cause $ to
be small. (See p. 133 of textbook.) Re-scale transistor area as needed up to 500%.
Step 3 --
Check for circuit des cription errors. Are the node numbers okay ? Have your listed the transistor nodes in the
following sequence: collector, base, and emitter ? For transistors biased below 0 VDC, their substrate nodes
must be connected to the negative supply. PSPICE's default for the 4th node is ground.
Step 4 --
Check for expo nent errors in the circuit description and transistor models. Avoid using letter abbreviations for
units unless you are sure. Note: M = 1E-3 (milli-) and MEG = 1E6.
Step 5 --
Check for mix-ups between the letter O and the number zero. Similarly check for mix-ups between the letter "l"
and the number "1."
Step 6 --
For problems with your step response outputs, have you selected a total time duration (see .TRANS section of
your SPICE Guide) that is at least 10 times larger than your anticipated rise time, wh ich is approximately 0.35/f H
?? You should also use a pulse input in the microvolt range so that the open loop gain of your amplifier will not
cause the output node to exceed its voltage swing limits. During transient analysis and DC analysis, PSPICE
will continuously check for saturation of any transistors.
Step 7 --
FAILURE TO CONVERGE: Under certain circuit conditions, PS PICE may not con verge. For mild cases of
non-convergence, specify numerical starting values in your program listing (see .NODESET command) based
on previous PSPICE outputs. For severe cases of non-convergence, break your circuit into separate stages and
use the DC node voltage s from the previous sta ge as your initial node voltages. Non-convergence may be
caused by circuit oscillations (e.g., composite PNP) too.
p. 4
Copying PSPICE and EE530 Transistor Models from the Network
using the PCs in E-200 Computer Lab (one disks needed)
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Go to the DOS prompt by double-clicking on the MS-DOS PROMPT icon .
Insert your formatted and empty disk into the 3.5" floppy drive.
Type: A: and pre ss the e nter key. {Your p rompt o n the sc reen sh ould now read A:\}
Type: ftp kahuna.sdsu.edu and press the enter key to conne ct to the UNIX server.
{Note: You are using the UNIX Operating System and UNIX is case sensitive. If the above fails, try
anothe r comp uter or try a gain later. Th e netwo rk could be dow n.}
W hen it ask s for a us ernam e type: ftp and p ress the e nter k ey.
W hen it ask s for a pa sswor d type : ee530 and p ress the e nter k ey.
W hen it finishe s flashing inform ation onto the scre en type: cd pub and p ress the e nter k ey.
Then type: cd ee530 and pre ss the e nter key. {To abo rt from the UNIX environm ent, enter C TRL- C.}
Then type: bi and p ress the e nter k ey to s et the trans fer typ e to b inary.
Then type: prompt and press the enter key to turn off the prompting. If you wish to specify a subdirectory on your
diskette, enter lcd A:\subd irectory.
Then type: mget * and press enter to transfer the "model.def" files to your disk in the floppy drive.
W hen the tra nsfer is c omp lete type: exit and remove your disk from the floppy drive.
If you have finished, continue with to Step 34 below.
Copying PSPICE from the Network (two disks needed)
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From the C:> prompt, insert your first of two formatted and empty disks into the 3.5" floppy drive.
Type: A: and p ress the e nter k ey.
Your prompt on the screen should now read A:\>.
Type: ftp kahuna.sdsu.edu and p ress the e nter k ey.
{Note: You are using the UNIX Operating System and UNIX is case sensitive. If the above fails try
anothe r comp uter or try a gain later. Th e netwo rk could be dow n.}
W hen it ask s for a us ernam e type: ftp and p ress the e nter k ey.
W hen it ask s for a pa sswor d type : pspice and p ress the e nter k ey.
W hen it finishe s flashing inform ation onto the scre en type: cd pub and p ress the e nter k ey.
Then type: cd pspice and pre ss the e nter key. {To abo rt from the UNIX environm ent, enter C TRL- C.}
Then type: cd disk1 and p ress the e nter k ey.
Then type: bi and p ress the e nter k ey to s et the trans fer typ e to b inary.
Then type: prompt and press the enter key to turn off the prompting.
Then type: mget * and press enter to transfer the files to your disk in the floppy drive.
{This tran sfer can take from 5 to 10 m inutes.}
When it is finished transferring take out your first disk and put in the second one.
Then type: cd .. and pre ss ente r. Rem emb er the sp ace be tween th e "cd" and the ".."
Then type: cd disk2 and press enter.
Then type: mget * and press enter.
{This tran sfer can take 5 to 1 0 minute s.}
W hen the tra nsfer is c omp lete type: exit and remove your disk from the floppy drive.
Type C: and press the enter key. You should be back on the C: drive and able to leave the system.