Download NTE74LS196 Integrated Circuit TTL − Presettable

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Transcript
NTE74LS196
Integrated Circuit
TTL − Presettable Decade Counter/Latch
Description:
The NTE74LS196 is a high−speed monolithic decade counter in a 14−Lead plastic DIP type package
consisting of four DC coupled, master−slave flip−flops which are internally interconnected to provide
a divide−by−two and a divide−by−five counter. This device is fully programmable; that is, the outputs
may be preset to any state by placing a low on the count/load input and entering the desired data at
the data inputs. The outputs will change to agree with the data inputs independent of the state of the
clocks.
During the count operation, transfer of information to the outputs occurs on the negative−going
edge of the clock pulse. The NTE74LS196 features a direct clear which when taken low sets all
outputs low regardless of the state of the clocks.
The NTE74LS196 may also be used as a 4−bit latch by using the count/load input as the strobe and
entering data at the data inputs. The outputs will directly follow the data inputs when the count/load
is low, but will remain unchanged when the count/load is high and the clock inputs are inactive.
All inputs are diode−clamped to minimize transmission−line effects and simplify design and are
compatible with most TTL logic families.
Features:
D Fully Programmable
D Fully Independent Cleat Input
D Input Clamping Diodes Simplify System Design
D Output QA Maintains Full Fan−Out Capability in Addition to Driving Clock−2 Input
Absolute Maximum Ratings: (Note 1)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
DC Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Interemitter Voltage (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80mW
Operating Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Note 1. Unless otherwise specified, all voltages are referenced to GND.
Note 2. This is the voltage between two emitter of a multiple−emitter transistor. For this circuit, this
rating applies between th clear and count/load inputs.
Recommended Operating Conditions:
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VCC
4.75
5.0
5.25
V
High−Level Output Current
IOH
−
−
−400
A
Low−Level Output Current
IOL
−
−
8
mA
0
−
30
MHz
0
−
15
MHz
20
−
−
ns
Clock−2 Input
30
−
−
ns
Clear
15
−
−
ns
Load
20
−
−
ns
10
−
−
ns
10
−
−
ns
15
−
−
ns
30
−
−
ns
50
−
−
ns
0
−
+70
C
Count Frequency
Clock−1 Input
fclock
Clock−2 Input
Pulse Width
Clock−1 Input
tw
Input Hold Time, High or Low Level Data
th
Input Setup Time
High−Level Data
tsu
Low−Level Data
Count Enable Time (Note 3)
Clock 1
tenable
Clock 2
Operating Temperature Range
TA
Note 3. .Minimum count enable time is the interval immediately preceding the negative−going edge
of the clock pulse during which interval the count/load and clear inputs must both be high
to ensure counting.
Electrical Characteristics: (Note 4, Note 5)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
High−Level Input Voltage
VIH
2
−
−
V
Low−Level Input Voltage
VIL
−
−
0.8
V
Input Clamp Voltage
VIK
VCC = MIN, II = −18mA
−
−
−1.5
V
High Level Output Voltage
VOH
VCC = MIN, VIH = 2V, VIL = MAX, IOH = -400A
2.7
3.4
−
V
Low Level Output Voltage
VOL
VCC = MIN, VIH = 2V,
VIL = MAX, Note 6
IOL = 4mA
−
0.25
0.4
V
IOL = 8mA
−
0.35
0.5
V
VCC = MAX, VI = 5.5V
Data, Count/Load
−
−
0.1
mA
Clear, Clock 1
−
−
0.2
mA
Clock 2
−
−
0.4
mA
Data, Count/Load
−
−
20
A
Clear, Clock 1
−
−
40
A
Clock 2
−
−
80
A
Input Current
High Level Input Current
II
IIH
VCC = MAX, VI = 2.7V
Note 4. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 5. All typical values are at VCC = 5V, TA = +25C.
Note 6. QA outputs are tested at specified IOL plus the limit value of IIL for the clock−2 input. This permits driving the clock−2 input while maintaining full fan−out capability.
Electrical Characteristics (Cont’d): (Note 4, Note 5)
Parameter
Symbol
Low Level Input Current
IIL
Test Conditions
VCC = MAX, VI = 0.4V
Min
Typ
Max
Unit
Data, Count/Load
−
−
−0.4
mA
Clear
−
−
−0.8
mA
Clock 1
−
−
−2.4
mA
Clock 2
−
−
−2.8
mA
Short−Circuit Output Current
IOS
VCC = MAX, Note 7
−20
−
−100
mA
Supply Current
ICC
VCC = MAX, Note 8
−
16
27
mA
Note 4. .For conditions shown as MIN or MAX, use the appropriate value specified under “Recommended
Operation Conditions”.
Note 5. All typical values are at VCC = 5V, TA = +25C.
Note 7. Not more than one output should be shorted at a time, and the duration of the short−circuit
should not exceed one second.
Note 8. ICC is measured with all inputs grounded and all outputs open.
Switching Characteristics: (VCC = 5V, TA = +25C unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
30
40
−
MHz
Maximum Count Frequency
(From Clock 1 Input to QA Output)
fmax
Propagation Delay Time
(From Clock 1 Input to QA Output)
tPLH
−
8
15
ns
tPHL
−
13
20
ns
Propagation Delay Time
(From Clock 2 Input to QB Output)
tPLH
−
16
24
ns
tPHL
−
22
33
ns
Propagation Delay Time
(From Clock 2 Input to QC Output)
tPLH
−
38
57
ns
tPHL
−
41
62
ns
Propagation Delay Time
(From Clock 2 Input to QD Output)
tPLH
−
12
18
ns
tPHL
−
30
45
ns
Propagation Delay Time
(From A, B, C, D Input to QA, QB, QC, QD Output)
tPLH
−
8
15
ns
tPHL
−
13
20
ns
Propagation Delay Time
(From Load Input to Any Output)
tPLH
−
27
41
ns
tPHL
−
30
45
ns
Propagation Delay Time
(From Clear Input to Any Output)
tPHL
−
34
51
ns
RL = 2k,
CL = 15pF
Pin Connection Diagram
LOAD 1
14 VCC
QC 2
C 3
13 CLR
12 QD
A 4
11 D
QA 5
10 B
CLK 2 6
9 QB
GND 7
8 CLK 1
14
8
1
7
.300 (7.62)
.785 (19.95) Max
.200
(5.08)
Max
.100 (2.45)
.600 (15.24)
.099 (2.5) Min