Download the 18f2550 usb connection

THE 18F2550 USB CONNECTION
(003)
About UOWN, and Buffer Descriptor Offsets:
usb_defs.inc
………
……..
#define USB_Buffer 0x0480
#define
UOWN
; Register location after last buffer descriptor register
0x07
; offsets from the beginning of the Buffer Descriptor
#define BYTECOUNT
0x01
#define ADDRESSL
0x02
#define ADDRESSH
0x03
……..
………
#define USB_Buffer 0x0480 ; Register location after last buffer descriptor register
The registers in Bank 4 are used specifically for endpoint buffer control in a structure
known as the Buffer Descriptor Table (BDT). This provides a flexible method for users
to construct and control endpoint buffers of various lengths and configuration.
At a minimum, the BDT must be at least 8 bytes long. This is because the USB
specification mandates that every device must have Endpoint 0 with both input and
output for initial setup.
If the endpoint corresponding to a particular BD is not enabled, its registers are not
used. Instead of appearing as unimplemented addresses, however, they appear as
available RAM.
As with any address in the data memory space, the BD registers have an indeterminate
value on any device Reset.
If two endpoints are used, it does not mean that endpoint0 and endpoint1 are used; it
means that an ENPOINT0 OUT (one endpoint) and an ENPOINT0 IN (one more
endpoint) are used. The code of course is not restricted to two endpoints; up to 32
(endpoint0 out - endpoint0 in, through enpoint15 out - endpoint15 in) might be used
depending on the USB configuration. Of course Endpoint 0 is always used, as control,
so minimum two endpoints must be used.
Note that the same register UEPn: USB ENDPOINT n CONTROL REGISTER (UEP0
THROUGH UEP15) is used to define the n OUT an n IN endpoint, by means of its
configuration bits. There are not 32 physical registers just 16 (0 to 15).
Since 32 endpoints are defined (using 4 locations for each one <32x4=128 (0x0400 to
0x047F)>, the next following location is 0x0480 (Register location after last buffer
descriptor register).
What should it be written in those locations, and How?
It all depends on the kind of information to be transmitted or received at the particular
moment.
First of all, lets see what it is to be written in the endpoint´s BDs.
The BDT is composed of Buffer Descriptors (BD) which are used to define and control
the actual buffers in the USB RAM space.
Each BD, in turn, consists of four registers:
• BDnSTAT: BD Status register
• BDnCNT: BD Byte Count register
• BDnADRL: BD Address Low register
• BDnADRH: BD Address High register
Buffer descriptors not only define the SIZE of an endpoint buffer, but also
determine its configuration and control. Most of the configuration is done with the
BD Status register, BDnSTAT. Each BD has its own unique and correspondingly
numbered BDnSTAT register.
Because the buffers and their BDs are shared between the CPU and the USB module, a
simple semaphore mechanism is used to distinguish which is allowed to update the BD
and associated buffers in memory.
This is done by using the UOWN bit (BDnSTAT<7>) as a semaphore to distinguish
which is allowed to update the BD and associated buffers in memory.
When UOWN is clear, the BD entry is “owned” by the microcontroller core. When the
UOWN bit is set, the BD entry and the buffer memory are “owned” by the USB
peripheral.
Prior to placing ownership with the USB peripheral, the user can configure the
basic operation of the peripheral through the BDnSTAT bits. During this time, the
byte count and buffer location registers can also be set.
When UOWN is set, the user can no longer depend on the values that were written
to the BDs. From this point, the SIE updates the BDs as necessary, overwriting the
original BD values. The BDnSTAT register is updated by the SIE with the token PID
and the transfer count, BDnCNT, is updated.
UOWN is the only bit that is shared between the two configurations of BDnSTAT.
bit 7 UOWN: USB Own bit
0 = The microcontroller core owns the BD and its corresponding buffer
This bit must be initialized by the user to the desired value prior to enabling the
USB module.
The SIE will clear the UOWN bit when a transaction has completed (The only
exception to this is when KEN is enabled and/or BSTALL is enabled).
When UOWN = 0, the microcontroller core owns the BD. At this point, the other seven
bits of the register take on control functions.
The Keep Enable bit, KEN (BDnSTAT<5>), determines if a BD stays enabled. It
should only be enabled (KEN=1) when the Streaming Parallel Port is selected as the
data I/O channel instead of USB RAM.
The Address Increment Disable bit, INCDIS (BDnSTAT<4>), controls the SIE’s
automatic address increment function (bit 4 INCDIS: Address Increment Disable bit
=0 = Address increment enabled). The starting address location would be determined by
the BDnADRL: BD Address Low register, and BDnADRH: BD Address High register,
being the quantity of locations (bytes) to be transmitted or received determined by
BDnCNT: BD Byte Count register and bit 1-0 BC9:BC8 (Byte Count 9 and 8 bits) of
BDnSTAT register.
The byte count bits represent the number of bytes that will be transmitted for an IN
token or received during an OUT token. Together with BC<7:0>, the valid byte counts
are 0-1023. The BD9:BD8 bits (BDnSTAT<1:0>) store the two most significant digits
of the SIE byte count; the lower 8 digits are stored in the corresponding BDnCNT
register.
For example (OUT transaction), if eight (8) bytes are to be the BDnCOUNT for
endpoint0 out, we may find (genhid.asm):
movlw
movwf
movlw
movwf
movlw
movlw
movwf
1
0x08
BD0OBC, BANKED
low USB_Buffer
BD0OAL, BANKED
high USB_Buffer
0x88
; set UOWN bit (USB can write)
BD0OST, BANKED
0
0
0
1
0
0
0
The BDnSTAT byte of the BDT should always be the last byte updated when
preparing to arm an endpoint.
Keep in mind that an OUT transaction means from HOST to PIC, and an IN
transaction means from PIC to HOST.
The starting address where the HOST will write to PIC is determined by the values
written in BDnADRL: BD Address Low register and BDnADRH: BD Address High
register.
To simplify the procedure (for a feasible ping pong configuration), an OFFSET is used
for the BYTECOUNT, ADDRESSL and ADDRESSH bytes (usb_defs.inc):
; offsets from the beginning of the Buffer Descriptor
#define BYTECOUNT
0x01
#define ADDRESSL
0x02
#define ADDRESSH
0x03
genhid.asm defines the USB buffer data, where the information is to be written:
USB_buffer_data
res
8
As seen it is limited (by software) to eight bytes.
Going back to Main:
APPLICATION
code
Main
banksel COUNTER
for COUNTER, 0x01, 0x1E
next COUNTER
movlw
0xC7
movwf
T0CON, ACCESS
call
InitUSB
; do nothing for a little while
; set prescaler for Timer0 for 1:256 scaling (Timer0 will go off every 10.9 ms)
; initialize the USB registers and serial interface engine
Lets see what the InitUSB is about (as far as it is concerned with the main USB
configuration registers):
InitUSB
clrf
clrf
movlw
movwf
UIE, ACCESS
UIR, ACCESS
0x14
UCFG, ACCESS
; mask all USB interrupts
; clear all USB interrupt flags
; configure USB for FULL-speed transfers and to use the on-chip
; transciever and pull-up resistor
movlw
0x08
movwf
UCON, ACCESS
…………..
…………..
clrf
UIE, ACCESS
0
clrf
0
; mask all USB interrupts
0
UIR, ACCESS
0
0
; enable the USB module and its supporting circuitry
0
0
0
0
0
0
0
; clear all USB interrupt flags
0
movlw 0x14
movwf
UCFG, ACCESS
0
0
0
; configure USB for FULL-speed transfers and
;to use the on-chip transciever and pull-up
; resistor
0
0
0
1
0
1
0
0
bit 7 UTEYE= 0 = Eye pattern test disabled: USB Eye Pattern Test Enable bit
bit 6 UOEMON= 0 = UOE signal inactive: USB OE Monitor Enable bit
bit 4 UPUEN=1 = On-chip pull-up enabled (pull-up on D+ with FSEN = 1 or D- with
FSEN = 0): USB On-Chip Pull-up Enable bit
bit 3 UTRDIS=0 = On-chip transceiver active: On-Chip Transceiver Disable bit
bit 2 FSEN=1 = Full-speed device (pull up, internal <on chip> resistor on D+):
controls transceiver edge rates; requires input clock at 48 MHz: Full-Speed Enable bit
movlw 0x08
movwf
UCON, ACCESS
; enable the USB module and its supporting
; circuitry
0
0
0
0
1
0
bit 3 USBEN: USB Module Enable bit
1 = USB module and supporting circuitry enabled (device attached)
0
0
The overall operation of the USB module is controlled by the USBEN bit
(UCON<3>). Setting this bit activates the module and resets all of the PPBI bits in the
Buffer Descriptor Table to ‘0’. This bit also activates the on-chip voltage regulator and
connects internal pull-up resistors, if they are enabled. Thus, this bit can be used as a
soft attach/detach to the USB. ALTHOUGH ALL STATUS AND CONTROL
BITS ARE IGNORED WHEN THIS BIT IS CLEAR, THE MODULE NEEDS TO
BE FULLY PRECONFIGURED PRIOR TO SETTING THIS BIT.
Also, before setting UOWN (UOWN=1), an appropriate and meaningfull information
must be provided in BDT, for enumeration (setup phase) process or regular operations
on USB pipes.