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Design of a Near Threshold Low Power
DLL for Multiphase Clock Generation
and Frequency Multiplication
Mehdi Sadi,
Italo Armenti
Outline
Introduction and Motivation
2. Background
3. Our Works and simulations
4. Conclusions and Future Works
1.
Introduction and Motivation
 Delay Locked Loops (DLL) are extensively used for multiphase
clock generation in SoC and in clock and data recovery circuits.
 DLL`s counterpart Phase Locked Loops(PLL) suffer from
instability due to PVT variation and noise.
 Very few researchers have looked into the effect of voltage
scaling on DLL performance .
Design Challenges
Design challenges when voltage supply is scaled down
 Appropriate device sizes in the critical path,
 Ensuring correct duty cycle at output frequency.
 Keeping static phase error within bounds.
Background
(Mesgardazeh et. al)
 Possible to redesign
with reduced components but same
performance at operating frequency.
Block diagram
Phase Detector
 C2MOS DFF with Reset option.
 Critical path devices are sized to ensure
faster charging and discharging at the
desired frequency range.
Freq
Minimum
Resolution
Power(uW)
1GHz
45p
40
700M
55p
39.88
500M
55p
39.63
200M
55p
39.63
100M
55p
39.62
VDD
D
Reference
Other
signal
CLK
Lead
Reset
Stable
Control
Signal
Generator
VDD
D
Other signal
CLK
Reference
Reset
Lag
Up/Down~
Delay Line
Input Signal to
be delayed
Stage 1
Buffer
Stage 2
Buffer
Stage 8
Buffer
Delayed Output
Cap
Capacitance in f F
600

Binary weighted switched capacitors control the delay per stage.
500
400
300
200
100
0
0
50
100
150
200
250
Control word (Equivalent Decimal Value)
**
Delay Line Design
 Delay per stage,
 At lock in condition
The switching voltage should be adjusted at
VDD/2 to avoid duty cycle error.
Counter
 8 bit binary up down counter with reset and hold options.
 The counter is power and clock gated to reduce power when the clock phases are
aligned.
 During Sleep mode the counting states are held in a latch.
Gating Effect Started
Power without gating = 9.1uW
Power with gating = 2.72 uW
70 % Power saved with gating
Edge Combiner
 XOR Gate Based Edge Combiner. Generates 4 times the reference frequency
 To ensure proper duty cycle the Devices in the critical path must be sized properly.
Sizing also depends on operating frequency range.
Full Waveform
Process Variation
Process Corner
Static Phase error
(ps)
Lock in time at 200 MHz
TT
50
50 cycles
SS
55
55 cycles
FS
47
50 cycles
SF
45
50 cycles (also duty cycle mismatch)
FF
45
60 cycles
Performance
This work
IEEE Tran 08
JSSC 09
VLSI Symp 07
Type
All Digital
Digital
Digital
Digital
Process
45nm
0.35 um
90nm
0.13um
Supply
0.7V
3.3V
1V
1.2V
Frequency
Range
Static Phase
Error
Lock in time
80 MHZ - 200MHz
4 -200MHz
2GHz
1.6GHz
N/A
N/A
N/A
Between 28 to
110 Cycles
16 cycles
N/A
N/A
Power
120uW
17mW
7mW
6mW
55ps
Conclusion
 We have designed a ultra low power all digital DLL operating
at 80 -200MHz with 0.7V supply and 120uW.
 The DLL can be scaled down to operate at further low
voltage by adjusting the critical path device widths
Thank You