Download Powering i.MX35 using TPS650250

Reference Guide
SLVU343 – April 2010
Power Supply Reference Design for Freescale™i.MX35
Using TPS650250
This application report details the power supply requirements of the Freescale™ i.MX35 processor, and
how to design with the TPS650250.
1
Features
•
•
•
•
•
•
2
TPS650250 highly integrated Power Management Unit
3.3V to 6.0V input voltage range
Simple voltage scaling using external circuit
Output Current Up to 1600mA
Up to 97% Efficiency
Small 5 mm x 5mm 32 pin QFN package
Introduction
This reference design applies for the Freescale™ i.MX35 processor family. It provides all required the
analog and logic supply rails and the correct sequencing to power up a Freescale™ i.MX35 processor.
3
Requirements
Table 1. Power Requirements of the Freescale™ i.MX35 Processor
Pin Name
I/O
Core
Voltage
Imax [mA]
MVDD, PVDD
1.5
20
QVCC (0 < fARM < 400MHz)
1.3
QVCC (0 < fARM < 532MHz)
1.4
400
Tolerance
Sequencing
Order
Timing
Delay
n/a
–6%, +10%
2
–6.2%, +13%
1
-5.4%, + 5%
1
n/a
I/O
NVCC_EMI1,
NVCC_EMI2,
NVCC_EMI_3,
NVCC_LCDC,
NVCC_NFC
1.8 / 3.3
90
–5%, +10%
1
n/a
I/O
NVCC_MISC,
NVCC_SDIO,
NVCC_CRM,
NVCC_ATA,
NVCC_MLB,
NVCC_JTAG
1.8 / 3.3
60
±5%
1
n/a
I/O
OSC24M_VDD,
OSC_AUDIO_VDD,
PHY1_VDDA,
PHY2_VDD,
USBPHY1_UPLLVDD,
USBPHY1_VDDA_BIAS
3.3
25
±9%
2
n/a
FUSE_VDD (this rails is typ. Tied
to GND, it is only needed if in
system fuse burning is needed)
3.6
25
±5%
2
n/a
Fuse
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Requirements
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Table 2. MCIMX35 Operating Ranges
Symbol
VDD
Parameter
Typ
Max
Unit
Core operating voltage, 0 < fARM < 400 MHz
1.22
1.47
V
Core operating voltage, 0 < fARM < 532 MHz
1.33
1.47
V
State retention voltage
(1)
1
V
NVCC_EMI1,2,3
EMI
1.7
3.6
V
NVCC_CRM
WTDG, Timer, CCM, GPIO, CSPI1
1.75
3.6
V
NVCC_NANDF
NANDF
1.75
3.6
V
NVCC_ATA
ATA, USB generic
1.75
3.6
V
NVCC_SDIO
eSDHC1
1.75
3.6
V
NVCC_CSI
CSI, SDIO2
1.75
3.6
V
NVCC_JTAG
JTAG
1.75
3.6
V
NVCC_LCDC
LCDC, TTM, I2C1
1.75
3.6
V
NVCC_MISC
I2Xx2, ESAI, I2C2, UART2, UART1, FEC
1.75
3.6
V
NVCC_MLB (2)
MLB
1.75
3.6
V
PHY1_VDDA
USB OTG PHY
3.17
3.3
3.43
V
USBPHY1_VDDA_BIAS
USB OTG PHY
3.17
3.3
3.43
V
USBPHY1_UPLLVDD
USB OTG PHY
3.17
3.3
3.43
V
PHY2_VDD
USB HOST PHY
3.17
3.3
3.43
V
OSC24M_VDD
OSC24M
3.0
3.3
3.6
V
OSC_AUDIO_VDD
OSC_AUDIO
3.0
3.3
3.6
V
MVDD
MPLL
1.4
1.65
V
PVDD
PPLL
1.4
1.65
V
FUSE_VDD (3)
Fusebox program supply voltage
3.0
TA
Operating ambient temperature range
–20
(1)
(2)
(3)
3.1
Min
3.6
3.6
V
70
°C
EMI I/O interface power supply should be set up according to external memory. For example, if using SDRAM then
NVCC_EMI1,2,3 should all be set at 3.3 V (typ). If using MDDR or DDRe, NVC_EMI1,2,3 must be set at 1.8 V (typ).
MLB interface I/O pads can be programmed to function as GPIO for the consumer and industrial parts by settling NVCC_MLB to
1.8 or 3.3 V. NVCC_MLB can be left floating.
The Fusebox read supply is connected to supply the full speed USBPHY.FUSE_VDD is only used for programming. It is
recommended that FUSE_VDD be connected to ground when not being used for programming.
Power Up Sequencing
The i.MX35 processor consists of four major sets of the power supply voltages: digital logic domains
(VDDn), I/O power supplies (NVDDx), analog power supplies, and the fuse voltage supply (FUSEVDD).
These voltage domains can be grouped together, depending on the operating mode and needs of the
i.MX35 processor, and the specific application.
Recommended power sequence for the processor is as shown below:
1. Assert POR (POR = Low)
2. Turn on the digital logic domain and I/O power supplies (VDDn, NVCCx)
3. Wait until VDDn, NVCCx power supplies are stable + 32 µs
4. Turn on all other power supplies
5. Negate the POR signal (POR = High)
3.2
Power Down Sequencing
The power up sequence in reverse is recommended for power down, however all supplies can be shut
down at the same time.
2
Power Supply Reference Design for Freescale™i.MX35 Using TPS650250
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Powering Freescale™ i.MX35 using TPS650250
The TPS650250 is an integrated Power Management IC for applications powered by one Li-Ion or
Li-Polymer cell, which require multiple power rails.
The TPS650250 provides three highly efficient, step-down converters targeted at providing the core
voltage, peripheral, I/O and memory rails in a processor based system. All three step-down converters
enter a low power mode at light load for maximum efficiency across the widest possible range of load
currents.
The functional block diagram of the TPS650250 is shown in Figure 1.
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TPS650250
1R
VCC
Vbat
1 mF
VINDCDC1
Vbat
DCDC1 (I/O)
10 mF
STEP-DOWN
CONVERTER
1600 mA
EN_DCDC1
ENABLE
VINDCDC2
Vbat
DCDC2
(memory)
10 mF
STEP-DOWN
CONVERTER
800 mA
EN_DCDC2
ENABLE
VINDCDC3
Vbat
3.3 V / 2.8 V
or adjustable
L1
2.2 mH
VDCDC1
R1
22 mF
DEFDCDC1
PGND1
R2
2.5 V / 1.8 V
or adjustable
L2
2.2 mH
VDCDC2
R3
22 mF
DEFDCDC2
PGND2
R4
L3
10 mF
DCDC3 (core)
2.2 mH
VDCDC3
DEFDCDC3
ENABLE
STEP-DOWN
CONVERTER
800 mA
EN_DCDC3
PGND3
R5
22 mF
R6
MODE
PWM/ PFM
VIN_LDO
VIN
VLDO1
200 mA LDO
EN_LDO
ENABLE
VLDO1
FB_LDO1 R7
2.2 mF
R8
VLDO2
200 mA LDO
VLDO2
FB_LDO2 R9
R10
EN_Vdd_alive
ENABLE
VCC
Vbat
2.2 mF
VLDO3
30 mA LDO
Vdd_alive
1V
2.2 mF
R11
I/O voltage
PWRFAIL_SNS
R12
-
PWRFAIL
R19
+
Vref = 1 V
AGND1
AGND2
Figure 1. TPS650250 Functional Block Diagram
According to the recommended Power-Up sequence given in section 3.1 a power-up sequence consisting
of two groups was selected and realized in this power reference design. The first group consists of all rails
supplied by DCDC1, DCDC2 and the LDO LDO1. The second group contains LDO3 and LOD3 and
LDO4.
4
Power Supply Reference Design for Freescale™i.MX35 Using TPS650250
Copyright © 2010, Texas Instruments Incorporated
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Table 3. TPS650250 assignment of Converter Output rails
Supply Rail
Voltage [V]
TPS65051 Output
Sequencing Order
VCC
Core
1.0V / 1.4V
DCDC3
1
NVCC
I/O
1.8
DCDC2
1
USB OTG PHY
USB HOST PHY
OSC24M
OSC_AUDIO
I/O
3.3
DCDC1
2
MVDD
PVDD
I/O
1.5
LDO1
2
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Figure 2. Reference Design Schematic
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Power Supply Reference Design for Freescale™i.MX35 Using TPS650250
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Measurement Results
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Table 4. Bill of Materials
Count RefDes
5
Value
Description
Size
Part Number
MFR
2
C1, C5
1.0 µF
Capacitor, Ceramic, 6.3V, X5R,10%
0603
C1608X5R0J105K
TDK
3
C12–C14
2.2 µF
Capacitor, Ceramic, 6.3V, X5R, 10%
0603
C1608X5R0J225K
TDK
1
C16
10 nF
Capacitor, Ceramic, 6.3V, X5R,10%
0603
C1608X5R0J105K
TDK
9
C2–C4,
C6– C11
10 µF
Capacitor, Ceramic, 6.3V, X5R, 10%
0805
C2012X5R0J106K
TDK
2
L1, L3
2.2 µH
Inductor, SMT, 1.72A, 59milliohm
0.157 x 0.157 inch
VLCF4020T-2R2N1R7
TDK
1
L2
3.3 µH
Inductor, SMT, 1.52A, 78milliohm
0.157 x 0.157 inch
VLCF4020T-3R3N1R5
TDK
1
Q1
MOSFET, Nch
SOT23
Std
Std
2
R10, R17
200k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R16
40.2k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R18
90.9k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R19
182k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R21
68k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R22
330k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R4
1
Resistor, Chip, 1/16W, 5%
0603
Std
Std
1
R5
1.0M
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R6
470k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
R7
0
Resistor, Chip, 1/16W, 1%
0603
2
R8, R11
301k
Resistor, Chip, 1/16W, 1%
0603
1
R9
100k
Resistor, Chip, 1/16W, 1%
0603
Std
Std
1
U1
TPS650250RHB IC, Power Management ICs for Li-Ion
Powered Systems
QFN-32
TPS650250RHB
TI
Measurement Results
Figure 3. Start-up
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Measurement Results
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Figure 4. Voltage Scaling 1.3V to 1.0V
Figure 5. Voltage Scaling 1.0V to 1.3V
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Power Supply Reference Design for Freescale™i.MX35 Using TPS650250
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Measurement Results
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100
90
VI = 3.8 V
80
Efficiency - %
70
VI = 4.2 V
VI = 5 V
60
50
40
30
TA = 25°C,
VO = 3.3 V,
PFM/PWM Mode
20
10
0
0.1
1
10
100
1k
IO - Output Current - mA
10k
Figure 6. Efficiency DCDC1
VI = 2.5 V
Efficiency - %
VI = 3.8 V
VI = 4.2 V
VI = 5 V
TA = 25oC
VO = 1.8 V
PWM / PFM Mode
0.01
0.1
1
10
100
1k
10 k
IO - Output Current - mA
Figure 7. Efficiency DCDC2
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References
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100
TA = 25°C,
90 VO = 1.5 V,
PWM/PFM Mode
80
Efficiency - %
70
VI = 2.5 V
60
VI = 3 V
50
VI = 3.8 V
40
30
VI = 4.2 V
20
VI = 5 V
10
0
0.01
0.1
1
10
100
IO - Output Current - mA
1k
Figure 8. Efficiency DCDC3
6
References
1. i.MX35 data sheet from Freescale Semiconductor, MCIMX35SR2CEC,REV2 ,2/2009
2. TPS650250 datasheet from Texas Instruments (SLVS843A), December 2008
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