Download ASCI mode of operation for a single

Current Source Inverter
Load-Commutated CSI
, ASCI mode of operation for a single-phase Current Source Inverter (CSI) was presented. Two commutating
capacitors, along with four diodes, are used in the above circuit for commutation from one pair of thyristors to the
second pair. Earlier, also in VSI, if the load is capacitive, it was shown that forced commutation may not be needed.
The operation of a single-phase CSI with capacitive load (Fig. 40.1) is discussed here. It may be noted that the
capacitor, C is assumed to be in parallel with resistive load (R). The capacitor, C is used for storing the charge, or
voltage, to be used to force-commutate the conducting thyristor pair as will be shown. As was the case in the last
lesson, a constant current source, or a voltage source with large inductance, is used as the input to the circuit.
The power switching devices used here is the same, i.e. four thyristors only in a full- bridge configuration. The
positive direction for load current and voltage, is shown in Fig. 40.1. Before t = 0, the capacitor voltage is , i.e. the
capacitor has left plate negative and right plate positive. At that time, the thyristor pair, Th C −= Vv 1 2 & Th4 was
conducting. When (at t = 0), the thyristor pair, Th1 & Th3 is triggered by the pulses fed at the gates, the conducting
thyristor pair, Th2 & Th4 is reverse biased by the capacitor voltage C = −Vv 1 , and turns off immediately. The
current path is through Th1, load (parallel combination of R & C), Th3, and the source. The current in the thyristors
is Iii , the output current is ThTh 31 == Iiac = ; the capacitor voltage, changes from to , as the capacitor gets charged
by the current during the time, . The load voltage is . Thus, the waveform of the current, Cv −V1 V1 Ci tT >> 0)2/( C
= vv0 )/()/( 00 RvRvi = = C through load resistance, R has the same nature as that of (Fig. 40.2). Similarly, when (at ),
the thyristor pair, Th Cv = Tt 2/ 2 & Th4 is triggered by the pulses fed at the gates, the conducting thyristor pair,
Th1 & Th3 is reverse biased by the capacitor voltage C = Vv 1 , and turns off immediately. The current path is
through Th2, load (parallel combination of R & C), Th4, and the source. The current in the thyristors is IiiTh = Th42
= , but the output current is ; the capacitor voltage, changes from to , as the capacitor gets charged by the current
during the time, . Iiac −= Cv V1 −V1 Ci >> TtT )
Various current and voltage waveforms during one cycle , are shown in Fig. 40.2. At t = 0, the capacitor voltage is tT
>> 0 C = −Vv 1 , then 0 = C = −Vvv 1 , and the load current through R is . As stated earlier, during the time , the
capacitor gets charged, with its voltage changing from 0 1 1 )/( −=−= IRVi tT >> 0)2/( −V1 to . So, At V1 = Tt 2/ , the
load current is . The input voltage is 0 0 1 1 )/()/()/( IRVRvRvi C ==== 0 vvin = , during , and , during . tT >> 0)2/( 0
vvin −= >> TtT )2/( It may be observed that, when the thyristor pair, Th1 & Th3 is conducting for , the currents are
leaving node A (Fig. 40.1), and the current, I is entering node A. Therefore, the equivalent circuit for , is shown in
Fig. 40.3a. The current in node A, is or, . At t = 0, tT >> 0)2/( 0 , iiC tT >> 0)2/( IiiC 0 =+ 0iIiC −= 10 = −Ii , and 1IIiC = +
. The mathematical steps for a steady solution of the output current, and other parameters, such as input voltage
etc., are given later. Just after (T/2), when the thyristor pair, Th2 & Th4 is conducting, the currents are entering
node B (Fig. 40.1), and so also the current, I. The equivalent circuit for , is shown in Fig. 40.3b. The current in node
B is 0 , iiC >> TtT )2/( C + 0 + Iii = 0 or, )( 0iIiC = − + . At t = (T/2), , and . The cycle repeats itself.