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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on October 7, 2002 by Leland Chang ([email protected])
Borivoje Nikolic
Homework #5
EECS 141
Solutions
Problem 1 – Self-loaded Inverter Delay
a) Use HSPICE to find the average propagation delay (average of low-high and
high-low transitions) for an inverter in this process for a fanout of 1, 2, 3, and 4.
The following SPICE deck works… To be entirely correct, you could calculate
the actual perimeter/area for an actual device layout. This would change your
delays and your values for Cd. Here, we just use whatever default capacitances
SPICE assumes…
************************************************************************
* ee141 hw5: 4-stage inverter chain
.param cload='20f'
.param fanout='4'
.lib '/home/ff/ee141/MODELS/g25.mod' TT
************************************************************************
* inverter
.subckt inv in out vdd gnd
m1 out in gnd gnd nmos w=1u l=.25u
m2 out in vdd vdd pmos w=2u l=.25u
.ends
************************************************************************
* inverter plus capacitive load at output
.subckt invcap in vdd gnd
x1 in out vdd gnd inv
c1 out 0 'cload'
.ends
************************************************************************
* load inverter plus fanout
.subckt invload in vdd gnd
x1 in out1 vdd gnd inv
x2 out1 vdd gnd invcap m='fanout'
.ends
************************************************************************
* main deck
* 4-stage inverter chain
x1 stepin in vdd 0 inv
x2 in out vdd 0 inv
x3 out out2 vdd 0 inv
x4 out2 vdd 0 invcap m='fanout'
* loading inverters
x2load in vdd 0 invload m='fanout-1'
x3load out vdd 0 invload m='fanout-1'
* voltage sources
vdd vdd 0 dc 2.5
vin stepin 0 pulse (0 2.5 100p 200p 200p 800p 10n)
.tran 1p 2n
.measure tplh trig V(in) val=1.25 fall=1 targ v(out) val=1.25 rise=1
.measure tphl trig V(in) val=1.25 rise=1 targ v(out) val=1.25 fall=1
.end
************************************************************************
Inverter Delay
120
Delay [ps]
100
80
y = 21.153x + 29.158
60
40
20
0
0
1
2
3
4
5
Fanout
b) In your plot, the points should fall in a straight line…find the best-fit line through
the data. This allows you to extrapolate the delay for a fanout of 0 (intercept with
the x-axis). This is your self-loaded delay. What is this value?
Self-loaded delay = 29.2ps
c) In your plot, the slope of the line tells you about the additional delay per fanout.
What is this value?
Slope = 21.2ps per fanout
d) From your answers to b) and c), find the Cg/Cd, the ratio between the gate
capacitance (load per additional fanout) and the drain capacitance (self-load).
Assuming that Cg=Cox(Wn+Wp)L, compute Cg and Cd.
Cd/Cg = Self-loaded delay / Delay for one fanout = 29.2 / 21.2 =
Cg = (3.9 * 8.85e-14 F/cm / 58Å) * (1m + 2m) * 0.25m =
1.38
4.46fF
Cd = 1.38 * Cg = 6.15fF
e) Using Cd (and Cg if you like), compute Req. Just use the average delay, ignoring
differences between high-low and low-high transitions.
Using the self-loaded delay:
Req = tp,self-load / (0.69 * Cd) = 29.2 ps / (0.69 * 6.15fF) = 6.87k
Problem 2 – Self-loaded NAND Delay
a) Use HSPICE to find the average propagation delay for a NAND gate in this
process for a fanout of 1, 2, 3, and 4. Plot the propagation delay as a function of
the fanout.
************************************************************************
* ee141 hw5: 4-stage nand chain
.param cload='20f'
.param fanout='4'
.lib '/home/ff/ee141/MODELS/g25.mod' TT
************************************************************************
* nand
.subckt nand in1 in2 out vdd gnd
m1 out in2 x gnd nmos w=2u l=.25u
m2 x in1 gnd gnd nmos w=2u l=.25u
m3 out in1 vdd vdd pmos w=2u l=.25u
m4 out in2 vdd vdd pmos w=2u l=.25u
.ends
************************************************************************
* nand plus capacitive load at output
.subckt nandcap in vdd gnd
x1 vdd in out vdd gnd nand
c1 out 0 'cload'
.ends
************************************************************************
* load nand plus fanout
.subckt nandload in vdd gnd
x1 vdd in out1 vdd gnd nand
x2 out1 vdd gnd nandcap m='fanout'
.ends
************************************************************************
* main deck
* 4-stage nand chain
x1 vdd stepin in vdd 0 nand
x2 vdd in out vdd 0 nand
x3 vdd out out2 vdd 0 nand
x4 out2 vdd 0
nandcap m='fanout'
* loading nand's
x2load in vdd 0 nandload m='fanout-1'
x3load out vdd 0 nandload m='fanout-1'
* voltage sources
vdd vdd 0 dc 2.5
vin stepin 0 pulse (0 2.5 100p 200p 200p 800p 10n)
.tran 1p 2n
.measure tplh trig V(in) val=1.25 fall=1 targ v(out) val=1.25 rise=1
.measure tphl trig V(in) val=1.25 rise=1 targ v(out) val=1.25 fall=1
.end
************************************************************************
NAND Delay
160
140
Delay [ps]
120
100
y = 25.765x + 44.034
80
60
40
20
0
0
1
2
3
4
5
Fanout
b) What is the self-loaded delay of a NAND gate?
Self-loaded delay = 44.0ps
c) What is the slope of the best-fit line through your data points (additional delay
per fanout)? This slope is related to the number obtained from logical effort
calculations when you divide by the slope for an inverter (problem 1)…compare
slopeNAND/slopeINV to the theoretical value from logical effort.
Slope = 25.8ps per fanout
Slope ratio = 25.8 / 21.2 =
1.22
This is close to the logical effort value of 1.33.
d) From your answers to b) and c), find the Cd/Cg. Compute Cg and Cd.
Cd/Cg = Self-loaded delay / Delay for one fanout = 44.0 / 25.8 =
Cg = (3.9 * 8.85e-14 F/cm / 58Å) * (2m + 2m) * 0.25m =
1.71
5.95fF
Cd = 1.71 * Cg = 10.17fF
This drain capacitance is bigger than for the inverter…which makes sense
because we’re hooking up more devices to the output…and the transistor W’s are
bigger as well.
e) Compute Req.
Using the self-loaded delay:
Req = tp,self-load / (0.69 * Cd) = 44.0 ps / (0.69 * 10.17fF) = 6.27k
The Req is similar to the value we found for the inverter…which makes sense
because we doubled the W’s for the stacked NMOS transistors.
Problem 3 – You Guessed It…Self-loaded NOR Delay
a) Use HSPICE to find the average propagation delay for a NOR gate in this process
for a fanout of 1, 2, 3, and 4. Plot the propagation delay as a function of the
fanout.
***********************************************************************
* ee141 hw5: 4-stage nor chain
.param cload='20f'
.param fanout='4'
.lib '/home/ff/ee141/MODELS/g25.mod' TT
************************************************************************
* nor
.subckt nor in1 in2 out vdd gnd
m1 out in2 gnd gnd nmos w=1u l=.25u
m2 out in1 gnd gnd nmos w=1u l=.25u
m3 out in2 x vdd pmos w=4u l=.25u
m4 x in1 vdd vdd pmos w=4u l=.25u
.ends
************************************************************************
* nor plus capacitive load at output
.subckt norcap in vdd gnd
x1 gnd in out vdd gnd nor
c1 out 0 'cload'
.ends
************************************************************************
* load nor plus fanout
.subckt norload in vdd gnd
x1 gnd in out1 vdd gnd nor
x2 out1 vdd gnd norcap m='fanout'
.ends
************************************************************************
* main deck
* 4-stage nor chain
x1 gnd stepin in vdd 0 nor
x2 gnd in out vdd 0 nor
x3 gnd out out2 vdd 0 nor
x4 out2 vdd 0
norcap m='fanout'
* loading nor's
x2load in vdd 0 norload m='fanout-1'
x3load out vdd 0 norload m='fanout-1'
* voltage sources
vdd vdd 0 dc 2.5
vin stepin 0 pulse (0 2.5 100p 200p 200p 800p 10n)
.tran 1p 2n
.measure tplh trig V(in) val=1.25 fall=1 targ v(out) val=1.25 rise=1
.measure tphl trig V(in) val=1.25 rise=1 targ v(out) val=1.25 fall=1
.end
************************************************************************
NOR Delay
200
180
160
Delay [ps]
140
120
y = 34.428x + 49.647
100
80
60
40
20
0
0
1
2
3
Fanout
f) What is the self-loaded delay of a NAND gate?
Self-loaded delay = 49.6ps
4
5
g) What is the slope of the best-fit line through your data points (additional delay
per fanout)? This slope is related to the number obtained from logical effort
calculations when you divide by the slope for an inverter (problem 1)…compare
slopeNAND/slopeINV to the theoretical value from logical effort.
Slope = 34.4ps per fanout
Slope ratio = 34.4 / 21.2 =
1.63
This is very close to the logical effort value of 1.67.
h) From your answers to b) and c), find the Cd/Cg. Compute Cg and Cd.
Cd/Cg = Self-loaded delay / Delay for one fanout = 49.6 / 34.4 =
Cg = (3.9 * 8.85e-14 F/cm / 58Å) * (1m + 4m) * 0.25m =
1.44
7.44fF
Cd = 1.44 * Cg = 10.73fF
This drain capacitance is bigger than for the NAND…which makes sense because
the total transistor W (NMOS plus PMOS) is larger.
i) Compute Req.
Using the self-loaded delay:
Req = tp,self-load / (0.69 * Cd) = 49.6 ps / (0.69 * 10.73fF) = 6.70k
The Req is similar to the value we found for the inverter…which makes sense
because we doubled the W’s for the stacked PMOS transistors.
Problem 4 – Investigating Wire Delay in a Pentium 4 Chip…
a) What is the propagation delay through just this metal wire (without considering
the buffer)?
R = 0.02 / * (1.2cm/0.6m) = 400
Cpp = 0.03 fF/m2 * (0.6m) * (1.2cm) = 216fF
Cfringe = 2 * 0.03 fF/m * 1.2cm = 480fF
Cwire = Cpp + Cfringe = 696fF
Assuming the lumped model,
tp = 0.69 * R * Cwire = 192 ps
or assuming the distributed RC model,
tp = 0.38 * R * Cwire = 106 ps
b) Under the microscope, it is very difficult to tell the size of the second inverter.
However, assuming that the designers at the blue-logo-ed company sized it to
minimize total delay (a good assumption, don’t you say?), what is the size of this
inverter? What, then, would be the minimum delay through the two-stage buffer?
The circuit given in this part of the problem looks like the following:
If we wanted to be nitpicky, we could add the load minimum-sized inverter to
Cwire, but that only adds 1.5fF, which is negligible compared with the 696fF wire
capacitance.
To find the minimum delay, we want
tp0/(u*Ci) + tp0/Cwire = minimum
=> u = sqrt (Cwire/Ci) = sqrt (696fF / 1.5fF) = 21.5
Thus, the second buffer should be 21.5X larger than the first buffer.
tp,buffer = 2 * u * tp0 = 2 * 21.5 * 7.0ps = 302ps