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Basic Knowledge of Data Converters
Agenda
•
•
Data Converter Overview
ADC/DAC Basics
–
–
–
Sampling Theory
ADC Architectures
• SAR
• Delta-Sigma
• Pipeline
• Flash
DAC Architectures
•
•
•
R-2R
String
Data Converter Specifications / Test (how to get them from DATASHEET)
– DC Spec.
– AC Spec.
–
ADC/DAC Nomenclature
What is ADC
Analog
to
Digital
AMPLITUDE
7FFFFF
TIME
0000000
800000
What is DAC
Digital
to
Analog
AMPLITUDE
7FFFFF
0000000
800000
TIME
ADC/DAC Basic
– Sampling Theory
– ADC Architectures
•
•
•
•
Delta-Sigma
SAR
Pipeline
Flash
– DAC Architectures
• R-2R
• String
Basic ADC Theory
• Analog signal is sampled
• The sampled analog signal is compared to
one or more reference voltages
• The result of the comparison is converted
by digital logic to a binary number.
SHANNON’S information theorem
NYQUIST’S Criteria
 Shannon:
 An analog signal with a Bandwidth of fa must be sampled at a rate
fs>2fa in order to avoid the loss of information.
 The Signal Bandwidth may extend from DC to fa (Baseband Sampling)
or from f1 to f2, where fa = f2-f1 (Undersampling, or Super-Nyquist).
 Nyquist:
 If fs<2fa, then a phenomenon called aliasing will
occur.
 Aliasing is used to advantage in undersampling
applications
Sampling Theory
Input Waveform
Sampled Output
Sampling Function
f(t)
h(t)
X
t1 t2 t3 t4
g(t)
Unit Pulses
f(t4)
=
t
f(t1)
t
T
f(t2) f(t3)
t1 t2 t3 t4
t
Fourier Transform
Input Spectrum
Sampling Spectrum
Sampled Spectrum
H(f) Nyquist region
F(f)
G(f)
=
*
f1
*
f
fs = 1/T
2fs
NYQUIST'S THEOREM: fs-f1 > f1
f
f1
fs fs+f1 2fs-f1 f
 fs > 2 ´ f1
14-8
Oversampling
Why Oversample?
•
•
TO MOVE ALIASING FREQUENCY FURTHER FROM THE
DESIRED SIGNAL.
TO RELIEVE ANTIALIASING AND RECONSTRUCTION FILTER
REQUIREMENTS
– COST
– COMPLEXITY
– RESPONSE
•
•
TO ALLOW FOR LOWER APPARANT INPUT NOISE BY
FILTERING IN THE DIGITAL DOMAIN.
TO ALLOW FOR LOWER APPARANT INPUT NOISE BY
SPREADING THE QUANTIZING NOISE OVER A WIDER
BANDWIDTH.
Sampling ADC
Quantization Noise
SIGNAL
OUTPUT
RMS QUANTIZATION
NOISE = q/
fs
2
12
fs
Effects of oversampling on
Quantization Noise
Analog signal fa sampled @ fs has images (aliases)
at |±Kfs ±fa|, K = 1, 2, 3, ...
fa
I
I
fs
0.5fs
1.5fs
ZONE 2
ZONE 1
ZONE 3
fa
I
0.5fs
2fs
ZONE 4
I
fs
I
I
I
I
1.5fs
2fs
Effect of oversampling on filter requirement
Analog filter requirement for fo = 10MHz: fS = 30MSPS AND fS
= 60MSPS
ANALOG LPF
fCLOCK = 30MSPS
dB
fo
IMAGE
IMAGE
10
20
30
40
IMAGE
50
IMAGE
60
70
80
FREQUENCY (MHz)
fCLOCK = 60MSPS
dB
fo
ANALOG
LPF
IMAGE
IMAGE
10
20
30
40
50
60
70
80
Undersamplinig
Why Undersample?
• The AC bandwidth of the “analog portion” of an ADC is usually wider
than the maximum sample rate.
• Nyquist says that the BANDWIDTH not the FREQUENCY of the
signal must be ½ sampling rate.
• You can process the spectrum at harmonics of the sample rate as well
Undersampling
A
ZONE 1
0.5fs
fs
1.5fs
2fs
2.5fs
3fs
3.5fs
fs
1.5fs
2fs
2.5fs
3fs
3.5fs
2fs
2.5fs
3fs
3.5fs
ZONE 2
B
I
0.5fs
ZONE 3
C
I
0.5fs
fs
1.5fs
Intermediate Frequency (IF) signal at 72.5MHz (±2MHz)
is aliased between DC and 5MHz
fs = 10.000 MHz
7fs= 70.000 MHz
dc
fs
2fs
3fs
4fs
5fs
6fs
7fs
0
10
20
30
40
50
60
70
BASEBAND
ALIAS:
dc TO 5 MHz
SIGNAL:
72.5 ± 2 MHz
f s = 10.000 MSPS
Anti-aliasing filter for undersampling
fs - f 1
f1
f2
2fs - f2
fc
DR
SIGNALS
OF
INTEREST
IMAGE
0
0.5fS
Bandpass filter specifications
IMAGE
IMAGE
fS
1.5fS
2fS
STOPBAND ATTENUATION = DR
TRANSITION BAND: f2 TO 2fs - f2
f1 TO fs - f1
CORNER FREQUENCIES: f1, f2
Quantization Error
• Analog signals are continuous
• Digital signals have discrete values
• A digital word that is converted to an analog signal
will always contain errors
• Quantization Error or Noise is dependent on the
number of bits used in the conversion
Quantization
Data Converters’ Architectures
• ADCs
–
–
–
–
Delta Sigma
SAR
Pipeline
Flash
• DAC
– R-2R
– String
Customers Talk Architecture???
Should you be scared - NO
Can you handle it - TRY
Just know the key characteristics and you
have just focused in on your device selection
A/D Converter
- SAR
- Pipeline
- Flash
- Delta Sigma
ADC Architectures:
Speed, Resolution, and Latency Analogy
Delta Sigma
–
–
–
–
16 to 24 bits of resolution
Typically Slow 10SPS to 105kSPS
Long Latency
If I was a camera I would have my aperture open longer
SAR
–
–
–
–
8 to 18 bits of resolution
~50kSPS to 4MSPS
No latency
If I was a camera I would be have fast shutter speed
Pipeline
–
–
–
–
8 to 14 bits of resolution
Up to over 300 MSPS
Some clock cycle latency
I want to be a video camera when I grow up
Flash
–
–
–
–
8 to 10 bits of resolution
Up to over 1 GSPS
no latency
I just want to be FLASH
TI Analog to Digital Families
300 M
Speed: Sample Rate in SPS
100 M
Pipeline
Advantages
•Higher Speeds
•Higher Bandwidth
Disadvantages
•Lower Resolution
•Pipeline Delay/Data Latency
•More power
10 M
1M
Delta
Sigma
SAR
Advantages
•High Resolution
•Low cost
•Low Power typically
•High Stability
(averages and filters out noise)
Disadvantages
•High Latency
•Low Speed typically
Advantages
•No Latency (happens immediately)
•High Resolution and Accuracy (<=18-bits)
•Typically Low Power
•Easy to Use and Multiplex
Disadvantages
•Typically sample Rates Limited to
Approximately 4 MHz
500 k
100 k
10 k
Delta Sigma
1k
0
6
8
10
12
14
16
Accuracy (Resolution in bit)
18
20
24
+
-
S/H
fS
Clock
An “n” bit SAR converter takes n
cycles to complete a conversion.
SAR and
Control Logic
MSB
LSB
D/A Converter
Ref
FS: Full Scale
Data Out
VIN
ADC – Successive Approximation
Register (SAR) Architecture
From most to least significant bit
(MSB to LSB) simple compare
functions are done and, when a bit
is a 1, that amount of voltage is
subtracted from the input signal.
SAR’s are workhorse converters…
easy to use… simple to
understand… but are limited in
both resolution and speed.
FS
FS
2
TI has MANY SAR ADCs.
0
MSB
LSB
Successive Approximation ADC
ADC – Pipeline Architecture
Pipeline converters are another high speed architecture. Several lower
resolution converters are put together to result in a fast conversion time.
Generally lower power and lower cost than Flash converters, the main
disadvantage of a Pipeline converter is that it takes as many clock cycles as
there are stages to output the data resulting in latency.
STAGE 1
STAGE N
Sample Hold
Amplifier
ANALOG
INPUT
Sample Hold
Amplifier
+ S
SAMPLE HOLD
AMPLIFIER
ADC
DAC
REGISTER
TI has many Pipeline
converters!
+
-
ADC
S
ADC
DAC
REGISTER
PARALLEL
DIGITAL
OUTPUT
Latency
SARs have none….OK, just a little
ADS7881
12 bits 4MSPS
Snapshot
Acquisition Time
Conversion Time = 150ηs
Aperture delay = 2ηs
If it was a 12 bit pipeline with 2 bits/stage, you would need:
150 ηs Conv t Delay = 6.6MSPS X 6 clock cycle delay = 40MSPS
Pipeline A/D Converter
Timing and Data Latency
Sample Points
S4
S5
S8
S1
S9
Analog Input
S2
S6
S3
S7
Track
Clock
Hold
Internal
S/H
Data Latency, 6.5 clock cycles
Track
Hold
Output Data
n
n-7
n+1
n-6
n+2
n-5
n+3
n-4
n+4
n-3
n+5
n-2
n+6
n-1
n+7
n
Pipeline A/D Converter
Signal Encoding: SAR vs. Pipeline
• SAR: Serial Encoding
Sample #1
MSB
B2
B3
B4
B5
B6
B7
LSB
B7
LSB
Conversion Time
• Pipeline: Parallel Encoding
Sample #1
MSB
B2
B3
B4
B5
B6
Conversion Time
Sample #2
MSB B2
B3
B4
B5
B6
B7
LSB
B3
B4
B5
B6
B7
Sample #3
MSB B2
LSB
And Now for something completely
different
Delta Sigma’s
Delta-Sigma Overview
• What is a delta-sigma ADC?
– A 1-bit converter that uses oversampling (can be multi-bit)
– “Delta” = comparison with 1-bit DAC
– “Sigma” = integration of the Delta measurement
• What is the advantage of delta-sigma?
– Essentially digital parts which result in low cost
– High resolution
• What are the disadvantages?
– Limited frequency response
– Most effective with continuous inputs
– Latency
3
S D Converters –
Functional Block Diagram
Analog
Input
PGA
Analog
Modulator
Advantages:
•
•
•
Minimum analog components
Integrates easily with digital logic
Oversampling reduces inband
noise
1-bit
wide
Digital
Filter
n-bits
wide Digital
Output
Disadvantages:
•
Speed limited to upper audio
range
Delta-Sigma A/D Converters
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Delta-Sigma A/D Signal Path
You are here
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Delta-Sigma A/D Signal Path
TIME DOMAIN
FREQUENCY DOMAIN
MAGNITUDE
AMPLITUDE
TIME
FREQUENCY
Delta-Sigma A/D Signal Path
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Delta-Sigma A/D Signal Path
TIME DOMAIN
Believe it or not, the sine
wave is in there!
FREQUENCY DOMAIN
SIGNAL
1
0
Fs
(drawing is approximate)
QUANTIZATION
NOISE
Delta-Sigma A/D Signal Path
TIME DOMAIN
FREQUENCY DOMAIN
SIGNAL
7FFFFF (+FS)
800000 (-FS)
Fs
QUANTIZATION
NOISE
Delta-Sigma A/D Signal Path
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Delta-Sigma A/D Signal Path
TIME DOMAIN
7FFFFF
FREQUENCY DOMAIN
SIGNAL
0000000
800000
QUANTIZATION
NOISE
Fs
Delta-Sigma A/D Signal Path
Analog
Input
Delta-Sigma
Modulator
Digital
Filter
Decimator
Digital Decimating Filter
(usually implemented as a single unit)
Digital
Output
Delta-Sigma A/D Signal Path
TIME DOMAIN
FREQUENCY DOMAIN
QUANTIZATION
ALIAS NOISE
7FFFFF
SIGNAL
0000000
800000
Fd
ORIGINAL Fs
Delta-Sigma A/D Signal Path
OUTPUT OF
DECIMATING FILTER
SIGNAL FROM
MODULATOR
7FFFFF
0000000
7FFFFF (+FS)
800000 (-FS)
800000
DECIMATING
FILTER
Oversampling, digital filter,
NOISE SHAPING, AND DECIMATION
A
fs
QUANTIZATION
NOISE = q / 12
q = 1 LSB
Nyquist
Operation
ADC
Oversampling
+ Digital Filter
Kfs
fs
B
+ Decimation
DIGITAL
ADC
DEC
FILTER
fs
Oversampling
+ Noise Shaping
+ Digital Filter
Kfs + Decimation fs
fs
Kfs
2
2
C
SD
MOD
fs
2
DIGITAL FILTER
REMOVED NOISE
Kfs
REMOVED NOISE
DIGITAL
DEC
FILTER
fs
Kfs
2
2
Kfs
The Delta-Sigma Modulator
Sigma
Delta
Signal input, X1
+
X3
X2
+
X4
To Digital
Filter
-
Difference
Amp
X5
Integrator
VMax
-
Comparator
(1-bit ADC)
1-bit DAC
4
Signal input,
X
1
+
X
3
X
2
-
+
X
4
Difference
Amp
X
5
1-bit DAC
X1
X2
Vmax
0V
+Vmax
-Vmax
X3
+Vmax
X4
1
X5
-Vmax
0
Vmax
0V
Integrator
VMax
Comparator
(1-bit ADC)
Latch
Delta-Sigma Modulator
To Digital
Filter
Averaging Filters
Full-scale
Delta-Sigma
Modulator
DC
input
levels
1-bit data
0V
1-bit data streams
1/2 full-scale input
1
0
1
0
1
0
1
0
Average
= 0.5
1/4 full-scale input
3/4 full-scale input
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
Average
= 0.25
Average
= 0.75
The Frequency Domain
Power
Signal amplitude
SNR = 6.02N + 1.76dB ; (for an N-bit ADC
Sine wave input)
Quantization Noise
Average noise floor (flat)
FS / 2
Frequency
FS
Power
Oversampling by K Times
Oversampling by K times
SNR = 6.02N + 1.76dB ; (for an N-bit ADC
Sine wave input)
Same total noise, but spread over more frequencies
Average noise floor
k FS / 2
Frequency
k FS
The Digital Filter
Ideal digital filter response
Power
Oversampling by K times
SNR = 6.02N + 1.76dB + 10 log(Fs/2*BW)
Noise removed by filter
BW
k FS / 2
Frequency
k FS
Noise-Shaped Spectrum
Signal Amplitude
Power
SNR = 6.02N + 1.76dB
The integrator serves as a
highpass filter to the noise.
The result is noise shaping
k FS / 2
Frequency
k FS
1st order DS Modulator
CLK
Vin(t)
Integrator
D/A
Dout(t)
Filtering the Shaped Noise
Signal amplitude
Power
Digital filter response
HF noise removed
by the digital filter
k FS / 2
Frequency
k FS
The 2nd Order Delta-Sigma
Modulator
INTEGRATOR
+
∑
-

INTEGRATOR 1-BIT ADC
+
∑
-

1-BIT OUTPUT
1-bit
DAC
MODULATOR OUTPUT
SPECTRAL QUANTIZATION
NOISE DENSITY
y x
i
i1
i
 e  2 e
i1
e

i2
 2  f T 
N2( f)  4 erms  2 T sin 

2


2
The Delta-Sigma Modulator
Modulator noise densities
0
100
200
300
Hz
1st-order
2nd-order
3rd-order
4th-order
400
500
The Delta-Sigma Modulator
Modulator noise densities
0
1
1st-order
2nd-order
3rd-order
4th-order
2
3
4
Hz
5
6
7
Sampling speed vs. ENOB
SIGNAL
Fd
Fs
QUANTIZATION
NOISE
ADC Topology Summary
ADC
Topology
SAR
F Conversion
< 5Msps
Resolution
Comments
Up to 18-bit
Simple operation, low
cost, low power.
Delta-Sigma < 100ksps
< 10MSPS
Up to 24-bit
Up to 16-18
bits
Slow, moderate cost.
Flash
< 500Msps
Up to 10-bit
Fast, expensive, large
power requirements.
Pipeline
< 200Msps
Up to 16-bit
Fast, expensive, large
power requirements.
6
D/A Converter
– R-2R
– String
– Current Steering
TI DAC Technologies
Instrumentation and Measurement
Typically for Calibration
Converter Resolution
20
DS
Industrial
Settling Time (µs)
Number of Out put DACs
Resistor String – Inexpensive
R-2R – More accurate -Trimmed at final test
Typically Voltage out
MDAC’s (dig control gain/atten, Waveform gen.)
High Speed Video and Communication
Update rate (MSPS)
Typically 1 Output but a few 2 Output
Current out
16
12
Resistor String
& R-2R
Current
Steering
8
1000
100
10
8
6
4
Settling Time- s
2
1
1/UpdateRate
Setling time
.05
.001
R-2R Architecture
R
R
R
R
R
R
R
R
+
2R
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
VR E F
+ small. Only 2*N resistors required
- tight resistor matching required
- not inherently monotonic
ANALOG
OUTPUT
( VOUT )
Resistor String DAC Architecture
VREF
R
7/8 V RE F
1
R
6/8 V RE F
0
1
R
0
5/8 V RE F
1
R
4/8 V RE F
0
1
+
R
0
3/8 V RE F
1
-
R
2/8 V RE F
0
1
VFB
R
0
1/8 V RE F
1
R
0V
VOUT
0
LSB
1
0
MSB
1
= VREF S(bi/2i)
Typical Block Diagrams of a Resistor
String DAC
VREF
VFB
REF(+)
DAC REGISTER
RESISTOR STRING
+
VOUT
REF(-)
GND
(a)
VREF
x2
DAC Latch
Data
Clock / W E
Control and
Interface
Buffer
C S
(b)
VOUT
Current Steering DACs
2N-1 Current Sources
I
I
I
IOUT
IOUT
Switches determined by digital input
Precision DAC Product Strategy
Low Cost
• Limited Accuracy
•
Low Cost
• High Accuracy
• Great AC Specifications
• Small Packages
• High Channel Counts
• Single and Dual Supply
Output Ranges
•
Expensive
• High Accuracy
•
More
BACK
DAC Architecture Positioning
15
Current Steering typically settles to 0.1%
Precision DACs (R-2R and String) to .003%
Settling Time (µs)
HPA07
10
5
Higher Power Consumption
0
0
1
* INL is at the 16-bit level
10
16
INL (LSB)
32
64
More
BACK
Data Converter Specifications
Evaluating the ADC (Datasheet)
Key Performance Characteristics
• DC
–
–
–
–
Offset error
Gain error
Differential linearity
Integral linearity
• AC
– SNR
– THD
– SFDR
• Others
How Large is an LSB ?
1 LSB =
N=
VFULLSCALE(nom.)
2N
N = Resolution of ADC
8
10
12
14
16
20
1 LSB
± 5 V input range
39.06
9.77
mV
2.44
mV
610
mV
153
V
9.53
V
1 LSB
+ 5 V input range
19.53
mV
4.88
mV
1.22
mV
305
V
76.3
V
4.77
V
1 LSB
+ 3 V input range
11.72
mV
2.93
mV
732
V
183
V
45.8
V
2.86
V
V
Resolution vs. Accuracy:
Poor Accuracy
Poor Resolution
Good Accuracy
Poor Resolution
Poor Accuracy
Good Resolution
Good Accuracy
Good Resolution
4
AC Specs
•
•
•
•
SNR (Signal-to-Noise Ratio) –
RMS value representing the ratio of the amplitude of the
desired signal to noise power below one half the sampling
frequency.
Measure of the strength of a signal to background noise.
Contributes to the overall dynamic performance of the
device at higher frequencies and affects the linearity at
those frequencies.
In the audio world, a low signal-to-noise ratio means the
device has lots of hiss and static, while a high rating means
clear-sounding audio.
THD (Total Harmonic Distortion) –
• The ratio of the sum of the powers of all harmonic
frequencies above the fundamental frequency to the power
of the fundamental frequency.
• THD is usually expressed in dB.
ENOB (Effective Number Of Bits) • The number of bits achieved in a real system.
• Is another way of specifying the SNR.
• ENOB = (SNR-1.76) / 6.02 and says that the converter is
equivalent to a perfect ADC of this ENOB number of bits.
SFDR (Spurious Free Dynamic Range) • The headroom available in an FFT plot.
• It is the distance in dB between the fundamental input and
the worse spur.
Fundamental
Signal
SFDR
First
Harmonic
Second
Harmonic
Average Noise
Floor
DC errors
111
Actual Transfer
Function
110
Ideal Transfer
Function
Digital Output code
101
100
011
010
001
000
Offset Error –
Actual Full Scale Range
Analog Input Voltage
Ideal Full Scale Range
Offset Error
• The offset error is the difference between the nominal and actual offset points.
• It is the difference in voltage between the first ideal code transition and the actual code transition of the ADC.
• This error affects all codes by the same amount and can usually be compensated for by a trimming process. If trimming is not possible, this error is
referred to as the zero-scale error.
Gain Error –
• The gain error is the difference between the ideal gain between zero and full scale on the transfer function and the actual gain after the offset error
has been corrected to zero.
• This error represents a difference in the slope of the actual and ideal transfer functions and as such corresponds to the same percentage
error in each step.
• This error can also usually be adjusted to zero by trimming.
DC Specs
111
Actual Transfer
Function
Ideal Transfer
Function
110
< 1LSB DNL
Digital Output code
101
100
011
010
> 1LSB DNL
001
000
Analog Input Voltage
INL < 0
INL (Integral Nonlinearity Error) - (or simply linearity error)
•
The deviation of the values on the actual transfer function from the ideal transfer function once the gain and offset errors have been
nullified.
• The summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the INL at that step.
• The unit for INL is LSB.
DNL (Differential Nonlinearity Error) – (or simply differential linearity)
• The differential nonlinearity error is the difference between an actual step width (for an ADC) or step height (for a DAC) and the ideal
value of 1 LSB (Least Significant Bit).
• If the DNL exceeds 1 LSB, the magnitude of the output gets smaller for an increase in the magnitude of the input.
• In an ADC there is also a possibility that there can be missing codes (if DNL < -1LSB) i.e. one or more of the possible 2n binary codes are never
output.
Major DNL Errors
ADC Missing Code
111
110
101
100
011
010
001
000
0
1
2
3
4 5
6
Input Voltage
7
LOST???
Different Datasheets list specs in different terminologies
– INL in LSB, mV, %, PPM
– Power in mW, V, I
– Gain error/drift in %FSR, μV
The Relevancy…
Power (W) = Vin (V) X Ioper (A)
Cheat
Book
LSB
LSB
*
mV
%
PPM
LSBX(2)[1].VrefX100
2N
LSB X 100
2N
LSB X 106
2N
mV
mV X 2N .
(2)[1].Vref 100
*
mV .
(2)[1] Vref
mV X 104
(2)[1] .Vref
%
% X 2N
100
% X (2)[1] .Vref
*
% X 104
PPM
PPM X 2N
104
PPM X (2)[1] .Vref
100
PPM
104
*
[1] The factor 2 in brackets is to be used for a bipolar device.
ADC Offset Errors
Ideal transfer characteristic
Output Code
111
110
101
100
011
Actual transfer characteristic
010
001
000
0
1
2
3
4 5
6
7
Input Voltage
10
ADC Gain Errors
Output Code
111
110
101
100
011
010
001
000
0
1
2
3
4 5
6
7
Input Voltage
11
ADC INL Errors
111
Output Code
110
101
100
011
010
001
000
0
1
2
3
4 5
6
7
Input Voltage
13
ADC DNL Errors
Output Code
111
110
101
100
011
010
001
000
0
1
2
3
4 5
6
7
Input Voltage
12
DNL Major Errors
ADC Missing Code
DAC Non-monotonic
7
Output Voltage
Output Code
111
110
101
100
011
010
001
000
0
1
2
3
4 5
6
Input Voltage
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Input Code
12
Amplitude (dB)
Dynamic Specifications
Fundamental
F
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
Harmonics
0
1k
H2
H3
H4
H5
H6
H7
H8
2k
3k
4k
5k
6k
7k
8k
H9
9k 10k
Frequency - Hz
14-30
Amplitude (dB)
Spurious Free Dynamic Range (SFDR)
Fundamental F
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
SFDR
0
1k
2k
3k
4k
5k
6k
7k
8k
9k
10k
Frequency / Hz
14-32
Amplitude (dB)
Intermodulation Distortion, IMD
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
f1
f2 - f1
0
1k
f2
2f1 - f2
2k
3k
2f2 - f1
4k
5k
6k
f1 + f2
7k
8k
9k
10k
Frequency / Hz
14-33
Measuring Noise
• RMS noise
– Usually calculated from standard
deviation of a series of samples
– Used to calculate ENOB
– Does not depend on noise type
• Peak-to-peak noise
– Gives “display resolution”
– Estimates typically assume that the
noise is Gaussian
Measuring Noise
Calculating RMS noise
N
Variance of a set
of N samples:
Standard deviation:
Effective number of
bits (if samples are
ADC codes):
 
2
 (x  x )
2
i
i 0
N
 
ENOB  M  log 2 
2
Measuring Noise
Peak-to-peak noise
For Gaussian noise, > 99.9% of
samples occur in the interval:
(
X

3
.
3

,X

3
.
3

)
X
X
Then our rule of thumb is:
Peak-to-peak noise = 6.6 * RMS noise
Digital Output Code
Signal to Noise Ratio (SNR)
111
110
101
100
011
010
001
000
SNR =
Q
VSIN
VN
SNR(dB) = 6.02 ´ N + 1.76
N is number of bits of resolution
0.5 FS
Each extra bit provides approximately
6 dB improvement in the SNR !
FS
Analog Input Voltage
Effective Number Of Bits (ENOB):
+Q/2
Q
-Q/2
ENOB =
(SNR + D)(dB) - 1.76
6.02
Quantization Noise
14-29
Definition of "NOISE-FREE" code
resolution
Effective
resolution
=
log2
Noise-free
Code resolution
=
log2
Full scale range
RMS noise
Full scale range
P-P noise
P-Pnoise = 6.6 × RMS noise
(most commonly used ratio)
= effective resolution – 2.72 bits
bits
Typical output RMS NOISE in uV
and effective resolution in bits
First Notch of Filter
and O/P Data Rate
-3 dB
Frequency
G=1
G=4
G = 16
G = 128
10 Hz
2.62 Hz
1.7
0.5
0.36
0.36
60 Hz
15.72 Hz
8.5
2.0
0.6
0.45
250 Hz
65.5 Hz
130
25
7.5
1.7
1 kHz
262 Hz
180
40
Output Noise:
3.1 x 103 0.7 x 103
Effective Resolution:

10 Hz
2.62 Hz
21.5
21.5
19.5
16.5
60 Hz
15.72 Hz
19.5
19
19
16.5
250 Hz
65.5 Hz
15.5
15
15
14.5
1 kHz
262 Hz
10.5
11
11
10
Device (Semiconductor, Resistor) Noise Dominates at the Lower
Frequencies (< 60 Hz notch)

Quantization Noise Dominates at the Higher Frequencies
Aperture-Jitter (Sampling Uncertainty)
A
VP
V+ Dv
V
Dv
DtA
t
The Aperture Error is
less than 1 LSB, if:
TA
-VP
Dt A 
1
2n    fmax
In a 12-bit system with a maximum signal frequency of 20 MHz, the ApertureJitter has to be less than 3.8 ps !
Jitter Limits
130
120
0.1 ps
110
0.3 ps
100
*16 Bit
1 ps
SNR(dB)
90
*14 Bit
3 ps
80
*12 Bit
70
10 ps
60
50
40
30
1
10
100
Maximum Signal Frequency (MHz)
* Equivalent converter SNR
1000
Number of Input Channels
– What is meant by 4 SE or 4 Diff?
Multiplexer
ADC
– What is meant by 3x2 Diff?
Multiplexer
ADC
Multiplexer
ADC
Number of Input Channels
Single Ended (SE) vs Differential (Diff)
• SE:
– Referenced to ground
– Grounds may not be the same across causing a noisier environment
Ain
• Diff:
– Full-scale Range
– Wider code steps
– More accurate
Ain+
Ain-
ADC Interface Solutions
Principle Configuration Choices
Single-Ended Input
+ fs
+ fs/2
Vcm
-fs/2
Input
Vcm
IN
ADC
- fs
Differential Input
IN
+ fs/2
Vcm
-fs/2
IN
ADC
IN
Vcm
Requires full input swing from +fs to –fs
2x the swing compared to differential
Input signal at IN typically requires a
common-mode voltage for bias
Input IN\ also requires a Vcm for correct
dc-bias
Combined Differential inputs result in
full-scale input of +fs to –fs
Each input only requires 0.5x the
swing compared to single-ended
Both inputs require a Vcm for correct
dc-bias
Typical SPI Interface
SPI
ADS8344
CH0
CS
SS
DCLK
SCLK
DOUT
MISO
DIN
MOSI
BUSY
GPI
CH7
43
I2C Interface — DSPs
VDD
ADS7828
2k
CH0
CH1
2k
C55XX
I2C
SDA
CH7
SCL
ADS7828
CH0
CH1
C55XX
I2C
SDA
SCL
CH7
48
Parallel—Digital Signal Processor
Digital Signal
Processor
ADS8322
CS
GPO
CLK
CLK
R/W
RD
decoder
CONVST
A[19:0]
Digital Signal
Processor
ADS8322
CS
GPO
CLK
CLK
R/W
RD
logic
A[19:0]
CONVST
GPO
GPO
BUSY
GPI
D[15..0]
D[15..0]
Figure 1
D[15..0]
BUSY
D[15..0]
logic
INT
Figure 2
46
Pseudo-Differential Mode ADC’s
AIN(+)
ADC
AIN(-)
+/- 200mV Maximum
DAC
Pseudo-Differential Mode ADC’s
DAC OUTPUT
AIN(+)
AIN(-)
Analog Output (V)
Settling time of a DAC
Settling Time, ts
Error
Band
Final Value
Glitch
Digital Change
Delay Time
t
Monotonicity
A DAC is monotonic if its output either increases or
remains constant as the digital input increases,
with the result that the output will always be a
single-valued function of the input.
Glitch Improvement
• Main Cause of Glitch
– Charge in the switch causes
node voltage to change
temporarily
– More number of switches
toggling when code changes –
more glitch!!
V IN
+
a
• TSMC products uses RowColumn decoding (see next
slide) – 30~40 switches
toggling at any code change
• HPA07 products uses single
decoder – maximum of two
switches toggling at any time
Charge Q
gets split
V
R FB
fb
Rt
VOUT
ADC Nomenclature
•
•
TI ADCs
- TLC/TLVxxxx
0 or Blank 8-Bit
1 10-Bit
2 12-Bit
3 14-Bit
4 16-Bit
7 4½ Digit
TLC: 5V
TLV: 3V
•
HS ADCs Not Included
ADS51xx
ADS52xx
ADS54xx
ADS55xx
ADS8xx
THS14xx
THS12xx
THS10xx
BB ADCs & Future
- ADS1xxx Delta-Sigma ADCs (except ADS1286 SAR)
ADS1xxx: 12-Bit
ADS11xx: 16-Bit
ADS121x: 24-Bit, Integrated
ADS122x: 24-Bit, Low Power
ADS123x: 24-Bit Weight
ADS125x: 24-Bit Programmable
ADS127x: 24-Bit Fast AC/DC
ADS16xx: 16-/18-Bit Wide Bandwidth
- ADS78xx/ADS8xxx SAR/Nyquist ADCs
ADS78xx: 8-/10-/12-/14-/16-Bit <1MSPS
ADS83xx: 16-/18-Bit <1MSPS
ADS84xx: 16-/18-Bit >1MSPS
ADS85xx: 12-/16-Bit +/-10V
- THS10xxx/12xx, TLV12xx/15xx High-speed (<10 MSPS)
All Future DAP ADCs Will Have ADS Prefix!
DAC Nomenclature
•
TI 8-/10-/12-Bit DACs
•
- TLC/TLV56xx
TLC: 5 V
TLV: 3 V
•
High Speed CMOS DACs
(Update Rate > 40MSPS)
DAC56xx
DAC9xx
DAC29xx
THS56xx
•
Delta Sigma DACs
DAC1xxx: 14/16-Bit
Burr-Brown and Newer TI DACs
- DACx5xx String DACs (0 to +5 V)
DAC55xx: 8-Bit, I2C, Unipolar
DAC65xx: 10-Bit, I2C, Unipolar
DAC751x: 12-Bit, SPI, Unipolar
DAC754x: 12-Bit, Parallel, Bipolar
DAC755x: Enhanced 12-Bit, SPI, Unipolar
DAC757x: 12-bit, I2C, Unipolar
DAC85xx 16-bit, Serial or Parallel, Unipolar or Bipolar
- DAC76xx R-2R DACs (0 to +2.5 V & +/-2.5 V)
DAC76xx: 12-/16-Bit, SPI or Parallel, Bipolar
- DAC77xx R-2R High-voltage DACs (0 to +10 V & +/-10 V)
DAC77xx: 12-/16-Bit, SPI or Parallel, Bipolar
- DACx8xx R-2R Multiplying DACs. 2nd Source to ADI/LTC
DAC78xx: 12-bit, SPI or Parallel
DAC880x: 14-Bit, SPI or Parallel
DAC881x: 16-Bit, SPI
DAC882x: 16-Bit, Parallel
- DAC883x: R2R DAC 16-Bit, SPI, Low Power, Best INL/DNL
Thanks!
Questions?