Download 2008 IC/CAD Contest - Problem A2

2008 IC/CAD Contest - Problem A2
Sequential Equivalence Checking for Synthesis-Retimed Circuit
Source: Cadence Design Systems, Inc.
1. Introduction
Equivalence checking (EC) is the process in electronic design automation (EDA) that
proves the functional equivalence of the golden (reference) design and the revised
design. Usually the revised design is obtained by synthesizing and optimizing the
golden design. Retiming is the circuit optimization technique that moves
combinational logic from one side of a register to another in order to improve the
performance, area and/or power characteristics of the design while preserving its
functional behavior [1]. Retiming complicates EC because retiming changes the
number and location of the registers, thus makes it hard for the mapping algorithms in
combinational EC tools, which need to identify matching registers between two
designs under verification. It is even more of a challenge for the EC tools when
retiming is accompanied by other logic optimization techniques.
2. Problem description and input/output format
Equivalence checking of retimed designs can be done by retiming the sequential
elements in golden or revised circuits such that the state points can be paired between
the two designs. The basic forward and backward retiming steps are shown in Figure
1.
D Q
forward
D Q
D Q
backward
Figure 1: The basic forward and backward retiming steps
Without any retiming modification to the golden or revised designs, combinational
equivalence checker will produce non-equivalent result for retimed designs. However,
this is a false negative result, which is caused by combinational equivalence checker's
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inability to map the sequential elements (key points) between golden and revised
designs. Your task is to apply retiming transformation to the input netlist such that
combinational equivalence checker can produce the correct equivalent result.

Input/output format
Both input and output are verilog netlists.
Input format: two verilog netlist files are given. One filename is called g.v, the
golden design; and the other filename is called r.v, the revised design.
You need to either retime golden or revised such that the resulting verilog description
will make golden and revised equivalent.
The input format is the verilog description. To simplify the problem, we assume the
primitive gates (and / or / not / xor) will be used for combinational logic, and the
sequential part is described in always @ (posedge clk) statement.
Output format: output is also a verilog netlist file. If you retime the golden design,
the output filename needs to be called retimed_g.v. If you retime the revised design,
the output filename should be retimed_r.v.
3. Example
The following is an example showing you the input data and expected result.
The verilog description of the golden design (g.v) is shown below and its
correspondent schematic is demonstrated in Figure 2.
=============================================================
module simple(clk,a,b,c,d,e,p1,p2,p3);
input clk,a,b,c,d,e;
output p1,p2,p3;
reg da,db,dc,dd;
and and1(p1,a,b);
and and2(a2,da,db);
and and3(a3,dc,dd);
and and4(p3,c,d);
and and5(a5,a2,a3);
and and6(p2,a5,e);
always @ (posedge clk)
begin
da<=a;
db<=b;
2
dc<=c;
dd<=d;
end
endmodule
Figure 2: The schematic of golden design (g.v)
=============================================================
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The verilog description of the revised design (r.v) is shown below and its schematic is
demonstrated in Figure 3.
=============================================================
module simple(clk,a,b,c,d,e,p1,p2,p3);
input clk,a,b,c,d,e;
output p1,p2,p3;
reg da1;
reg da2;
and and1(p1, a, b);
and and2(p3, c, d);
and and3(p2, da1, da2, e);
always @ (posedge clk)
begin
da1<=p1;
da2<=p3;
end
endmodule
Figure 3: The schematic of revised design (r.v)
=============================================================
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The objective of this problem is to either retime golden or revised design such that the
resulting verilog description will make golden and revised design equivalent.
Following is the sample output file retimed_r.v (modified from the revised design).
After retiming the revised design, the flops of golden design g.v and retimed design
can do one-to-one matching. Thus, the combinational equivalence checker can verify
them exactly without false negative. The relationship between golden design, revised
design and retimed design are shown in Figure 4.
g.v
?
r.v
EQ
retimed_g.v
1. # of flops in g.v and r.v are different.
2. # of flops in retimed_g.v and r.v are the same.
3. Assume we translate g.v into retimed_g.v. They
are functional equivalence.
4. If retimed_g.v ≡ r.v, then g.v ≡ r.v
If retimed_g.v ≡ r.v, then g.v ≡ r.v
Figure 4: The relationship of g.v, r.v and retimed design (retimed_g.v)
The verilog description of the retimed design (retimed_r.v) is shown below and its
schematic is illustrated in Figure 5.
=============================================================
module simple(clk,a,b,c,d,e,p1,p2,p3);
input clk,a,b,c,d,e;
output p1,p2,p3;
reg da,db,dc,dd;
and and1(p1, a, b);
and and11(pp1, da, db);
and and2(p3, c, d);
and and22(pp3, dc, dd);
and and3(p2, pp1, pp3, e);
always @ (posedge clk)
begin
da<=a;
db<=b;
dc<=c;
dd<=d;
end
endmodule
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Figure 5: The schematic of retimed design (retimed_r.v)
4. Language/Platform

Language: C or C++

Platform: SUN OS/Solaris or Linux OS
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5. Evaluation
Program will be evaluated by the following criteria,

Correctness: Input & output will be verified with combinational equivalence
checker. (e.g. Cadence Conformal LEC)

Number of equivalent flops: i.e. the program should maximize the number of
equivalent flops.

CPU time and Memory Usage
6. Reference
[1] C. Leiserson and J. Saxe, “Optimizing synchronous systems,” Journal of VLSI
and Computer Systems, vol. 1, pp. 41–67, January 1983.
[2] A. Kuehlmann and C. van Eijk, Combinational and Sequential Equivalence
Checking, in Logic Synthesis and Verification. Kluwer Academic Publishers,
2004.
[3] C. Leiserson and J. Saxe, “Retiming synchronous circuitry,” Algorithmica, vol.
6, pp. 5–35, 1991.
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