Download ECE442: Digital Electronics

ECE442: Digital Electronics
Homework #1
Due Wednesday, Feb 3
Read Chapters 1 and 3
Review summary charts
Review EE320 notes
Problems:
1.
It is desired to realize the function of a 3-input odd parity checker. Specifically,
the output Y is to be high when an odd number of the inputs are high. Show your
truth table and simplify using K-map and implement using NOR gates ONLY and
using NAND gate ONLY.
2. Design a Full binary adder using NOR gates ONLY.
3. Design a BCD (Binary Coded Decimal, 0 ~ 9) to 7-Segment decoder. A digital display
that consists of 7 LED (Light emitting diodes) segments is commonly used to display
decimal numerals in digital systems (or in calculators or digital watches. It is shown
below. Designate the inputs by A, B, C and D. Construct the truth table, the K-Map,
simplify and implement using NANG gates only.
a
f
b
g
c
e
d
4. How would you design a 32:1 multiplexer if you have two 16:1 Multiplexers and one
2:1 multiplexer only?
5. Five identical inverters are connected in cascade (Series). Each inverter introduces
a propagation delay of 2 nsec.
a) What is the total propagation delay from the input of the first inverter to the
output of the last inverter?
b) Now assume that the output of the last inverter is connected to the input of the
first inverter forming a "Ring" oscillator. Sketch the output of the oscillator and
find the frequency and the period of oscillation.
6.
A switch is used to control a capacitor's connection to either V
DD
or Gnd through a
resistor as shown below.
a) If the switch has been connected to R for a long period of time and is then flipped
2
to R at t = 0, calculate the time it takes the capacitor to reach 0.6 volts (V /2)
1
DD
b) If the switch has been connected to R for a long period of time and is then flipped
1
to R at t = 0, calculate the time it takes the capacitor to reach 0.6 volts (V /2)
2
DD
VDD = 1.2
R1 = 30K
R2 = 12.5K
1F
7. The VTC of a digital logic inverter is modeled by a three line segments. The input
voltage low and high are 1.5 and 2.5 volts respectively. The output voltage low and
high is 0.5 and 4 volts respectively. Sketch the VTC and find the noise margins and
the inverter-switching threshold V . Also find the gain in the transition region.
M
8. A step input from 0 to 1.2 volts is applied to the RC circuit shown below.
Calculate the time required for the voltage across the capacitor to reach 0.6
volts? Reach 1.2 volts? Go from 10% to 90% of the 1.2 volts?
R = 12.5 K
+
vi(t)
_
+
vo(t)
C = 100 fF
_
9. A switch is used to control a capacitor's connection to either VDD or Gnd
through resistors R1 and R2 respectively as shown below.
a) If the switch has been connected to R2 for a "long period of time" so that the
capacitor voltage is 0 volts, and the switch is then connected to R1 at t=0,
calculate the time it takes for the capacitor's voltage to reach 0.6 volts (i.e. V DD
/2)
b) If the switch has been connected to R1 for a "long period of time" so that the
capacitor voltage is 1.2 volts, and the switch is then connected to R2 at t=0,
calculate the time it takes for the capacitor's voltage to reach 0.6 volts
VDD = 1.2 volts
R1 = 30 K
R2 = 12.5 K
CL= 1F