Download Backpropagation for Population-Temporal Coded Spiking Neural

Ghent University
Compact hardware for real-time speech
recognition using a Liquid State Machine
Benjamin Schrauwen – Michiel D’Haene
David Verstraeten – Jan Van Campenhout
Electronics and Information Systems Department
Ghent University – Belgium
IJCNN 2007
Intro
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Goal:
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Create isolated digits speech recognition in digital FPGA hardware
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Real-time processing
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As small as possible
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First introduce LSM based speech recognition
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Investigate two existing hardware architectures (to fast, to large)
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Introduce new hardware architecture
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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LSM based speech recognition
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Ear model
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Liquid State Machine
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Recurrent structures without the training: Reservoir Computing
•Jaeger
(2001): Echo State Networks (engineering)
•Maass
(2002): Liquid State Machines (neuroscience)
•Steil
(2003): weight dynamics of Atiya-Parlos equivalent
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Fixed, random topology operated in correct dynamic regime
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Different node types possible: THG, linear, tanh, spiking, …
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Linear “readout” function which is trained (No local minima, no problems
with recurrent structure, one shot learning)
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On-line computing: prediction at every time-step
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Any time-invariant filter with fading memory can be learned (with output
feedback, universal computing)
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Reservoir computing
Compact hardware for real-time speech recognition using a LSM
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error
error
Influence of parameters
dynamic regime
reservoir size
error
Not very important:
•Connection fraction
•Exact topology
•Weight distribution
timescale
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Spiking Neural Networks
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Incoming spikes influence the membrane potential
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When certain threshold θ is reached: reset and fire
membr
θ
t
input
output
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Readout and post-processing
Compact hardware for real-time speech recognition using a LSM
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Digital spiking neurons
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SNN: mathematically a more complex model than ANN
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But: better implementable in hardware
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No weight multiplications: table look-up
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Filtering can be implemented using shifts and adds
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Interconnection only single bit, and sparse communication
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Asynchronous communication easily implementable
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Digital spiking neurons
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Hardware can take advantage of parallelism
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But area-speed trade-off: we don’t have to make the implementation faster than
needed by the application
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For trade-off: different implementations with other area-speed needed
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Possible parallelisms:
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Network parallelism
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Neuron/synapse parallelism
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Arithmetic parallelism
We implemented:
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SPPA: network parallel, neuron serial, arithmetic parallel
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PPSA: network parallel, neuron parallel, arithmetic serial
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SPSA: network serial or parallel, neuron serial, arithmetic serial
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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SPPA
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Much like classical CPU
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[Roggen 2003][Upegui 2005]
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Serial adder
PPSA
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Use FPGA features
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[Girau2006]
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[Schrauwen2006]
SRL16
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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SPSA
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Everything serial
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PEs are very small (4 LUTs)
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Many parallel PEs possible
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SIMD controller architecture
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Memory based interconnect
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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Area-speed trade-off for speech task
•Speech
task in hardware
•LSM with 200 neurons
•16 kHz processing speed
•Real-time requirement
LUTs
memory
Real-time
SPPA
13812
900 kbit
347
PPSA
13426
58 kbit
205
SPSA 10PE
488
144 kbit
2.2
SPSA 5PE
489
144 kbit
1.1
SPSA 1PE
489
144 kbit
0.23
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
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RC Toolbox
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Freely available RC Matlab toolbox (www.elis.ugent.be/rct)
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Simulation models for hardware quantization
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HW design methodology:
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Generic network and node settings
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Readout pipeline
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Generate network with hardware constraints
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Evaluate node quantization effects
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Automatically export to HW description
Compact hardware for real-time speech recognition using a LSM
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System
12 MHz
50 MHz
Compact hardware for real-time speech recognition using a LSM
IJCNN – August 13, 2007
100 MHz
150 MHz interc
Xilinx ML 401
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Conclusions
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Hardware real-time speech recognition in HW is possible with
very limited hardware
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Presented novel architecture for SNN implementation in HW
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Enlarges area/speed design space drastically
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Uses RC toolbox simulation environment for easy porting
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Future work: experiment with different applications; add further
SNN features such as SDTP, IP, dyn. synapses; and add the
possibility to change the weights
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