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Download Evaluates: MAX3890 MAX3890 Evaluation Kit General Description Features
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19-1554; Rev 1; 10/01 MAX3890 Evaluation Kit Component List DESIGNATION QTY C1–C6, C10, C11, 11 C13, C14, C15 DESCRIPTION 0.1µF ±10%, 25V min ceramic capacitors C7 1 0.33µF ±10%, 16V min, X7R type ceramic capacitor C8, C9, R1, R2, R23, JU6–JU9 0 Not installed C12 1 33µF capacitor Sprague 593D336X9020D J1–J6 6 SMA connectors (edge mount) J7–J22, J24–J43 36 SMB connectors (PC mount) J44, J45 2 SMA connectors (PC mount) J46, J47 2 Test points JU1–JU5 5 2-pin headers L1–L4 4 56nH inductors Coilcraft 0805CS-560XKBC R3 1 10kΩ ±5% resistor R4, R8, R12, R16 4 27Ω ±5% resistors R5, R9, R13, R17 4 24Ω ±5% resistors R6, R10, R14, R18 4 220Ω ±5% resistors R7, R11, R15, R19 4 130Ω ±5% resistors R20, R21 2 4.99kΩ ±1% resistors R22 1 20kΩ ±5% resistor U1 1 MAX3890 (64-pin TQFP-EP) None 1 MAX3890 PC board None 1 MAX3890 data sheet None 3 Shunts for JU1–JU3 Features ♦ +3.3V Single Supply ♦ Selectable Reference Clock Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) ♦ Fully Assembled and Tested Surface-Mount Board Ordering Information PART MAX3890EVKIT TEMP RANGE -40°C to +85°C IC PACKAGE 64 TQFP-EP* *Exposed Pad Component Suppliers SUPPLIER PHONE FAX Coilcraft 847-639-6400 847-639-1469 Sprague 207-324-4140 603-224-1430 Note: Please indicate that you are using the MAX3890 when contacting these suppliers. Detailed Description The MAX3890 EV kit simplifies evaluation of the MAX3890. The EV kit operates from a +3.3V single supply and includes all the external components necessary to interface with LVDS inputs and 3.3V positivereferenced emitter-coupled logic (PECL) outputs. The LVDS inputs (PDI_+, PDI_-, PCLKI+, PCLKI-, RCLK+, RCLK-)** are internally terminated with 100Ω differential input resistance and therefore do not require external termination. Ensure that LVDS devices driving these inputs are not redundantly terminated. The LVDS outputs (PCLKO+, PCLKO-) require a differential termination with a 100Ω resistor between complementary outputs. Do not terminate these outputs to ground. Layout Considerations The PECL outputs have voltage attenuation (0.46) and impedance matching networks on the EV board that allow 50Ω terminations to ground for oscilloscope interfacing. All signal inputs and outputs use coupled 50Ω transmission lines. All input signal lines are of equal length to minimize propagation-delay skew. Likewise, all output signal lines are of equal length. **Note: PCLKO±, PCLKI±, RCLK±, and SCLK± are labeled as PCKO±, PCKI±, RCK±, and SCK± on PC board. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. www.BDTIC.com/maxim 1 Evaluates: MAX3890 General Description The MAX3890 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3890 2.5Gbps 16:1 serializer with clock synthesis and low-voltage differential signal (LVDS) inputs. GND 3.3V J8 PCKI- J7 PCKI+ J6 SD0+ J5 SD0- J4 SCK0+ J3 SCK0- J2 SLB0+ J1 SLB0- J47 J46 R16 27Ω R12 27Ω R8 27Ω R4 27Ω C2 0.1µF C1 0.1µF C12 33µF 3.3V R18 220Ω R17 24Ω R14 220Ω R13 24Ω R10 220Ω R9 24Ω R6 220Ω R5 24Ω 3.3V 3.3V 3.3V R19 130Ω R15 130Ω R11 130Ω R7 130Ω R2 OPEN C3 0.1µF VCC0 JU1 GND J9 C10 0.1µF JU6 C8 OPEN VCCVC0 GND VCC SLBOSLBO+ VCC SOS VCC SCLKOSCLKO+ VCC SDOSDO+ VCC VCC PCLKI+ PCLKI- C11 0.1µF 1 2 3 4 VCCO 5 6 VCCO 7 8 9 10 11 12 VCCO 13 VCCDIG 14 15 16 VCCO C9 OPEN VCCPLL R22 20k VCCDIG Figure 1. MAX3890 EV Kit Schematic _______________________________________________________________________________________ www.BDTIC.com/maxim J10 J11 J12 C7 0.33µF JU5 JU4 JU3 J14 U1 MAX3890 J16 PDI12+ J15 PDI13+ PDI13- J13 PDI15+ PDI15- PDI14+ PDI14- R3 10k 3.3V VCCVCO L4 56nH C15 0.1µF VCCPLL VCC0 VCCDIG L3 56nH L2 56nH R1 OPEN 3.3V 3.3V 3.3V C13 0.1µF L1 56nH VCCDIG JU2 R21 4.99k C5 0.1µF J45 RCK- GND PDI2PDI2+ PDI3PDI3+ PDI4PDI4+ PDI5PDI5+ PDI6PDI6+ PDI7PDI7+ PDI8PDI8+ GND J17 PDI12- C6 0.1µF R20 4.99k C4 0.1µF VCCDIG JU9 JU8 JU7 J20 J21 PDI9+ J22 PDI9- R23 OPEN VCCDIG J42 PCKO+ C14 0.1µF GNDTEST J43 PCKO- PDI10+ PDI10- J19 PDI11- J18 PDI11+ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 J44 RCK+ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCC GND FIL+ FILVCC CKLSET RCLKRCLK+ VCC PCLKOPCLKO+ PDIOPDIO+ PDI1PDI1+ GND GND PDI15+ PDI15PDI14+ PDI14PDI13+ PDI13PDI12+ PDI12PDI11+ PDI11PDI10+ PDI10PDI9+ PDI9VCC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 2 VCCPLL J41 PDI0- J40 PDI0+ J39 PDI1- J38 PDI1+ J24 PDI8+ J25 PDI8- J26 PDI7+ J27 PDI7- J28 PDI6+ J29 PDI6- J30 PDI5+ J31 PDI5- J32 PDI4+ J33 PDI4- J34 PDI3+ J35 PDI3- J36 PDI2+ J37 PDI2- Evaluates: MAX3890 MAX3890 Evaluation Kit MAX3890 Evaluation Kit Exposed Pad Package The exposed pad (EP) 64-pin TQFP incorporates features that provide a very low thermal resistance path for heat removal from the IC—either to a PC board or to an external heatsink. The MAX3890’s EP must be soldered directly to a ground plane with good thermal conductance. Evaluates: MAX3890 Jumpers JU1 should be shorted for normal operation and removed to enable SLBO+ and SLBO- for system loopback testing. The MAX3890 EV kit allows the use of multiple reference clock frequencies with the appropriate setting on JU3, JU4, or JU5. See Table 1 for these jumper settings. Table 1. CLKSET Jumper Functions fRCLK (MHz) JU3 JU4 JU5 155.52 Shorted (to VCC) Open Open 77.76 Open Open Open 51.84 Open Shorted (20kΩ to ground) Open 38.88 Open Open Shorted (to ground) 1.0" Figure 2. MAX3890 EV Kit Component Placement Guide _______________________________________________________________________________________ www.BDTIC.com/maxim 3 Evaluates: MAX3890 MAX3890 Evaluation Kit 1.0" Figure 3. MAX3890 EV Kit PC Board Layout—Component Side 4 _______________________________________________________________________________________ www.BDTIC.com/maxim MAX3890 Evaluation Kit Evaluates: MAX3890 1.0" Figure 4. MAX3890 EV Kit PC Board Layout—Solder Side _______________________________________________________________________________________ www.BDTIC.com/maxim 5 Evaluates: MAX3890 MAX3890 Evaluation Kit 1.0" Figure 5. MAX3890 EV Kit PC Board Layout—Power Plane 6 _______________________________________________________________________________________ www.BDTIC.com/maxim MAX3890 Evaluation Kit Evaluates: MAX3890 1.0" Figure 6. MAX3890 EV Kit PC Board Layout—Ground Plane Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ______________________7 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. www.BDTIC.com/maxim
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