Download Exploring the limits: Development of Integrated High−Speed Circuits Prof. Dr. M. Möller

Exploring the limits:
Development of Integrated
High−Speed Circuits
Prof. Dr. M. Möller
Saarland University
MICRAM Microelectronic GmbH
Fig. 2
40th Anniversary − Moores Law Still Valid
M.Möller, Uni Saarland, MICRAM
Clock−Frequency / GHz
200.0
100.0
Todays operation area of
High−Speed Circuits
10.0
Moores Law:
double in about 20 months
Static Frequency Divider
1.0
Pentium CPU
III−V HBT
Si BJT
SiGe HBT
FET/HEMT
CMOS
1980
1985
1990
1995
2000
2005
Year
(Why) Does increase in speed slow down?
Fig. 3
Do we need (even) faster Semiconductor−Technologies?
M.Möller, Uni Saarland, MICRAM
max. divider frequency / GHz
Maximum Static Divider Frequency
in Si, SiGe und III/V Bipolar Technologies
Vitesse 04/04
VIP 2 Process
InP−DHBT, 4 LM.
USCB 01/05
InP−DHBT
3 LM+ BCB
150
Extrapolation by
Ichino ’94, Andre’98
Si−, SiGe
III−V
???
100
Research 06/2005:
InP/InGaAs PHBT
(Univ. Illinois)
50
600 GHz f T
246 GHz f max
@17 mA/m m 2
0
0
50
100
150
200
250
300
350
transistor cut−off frequency/ GHz
(fT ,f max )
Speed does not scale with transistor cut−off frequency − WHY ?
400
450
Fig. 4
Outline: Some Speed−Limiting Factors...
... And Ways to Surpass the Limits.
How fast is the "intrinsic" transistor?
Troublesome layout parasitics
High Mismatch − High−Speed
Borderline design: Speed−Optimisation
Chip−Assembly − a multidisciplinary challenge
Measurement setup − the Chicken and the Egg Dilemma
Some latest 100 Gbit/s Receiver/Transmitter results
"A rough overview from the circuit designers perspectice"
Fig. 4
What limits bipolar−transistor speed?
M.Möller, Uni Saarland, MICRAM
high−speed transistor, cross−section
base
emitter
collector
collector
Rc
C be
Rb
Ic
C cs
C cb
base
C cb
substrate
Rb
τf
Rc
C je
C cs
emitter
2 µm
substrate
high cut−off frequencies , f T fmax :
1
f T ~ C je
fmax=
+
τ
+
...
uT
f
Ic
Higher Speed
small R, C,
τ
small transistor size
high collector currrent I c
fT
8 π Rb C cb
high current density
Higher Current Density?
Fig. 6
Parasitic Capacitances of Transistor Metallization
M.Möller, Uni Saarland, MICRAM
E
short circuit at increasing frequency:
C
B
C
Transistor
B
Electromigration determines minimum metal cross−section area
E
Capacity reduction by:
lower dielectric constant
thicker dielectric
smaller metal width/area (eg. Copper insted of Aluminum)
Technological limit almost exhausted
New Materials/Technology
Fig. 7
Interconnect Parasitics Dominate Transistor Parasitics
M.Möller, Uni Saarland, MICRAM
microstrip
lines
Transistor
substrate
metal planes for
power−supply and
signal−line return path
Transistor
substrate
3−dimensional substrate−network
Layout: Very komplex 3−Dim. RLCM Network with major influence on the circuit’s speed.
Fig. 8
Layout Determines Speed−Limit
M.Möller, Uni Saarland, MICRAM
Example: Layout of 1:2 Clock Distribution Amplifier
metal stack:
section size: 130 x 170 um
4−layer metallization
EF2/EF3
M4: 3000 nm
900 nm, oxide 4
900 nm, oxide 3
M3: 600 nm
M2: 600 nm
900 nm, oxide 2
M1: 400 nm
900 nm, oxide 1
substrate
Small parasitic C: small (tall) wires, thick oxide, low dielectric constant
Small parasitic L: broad wires (tradeoff with C), short wires (often not possible) −> L becomes critical!
Fig. 9
Optimization Goal: Short Wiring
M.Möller, Uni Saarland, MICRAM
Section of a
43 Gb/s
CDR&DEMUX
1,8 x 2.5 mm 2
VCO
Clock−Signal
20 GHz, 2V
Clock Alignment
and Distribution
1:2 Clock
Distribution Amp.
Data In
40 Gb/s
20 mV
Input Amplifier
Differential
Strip−Line
Data Out
20 Gb/s
800 mV
Constraints: Line lengts of dedicated signals must be at the same length
Fig. 10
Design Rules Impact on Speed
M.Möller, Uni Saarland, MICRAM
Optimization−Spiral
cell
L
signal lines
Device Size & Design Rules
(Max. Current densities ...
Min. Spacing/width, ...
Overlap, Doughnuts ...
Resistor type, sheet resistance...)
cell
cell
3L
cell
e.g. clock
Driver power
Cell Size (L)
signal lines
3L−3∆
cell
cell
cell
Transmission Line Lengths
High−Speed needs High−Support by Design Rules
L− ∆
cell
Fig. 11
Bridgeover the Distance
M.Möller, Uni Saarland, MICRAM
Constraint: Need for global metallization planes
Micro−Strip Lines
Load (resistor R)
R
Micro−Strip Line
Impedance ZL
V
l
a
et
rm
ob
gl
I
al
m
et
al
e
p
up
Source
Current I
height "h"
(Supply plane is current return path)
Transfer function |Z| = V / I
(Power supply planes)
160
140
ZL=70 Ω
120
100
80
60
40
R=150 Ω
R= 50Ω
20
0
0
Line Impedance ZL ~
10
20
30
40
50
frequency / GHz
Example in Fig.:
ZL=50 Ω
70 Ω : h=2.2 µm
4.4 µ m
L
C
C ~ height "h"
C ~ epsr
L ~ 1/ line width ~ 1/C
ZL= 50 Ω
thick dielectric
& low epsr
high line impedance
Range of height and epsr limited: ZL < 80 Ohm
high bandwidth (speed)
& high gain (low power)
Fig. 12
Concept of Impedance Mismatch
M.Möller, Uni Saarland, MICRAM
high−ohmic!
Current Drive
Source I
~~ I
~~ I
∆I
low−ohmic!
Voltage Drive
low−ohmic!
~~ I
parasitic
Capacitance
Circuit input
including
Transmission−Line
high−ohmic!
Source ∆ V ~
~0
V
~~V
The More Mismatch
Load
Load
∆I
parasitic
Capacitance
~~V
The More Speed
Fig. 13
High−Speed Circuit Topology
M.Möller, Uni Saarland, MICRAM
Example: Amplifier Stage
Emitter−
follower
Transadmittance−
Stage
Transimpedance−
Stage
Emitter−
follower
(R=0: Current Switch)
Z
very high
high
Z
Z
very
low
high
R
very
high
Z
low
low
high
Double−Stage by Cherry/Hooper 1963
This is the Basic Principle Used in All High−Speed Circuits
Fig. 14
Complex−Conjugate Mismatch
M.Möller, Uni Saarland, MICRAM
Impedance characteristics of Source & Load
reverse as frequency increase
Trans−
admittance−
Iin
Stage
Im{Z}
Ω
Induktive, (L)
Emitter−
follower
f
f=0
Capacitive, (C)
0 10
Zin
Zout
Zout(f)
10K
1K
f=0
Re{Z}
Ω
f
Iout
Iin
Transfer−Function
with Emitterfollower
dB 15
Zin(f)
12
9
6
3
0
without Emitterfollower
0
5
10
15
Utilize Complex−Conjugate Mismatch to Increase Speed
20
25
f / GHz
Iout
Fig. 15
Transistor = Impedance−Transformator
M.Möller, Uni Saarland, MICRAM
Z
Zout =
Z
T
Zin = T Z + ...
+ ...
Z
T−Operator:
Impedances at the Base appear
rotated by 90° at the Emitter:
90°
L
ft
j f
Multiplication by T
rotates Z by − 90°
90°
− |R|
R
90°
T~
~
90°
(clockwise)
Impedances at the Emitter appear
rotated by −90° at the Base:
90°
L
90°
− |R|
R
90°
90°
C
Transformation Used to Optimize Pole/Zero Distribution of a Circuit
C
Fig. 16
Emitter−Follower Chain: A Tunable Resonance Network
M.Möller, Uni Saarland, MICRAM
V0
VI
V0
e.g. Trans−
admittance−
Stage
EF1
EF2
Transfer−Function
unstable
dB 10
5
EF3
0
−5
Peaking
by optimizing
Transistor−Parameters
−10
VI
−15
0
2
Shifting Dominationg Pole of Transfer−Function Shifting Dominationg Pole of Transfer−Function
by Variation of EF1 Base Resistance
by Variation of EF3 Base Resistance
f
GHz
14
13
stable
f
unstable
GHz 13
10
30
12
60
11 EF1: R
b Ω
10
9
−3 −2 −1
12
11
10
0
100
1
σ /GHz
unstable
stable
14
60
30
10
EF3: R b Ω
9
−3 −2 −1
0
1
σ /GHz
Great Opportunity to Increase Circuit Speed .... but ...
4
6
8 10 12 14
f / GHz
Fig. 17
Speed Optimized Circuits are Marginal Stable
M.Möller, Uni Saarland, MICRAM
Layout:
15 um length ~ 10pH
EF1
EF2
EF3
EF2
10 pH
Vin
Vin
Without 10 pH
Vin
With 10 pH
t
Proof of Stability: Every Litte Piece of Metal is Suspicious!
t
Feedback Path might be different than Signal Path
EF3
Fig. 18
Fast Technology: Low Breakdown Voltage (V CE0 )
M.Möller, Uni Saarland, MICRAM
Vcc (GND)
Vout
Circuits to prevent
for V CE0 breakdown
@ VCE= 4.5V
@ VCE= 5.5V
Vref
risky
slow
VCE
could be omitted
for V CE0 breakdown
@ VCE= 6.0V
@ VCE= 6.5V
Vee
Example:
Limit given by technology
VCEO = 2.5V
Green trace: Reference Output−Voltage @
V CEO = 2.5V
V CEO Limit can be extended up to V CBO by use of adequate Transistor−Models and Circuit Concepts
Fig. 19
Chip Assembly: High−Frequency Meets Precision Mechanics and Heat−Control
M.Möller, Uni Saarland, MICRAM
Conventional
Al/Au Bondwires
Coupled
Striplines
Ground−Frame
(multiple bonds)
Ground
Signal_p
Signal_n
Edge−Metallization
Ground
Chip
Teflon−Substrate
100µ m
Metal−Base
(Brass/Steel/Copper/CuW... )
electr. isolating
therm. conductive
Adhesive
Design Goals: Small Inductances, High Thermal Conductivity
Fig. 20
Using Bondwires to Optimize the Strip−Line to Chip Interface
M.Möller, Uni Saarland, MICRAM
Optimization goal:
E.g.: Optimization of Refection Coefficient
50 Ω −Stripline
on the Chip
coupled
50 Ω -Strip−Lines
Bondwire
Pads
−~
Z0 ~
−
S11
0
dB
L− ~ 50 Ω
~
C−
L−= 0
−10
L0
−20
k
−
L = 0,3 nH
−30
L0
Chip
−40
0
10
20
30
f/GHz
−
L = (1− k ) L 0
Odd−Mode−Inductance−L can be adjusted by bondwire spacing
Bondwire can be used also for Noise− and Pulsshape−Optimization
40
Fig. 21/22
High Speed = High Power Consumption
M.Möller, Uni Saarland, MICRAM
Power Density:
44 Gb/s
+
Chip:
1
W
mm2
Your kitchen hot−plate:
0.01
W
mm2
"Hot−Spots":
Areas of high power density
lead to local heat concentration
"Self−heating"
Transistor heat up due to its
own power
Time−constants in the ns−range!
Transistor cut−off frequency drops with increasing temperature:
Omit Hot−Spots
Spread Elements / Distribute Power Over Chip Area
But: Longer Wiring!
Fig. 23
Measurement of High−Speed Circuits
M.Möller, Uni Saarland, MICRAM
Actual Example:
Measurement of 100 Gbit/s SerDes ASICs
Agilent Sampling Scope
70 GHz, <300 fs Jitter
Agilent RF Generator 50 GHz
Agilent ParBert
8 Channels @ 12.5 Gbit/s
RZ−Patterns!
Agilent BERT
(12.5 Gbit/s)
Testbench
& DUT
Superposing 2 RZ Channels
12,5 Gbit/s −> 25 Gbit/s
The Chicken and the Egg Dilemma
Fig. 24
Measurement of 100 Gbit/s MUX and CDR&DEMUX Modules
M.Möller, Uni Saarland, MICRAM
100 Gbit/s 2:1 MUX with automatic
Clock−to−Data Timing Alignment
100 Gbit/s TIA & DEMUX (& CDR)
Output
1x12.5 Gbit/s
Input
4 x 25 Gbit/s
Measurement Concept with Auxiliary Circuits Must be Considered During Circuit Design
Fig. 25
100 Gbit/s Output Eye Diagram of 2:1 MUX Module
M.Möller, Uni Saarland, MICRAM
Technologie:
Infineon B10HF
fT = 225 GHz
f = 300 GHz
max
Outputsignal:
320 mVpp, single ended
< 400 fs Jitter
Fig. 26
86 Gbit/s Reveiver (TIA, DEMUX, CDR, VCO) with On−Chip PLL
M.Möller, Uni Saarland, MICRAM
German BMBF−Project:
MultiTeraNet
Technology:
Infineon B10HF
Measurement Results:
Min. Input Voltage (BER=0):
< 30 mV single ended
Recovered Clock:
< 400 fs Jitter
With Exteral VCO (50 GHz):
100 Gbit/s (BER=0)
That’s it for Today − Thank You!