Download RNA50C27A Datasheet CMOS System-Reset IC

Preliminary Datasheet
RNA50C27A
R03DS0064EJ0100
Rev.1.00
Aug 03, 2012
CMOS System-Reset IC
Description
This IC facilitates complicated power-on and power-monitoring resets of microcomputers that require the 3.3-V and
1.8-V dual power supplies. It also facilitates change of delay time of reset signal by externally setting resistance and
capacity for delay time. By employing complementary open-drain output, desired output such as open-drain output and
CMOS output can be obtained.
Functions








3.3-V detection voltage
Accuracy of 3.3-V detection voltage
Hysteresis of 3.3-V detection voltage
1.8-V detection voltage
Open-drain/CMOS output
1.8-V PMOS drive output
Package
Operating temperature
: 2.7 V
: 1.0%
: 5% Typ.
: 0.9 V Typ.
: 8-pin SSOP-8/MMPAK-8
: –40 to +85°C
Ordering Information
Part Name
RNA50C27AUSEL-E
RNA50C27AMMEL-E
Package Type
SSOP-8
MMPACK-8
Package Code
PVSP0008KA-A
PLSP0008JC-A
Package
Abbreviation
US
MM
Taping Abbreviation
(Quantity)
EL (3,000 pcs / Reel)
EL (3,000 pcs / Reel)
Surface
Treatment
E (Sn-Bi)
E (Sn-Bi)
Block Diagram
MR
8
CRext
7
VDD33 1
–
+
Delay
2 RESP
3 RESN
Vref
VDD18 6
5 SWG
GND 4
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 1 of 29
RNA50C27A
Preliminary
Pin Arrangement
VDD33
1
8
MR
RESP
2
7
CRext
RESN
3
6
VDD18
GND
4
5
SWG
(Top view)
Pin Description
Pin No.
1
Pin Name
VDD33
Function
Input power supply pin for 3.3 V voltage.
Recommended operating range is VTH33 to 3.6 V.
Set input voltage to 0.033 V/s or less when starting up.
If input voltage terminal VDD33 was momentary (VDD33 pin input voltage is lower than
detection voltage state period of short), for discharge of external capacitance becomes
insufficient, delay time will be very short.
Please check if there is any problem as a system.
2
RESP
Pull-down when reset signal output pin.
By connecting to RESN pin, CMOS output can be used.
3
RESN
4
5
GND
SWG
Pull-up when reset signal output pin.
By connecting to RESP pin, CMOS output can be used.
GND pin
6
VDD18
Input power supply pin for 1.8 V voltage.
Recommended operating range is 1.65 V to VDD33.
When terminal voltage is below 0.9 V Typ, and outputs high-level signal SWG.
7
CRext
Terminal is for determining Rext resistance and Cext capacitance of reset signal delay time.
Resistance is recommended for more than 3.3 k.
Delay time is given by tDLY = Cext  Rext [s]
Does not output reset signal when this pin is not high-level.
Connect external resistor for VDD33 necessarily.
8
MR
This terminal outputs a reset signal manually.
Has been pull-up internally 2 M.
If behavior is unstable, behavior is stabilized by connecting 220 pF to this pin to GND.
In addition, or when connected to potential, such as VDD33 to force this pin to external, pulse
width input to the MR be shorter than discharge time of CRext is, please note for delay
normal can not be obtained.
To be installed between 1.8 V power supply and 1.8 V voltage input of microcomputer, gate
of PMOS is external control signal.
It has been designed with load capacity of 2200 pF Typ., will change size of rise time/fall
time of SWG capacity.
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 2 of 29
RNA50C27A
Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item
Supply voltage
Input voltage
Output voltage
Symbol
VDD33
VDD18
VI
VO
Input current
Output current
Supply current
Power dissipation
II
IO
IDD
PT
Terminal
VDD33
VDD18
MR, CRext
RESP, RESN
SWG
MR, CRext
RESP, RESN, SWG
VDD33, VDD18
—
Storage temperature
Tstg
—
Ratings
4.6
4.6
–0.3 to VDD33
–0.3 to VDD33
–0.3 to VDD18
20
20
25
160
145
–55 to +125
Unit
V
Remarks
V
V
mA
mA
mA
mW
SSOP-8
MMPAK-8
°C
Recommended Operating Conditions
(Ta = 25°C)
Item
Supply voltage
Input voltage
Output voltage
Symbol
VDD33
VDD18
VI
VO
External resistor
External capacitor
MR pin capacitor
Drivable capacitor
Operating temperature
Rext
Cext
CMR
CL
Ta
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Terminal
VDD33
VDD18
MR, CRext
RESP
RESN
SWG
CRext
CRext
MR
SWG
—
Min
VTH33
1.65
0
0
0
0
3.3
—
—
—
–40
Typ
—
—
—
—
—
—
—
Nolimit
220
2200
—
Max
3.6
VDD33
VDD33
VDD33
VDD33
VDD18
—
—
—
—
85
Unit
V
Remarks
V
V
k
F
pF
pF
°C
VDD33 = 3.3V
SWG output
Page 3 of 29
RNA50C27A
Preliminary
Electrical Characteristics
DC Characteristics
(VDD33 = 3.3V, VDD18 = 1.8V, Ta = 25°C, Rext = 10k)
Item
Quiescent supply current
Detection voltage temperature
dependency
Symbol
IDD33
IDD18
VTH33
VTH18H
VTH18L
ΔVTH33
VTH33 ⋅ ΔTa
Detection voltage hysteresis
MR
Low-level input voltage
High-level input voltage
Internal pull-up resistance
CMOS Low-level output current
High-level output current
RESP
Output leakage current
High-level output current
RESN
Low-level output current
Output leakage current
SWG
Low-level output current
High-level output current
Low-level output voltage
High-level output voltage
VHYS
VIL
VIH
RMR
IOL
IOH
IOLEAK
IOH
IOL
IOLEAK
IOL
IOH
VOL
VOH
Detection voltage
Note:
Min
0.6
0.3
2.673
1.2
—
—
Typ
2.0
1.0
2.700
—
—
(100)
Max
8.0
3.0
2.727
—
0.6
—
VTH331.03
—
2.805
—
5
5
—
5
5
—
0.2
1.0
—
1.7
VTH331.05
—
—
(2.0)
15
10
(0.1)
10
15
(0.1)
0.35
3.0
—
—
VTH331.08
0.495
—
—
20
13
—
13
20
—
0.6
6.0
0.1
—
Unit
A
Test Conditions
V
ppm/°C
V
V
V
M
mA
A
mA
mA
A
mA
V
VO = 0.5V
VO = 2.8V
VO = 0.5V
VO = 2.8V
VO = 0.5V
VO = 2.8V
VO = 0.5V
VO = 1.3V
SWG = OPEN
When the voltage within VIL < VIN < VIH is applied to MR and VDD18 input by DC, oscillation may occur.
When RESP output and RESN short out and CMOS output is used.
AC Characteristics
(VDD33 = 3.3V, VDD18 = 1.8V, Ta = 25°C, Rext = 10k, RL = 100k, CL = 15pF)
CMOS
Item
Propagation delay time
Response time
RESP
Propagation delay time
Response time
RESN
Propagation delay time
Response time
SWG
Propagation delay time
Response time
Delay time
Symbol
tpLH
tpHL
tr
tf
tpLH
tpHL
tr
tf
tpLH
tpHL
tr
tf
tpHL
tpLH
tf
tr
tDLY
Min
Typ
Max
Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
(10) *
3
(5) *
2
(93) *
(500) *1
(100) *1
(100) *1
(100) *1
500 *2
(100) *3
(100) *3
3
(100) *
2
500 *
(100) *3
(100) *3
(100) *3
500 *2
100 *2
—
—
—
s
Test Conditions
ns
s
ns
s
s
s
ns
s
CL = 2200pF
s
CL = 2200pF
ms
Cext = 0.1F,
Rext = 1M
Notes: ( ) is a design reference value.
*1 Estimated from measured value of RESP, RESN (Will vary considerably depending on conditions).
*2 Edge is triggered 0 V3.3 V, 3.3 V0 V when change of maximum delay path VDD33.
*3 Signal to trigger MR.
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 4 of 29
RNA50C27A
Preliminary
Timing Chart
VHYS
VTH33
Vop_min
VDD33
VTH18H
VTH18L
VDD18
*1
VIH
VIL
MR
tDLY
tDLY
tDLY
tDLY
tDLY
tDLY
RES
SWG
Note:
MR has been pulled up to VCC by the internal resistance. Timing diagram is in phase with signal of VDD33.
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 5 of 29
RNA50C27A
Preliminary
Table of Graphs
DC Characteristics
Item
Quiescent supply current
Detection voltage
Detection voltage temperature
dependency
Detection voltage hysteresis
MR
Input voltage
Symbol
IDD33
IDD18
VTH33
VTH18H
VTH18L
vs. VDD33
Fig. 1-1
—
—
—
—
vs. VDD18
—
Fig. 2-1
—
—
—
vs. Ta
Fig. 3-1
Fig. 3-2
Fig. 3-3
Fig. 3-5
Fig. 3-5
Other
—
—
—
—
—
Test Circuit
1
1
2
3
3
—
—
—
—
2
—
Fig. 1-2, 3
Fig. 1-2, 3
—
—
—
Fig. 3-4
Fig. 3-6
Fig. 3-6
—
—
—
2
4
4
RMR
—
—
Fig. 3-7
—
5
IOLEAK
Fig. 1-4
Fig. 1-5
Fig. 1-6
Fig. 1-7
—
—
—
—
Fig. 3-8
Fig. 3-9
Fig. 3-10
Fig. 3-11
—
—
—
—
8
7
6
9
—
—
Fig. 2-2
Fig. 2-3
Fig. 3-12
Fig. 3-13
—
—
13
11
Symbol
tpLH
vs. VDD33
Fig. 1-8
vs. VDD18
—
vs. Ta
Fig. 3-14
Other
—
Test Circuit
14
tpHL
tr
tf
tpLH
Fig. 1-9
Fig. 1-10
Fig. 1-11
Fig. 1-12
—
—
—
—
Fig. 3-15
Fig. 3-16
Fig. 3-17
Fig. 3-18
—
—
—
—
17
20
23
15
tpHL
tr
Fig. 1-13
Fig. 1-14
—
—
Fig. 3-19
Fig. 3-20
—
—
18
21
tf
tpHL
Fig. 1-15
Fig. 1-16
—
—
Fig. 3-21
Fig. 3-22
—
—
24
16
tpLH
tf
Fig. 1-17
Fig. 1-18
—
—
Fig. 3-23
Fig. 3-24
—
—
19
22
tr
Fig. 1-19
Fig. 1-20
—
Fig. 2-4
Fig. 3-25
Fig. 3-26
—
Fig. 4-1
25
26
VHYS
VIL
VIH
RESP
RESN
SWG
Internal pulled-up
resistor
Output current
Output current
Output current
IOH
IOL
IOLEAK
IOL
IOH
AC Characteristics
Item
RESP
Propagation delay
time
Response time
RESN
Propagation delay
time
Response time
SWG
Propagation delay
time
Response time
Delay time
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
tDLY
Page 6 of 29
RNA50C27A
Preliminary
Test Circuits
1. Quiescent supply curren, IDD33, IDD18
IDD33
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
A
IDD18
A
VDD18
= 1.8 V
V1
2. Detection voltage, VTH33
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VDD33
VDD33
V1
VDD18
= 1.8 V
VHYS
V1
V
VDD33
VTH33
VDD33
= 3.3 V
V1
3. Detection voltage, VTH18H, VTH18L
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VDD18
VTH18H
Release Voltage
V
VDD18
V1
V1
VDD18
VTH18L
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Detection Voltage
Page 7 of 29
RNA50C27A
Preliminary
MR
RESP
CRext
RESN
VDD18
GND
SWG
V1
Rext
= 10 kΩ
VDD33
VMR
VDD18
= 1.8 V
V
VIH
Release Voltage
V1
VDD33
= 3.3 V
VDD33
V1
4. MR pin Input voltage Low-level / High-level, VIL/VIH
VMR
VDD33
VMR
VIL Detection Voltage
VDD33
= 3.3 V
IMR
5. MR pin Internal pulled-up resistor, RMR
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
IMR
I2
A
V
I1
V1
VDD18
= 1.8 V
VMR
RMR =
V2
VMR
(V2 – V1)
[Ω]
(I2 – I1)
6. CMOS(RESN) Output current Low-level, IOL
IOL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
A
VO
= 0.5 V
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
VDD18
= 1.8 V
Page 8 of 29
RNA50C27A
Preliminary
7. CMOS(RESP) Output current High-level, IOH
IOH
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
A
VO
= 2.8 V
VDD18
= 1.8 V
8. RESP pin Output leakage current, IOLEAK
IOLEAK
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
A
VDD18
= 1.8 V
VO
= 0.5 V
9. RESN pin Output leakage current, IOLEAK
IOLEAK
VDD33
= 3.3 V
A
VO
= 2.8 V
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VDD18
= 1.8 V
Page 9 of 29
RNA50C27A
Preliminary
10. SWG Output voltage High-level, VOH
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
V
VDD18
= 1.8 V
11. SWG pin Output current High-level, IOH
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
IOH
A
VO
= 1.3 V
VDD18
= 1.8 V
12. SWG Output voltage Low-level, VOL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
V
VDD18
= 1.8 V
13. SWG pin Output current Low-level, IOL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
IOL
A
VO
= 0.5 V
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
VDD18
= 1.8 V
Page 10 of 29
RNA50C27A
Preliminary
14. Propagation delay time RESP, tpLH
VDD33
VDD33
= 3.3 Vpp
V
VO
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
3.3 V
0V
RL
V
VHYS
VDD18
= 1.8 V
tpLH
VO
1.65 V
3.3 V
0V
RL = 100 kΩ
t
15. Propagation delay time RESN, tpLH
VDD33
RL
VDD33
= 3.3 Vpp
V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
3.3 V
0V
VO
V
VHYS
VDD18
= 1.8 V
tpLH
VO
1.65 V
3.3 V
0V
RL = 100 kΩ
t
16. Propagation delay time SWG, tpHL
VDD33
VDD33
= 3.3 Vpp
V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
3.3 V
0V
tpHL
1.8 V
VO
1.8 V
VDD18
= 1.8 V
CL = 2200 pF
VHYS
Rext
= 10 kΩ
0.9 V
VO
V
t
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 11 of 29
RNA50C27A
Preliminary
17. Propagation delay time RESP, tpHL
VDD33
= 3.3 V
VO
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
RL = 100 kΩ
3.3 V
1.65 V
tpHL
VO
3.3 V
RL
V
VMR
3.3 V
Rext
= 10 kΩ
1.65 V
VDD18
= 1.8 V
VMR
= 3.3 Vpp
3.3 V
V
t
18. Propagation delay time RESN, tpHL
RL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
RL = 100 kΩ
3.3 V
1.65 V
tpHL
VO
3.3 V
VO
V
VMR
3.3 V
Rext
= 10 kΩ
1.65 V
VDD18
= 1.8 V
VMR
= 3.3 Vpp
3.3 V
V
t
19. Propagation delay time SWG, tpLH
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VMR
= 3.3 Vpp
VO
VDD18
= 1.8 V
CL = 2200 pF
V
V
VMR
3.3 V
3.3 V
1.65 V
tpLH
VO
1.8 V
0.9 V
0V
t
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 12 of 29
RNA50C27A
Preliminary
20. Rising Response time RESP, tr
VDD33
= 3.3 V
VO
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
0V
RL = 100 kΩ
VO
2.97 V
0.33 V
tr
RL
V
3.3 V
VDD18
= 1.8 V
VMR
= 3.3 Vpp
t
21. Rising Response time RESN, tr
RL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
3.3 V
0V
VO
2.97 V
0.33 V
tr
VO
V
RL = 100 kΩ
VDD18
= 1.8 V
VMR
= 3.3 Vpp
t
22. Falling Response time SWG, tf
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VMR
= 3.3 Vpp
VO
VDD18
= 1.8 V
CL = 2200 pF
V
VO
1.8 V
1.62 V
0.18 V
0V
tf
t
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 13 of 29
RNA50C27A
Preliminary
23. Falling Response time RESP, tf
VDD33
= 3.3 V
VO
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
RL = 100 kΩ
2.97 V
0.33 V
0V
tf
RL
V
VO
3.3 V
VDD18
= 1.8 V
VMR
= 3.3 Vpp
t
24. Falling Response time RESN, tf
RL
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
RL = 100 kΩ
2.97 V
0.33 V
0V
tf
VO
V
VO
3.3 V
VDD18
= 1.8 V
VMR
= 3.3 Vpp
t
25. Falling Response time SWG, tr
VDD33
= 3.3 V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 10 kΩ
VMR
= 3.3 Vpp
VO
VDD18
= 1.8 V
CL = 2200 pF
V
VO
1.62 V
1.8 V
0V
0.18 V
tr
t
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 14 of 29
RNA50C27A
Preliminary
26. Delay time, tDLY
VDD33
VDD33
= 3.3 Vpp
V
VO
V
VDD33
MR
RESP
CRext
RESN
VDD18
GND
SWG
Rext
= 1 MΩ
VHYS
3.3 V
0V
VDD18
= 1.8 V
Cext
= 0.1 μF 0 V
tDLY
VO
1.65 V
3.3 V
t
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 15 of 29
RNA50C27A
Preliminary
Main Characteristics
Figure 1-1.
Supply Current vs. Supply Voltage
Supply Current, IDD33 (A)
1.0E–03
1.0E–04
1.0E–05
1.0E–06
1.0E–07
2
3
4
5
Supply Voltage, VDD33 (V)
Figure 1-3.
Manual Reset of Output Threshold
Voltage SWG vs. Supply Voltage
5
Manual Reset Threshold Voltage, VRM (V)
Manual Reset Threshold Voltage, VRM (V)
Figure 1-2.
Manual Reset Threshold Voltage of
Reset Output vs. Supply Voltage
4
3
VIH
VIL
2
1
0
2
3
4
3
VIH, VIL
2
1
0
2
5
4
3
4
5
Supply Voltage, VDD33 (V)
Supply Voltage, VDD33 (V)
Figure 1-4.
RESP Output Leakage Current vs. Output Voltage
Figure 1-5.
RESP Output Current vs. Output Voltage
0.00
1.0E–07
VDD33 = 2.4 V
Ta = 25°C, V_MR = 0 V
Output Current, IOH (A)
Output Leakage Current, IoLEAK (A)
5
5.0E–08
VDD33 = 2.4 V,
VDD33 = 3.3 V,
VDD33 = 4.6 V
0.0E+00
–5.0E–08
–1.0E–07
–0.02
VDD33 = 3.3 V
–0.04
VDD33 = 4.6 V
–0.06
–0.08
Ta = 25°C, V_MR = VDD33 V
–0.10
0
1
2
3
Output Voltage, VOL (V)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
4
5
0
1
2
3
4
5
Differential Output Voltage from VDD33, VOH (V)
Page 16 of 29
RNA50C27A
Preliminary
Figure 1-6.
RESN Output Current vs. Output Voltage
Figure 1-7.
RESN Output Leakage Current vs. Output Voltage
0.10
1.0E–07
Output Leakage Current, IoLEAK (A)
Output Current, IOL (A)
Ta = 25°C, V_MR = 0 V
0.08
VDD33 = 4.6 V
0.06
0.04
VDD33 = 3.3 V
Ta = 25°C, V_MR = VDD33 V
5.0E–08
VDD33 = 2.4 V,
VDD33 = 3.3 V,
VDD33 = 4.6 V
0.0E+00
–5.0E–08
0.02
VDD33 = 2.4 V
0.00
–1.0E–07
0
1
2
3
4
5
0
1
2
3
5
4
Output Voltage, VOL (V)
Figure 1-8.
RESP Output Rising Propagation Delay Time vs. Supply Voltage
Figure 1-9.
RESP Output Falling Propagation Delay Time vs. Supply Voltage
200
Falling Propagation Delay Time, tpHL (ns)
Rising Propagation Delay Time, tpLH (μs)
Output Voltage, VOL (V)
150
100
RL, CRext = 1 MΩ
50
RL, CRext = 100 kΩ
0
2
3
4
8
6
4
RL, CRext = 100 kΩ
2
RL, CRext = 1 MΩ
0
2
5
3
4
5
Supply Voltage, VDD33 (V)
Supply Voltage, VDD33 (V)
Figure 1-10.
RESP Output Rising Response Time vs. Supply Voltage
Figure 1-11.
RESP Output Falling Response Time vs. Supply Voltage
20
Falling Response Time, tf (ns)
20
Rising Response Time, tr (ns)
10
15
RL, CRext = 100 kΩ
10
5
RL, CRext = 1 MΩ
0
15
RL, CRext = 100 kΩ
10
RL, CRext = 1 MΩ
5
0
2
3
4
Supply Voltage, VDD33 (V)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
5
2
3
4
5
Supply Voltage, VDD33 (V)
Page 17 of 29
RNA50C27A
Preliminary
200
150
100
RL, CRext = 1 MΩ
50
RL, CRext = 100 kΩ
0
2
3
4
Figure 1-13.
RESN Output Falling Propagation Delay Time vs. Supply Voltage
Falling Propagation Delay Time, tpHL (ns)
Rising Propagation Delay Time, tpLH (μs)
Figure 1-12.
RESN Output Rising Propagation Delay Time vs. Supply Voltage
8
RL, CRext = 1 MΩ
6
4
2
RL, CRext = 100 kΩ
0
5
2
3
4
5
Supply Voltage, VDD33 (V)
Supply Voltage, VDD33 (V)
Figure 1-14.
RESN Output Rising Response Time vs. Supply Voltage
Figure 1-15.
RESN Output Falling Response Time vs. Supply Voltage
50
Falling Response Time, tf (ns)
50
Rising Response Time, tr (ns)
10
40
RL, CRext = 1 MΩ
30
20
10
RL, CRext = 100 kΩ
40
RL, CRext = 1 MΩ
30
20
10
RL, CRext = 100 kΩ
0
0
2
3
4
2
5
3
4
5
Supply Voltage, VDD33 (V)
Figure 1-16.
SWG Output Rising Propagation Delay Time vs. Supply Voltage
Figure 1-17.
SWG Output Falling Propagation Delay Time vs. Supply Voltage
200
Falling Propagation Delay Time, tpLH (μs)
Rising Propagation Delay Time, tpHL (μs)
Supply Voltage, VDD33 (V)
150
100
CL = 2200 pF, CRext = 1 MΩ
CL = 2200 pF, CRext = 100 kΩ
50
0
2
3
4
Supply Voltage, VDD33 (V)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
5
10
8
6
4
CL = 2200 pF, CRext = 1 MΩ
CL = 2200 pF, CRext = 100 kΩ
2
0
2
3
4
5
Supply Voltage, VDD33 (V)
Page 18 of 29
RNA50C27A
Preliminary
Figure 1-18.
SWG Output Rising Response Time vs. Supply Voltage
Figure 1-19.
SWG Output Falling Response Time vs. Supply Voltage
10
Falling Response Time, tr (μs)
Rising Response Time, tf (μs)
50
40
30
20
CL = 2200 pF, CRext = 1 MΩ
CL = 2200 pF, CRext = 100 kΩ
10
8
6
4
CL = 2200 pF, CRext = 1 MΩ
CL = 2200 pF, CRext = 100 kΩ
2
0
0
2
3
4
5
Supply Voltage, VDD33 (V)
2
3
4
5
Supply Voltage, VDD33 (V)
Figure 1-20.
Reset Output Delay Time vs. Supply Voltage
Delay Time, tDLY (ms)
200
150
CL = 2200 pF, CRext = 0.1 μF, 1 MΩ
100
50
CL = 2200 pF, CRext = 0.1 μF, 100 kΩ
0
2
3
4
5
Supply Voltage, VDD33 (V)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 19 of 29
RNA50C27A
Preliminary
Figure 2-1.
Supply Current vs. Supply Voltage
Supply Current, IDD18 (μA)
1.0E–03
1.0E–04
1.0E–05
1.0E–06
1.0E–07
1.0E–08
1
2
3
4
5
Supply Voltage, VDD18 (V)
Figure 2-3.
SWG Output Current vs. Output Voltage
Figure 2-2.
SWG Output Current vs. Output Voltage
0.00
0.010
VDD18 = 1.6 V
VDD18 = 1.8 V
0.008
Output Current, IOH (A)
Output Current, IOL (A)
Ta = 25°C, V_MR = VDD33 V
0.006
VDD18 = 4.6 V
0.004
0.002
–0.01
–0.02
–0.03
VDD18 = 4.6 V
–0.04
VDD18 = 1.8 V
Ta = 25°C, V_MR = 0 V
–0.05
0.000
0
1
2
3
4
5
0
1
2
3
4
5
Differential Output Voltage from Supply Voltage, VOH (V)
Output Voltage, VOL (V)
Figure 2-4.
Reset Output Delay Time vs. Supply Voltage
Delay Time, tDLY (ms)
200
150
CL = 2200 pF, CRext = 0.1 μF, 1 MΩ
100
50
CL = 2200 pF, CRext = 0.1 μF, 100 kΩ
0
1
2
3
4
5
Supply Voltage, VDD18 (V)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 20 of 29
RNA50C27A
Preliminary
Figure 3-1.
Supply Current vs. Ambient Temperature
Figure 3-2.
Supply Current vs. Ambient Temperature
Supply Current, IDD18 (μA)
10
8
6
4
2
0
–50
–25
0
25
50
75
2
–25
0
25
50
75
100
Figure 3-3.
Detection Voltage vs. Ambient Temperature
Figure 3-4.
Detection Voltage Hysteresis vs. Ambient Temperature
Detection Voltage Hysteresis Ratio (%)
Detection Voltage, VTH33 (V)
Detection Voltage, VTH18H, VTH18L (V)
4
Ambient Temperature, Ta (°C)
VHYS
2.85
2.80
2.75
VTH33
2.70
2.65
–25
0
25
50
75
10
8
6
4
2
0
–50
100
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Ambient Temperature, Ta (°C)
Figure 3-5.
Detection Voltage vs. Ambient Temperature
Figure 3-6.
Manual Reset Threshold Voltage vs. Ambient Temperature
1.8
1.5
1.2
0.9
0.6
0.3
0
–50
6
Ambient Temperature, Ta (°C)
2.90
2.60
–50
8
0
–50
100
–25
0
25
50
Ambient Temperature, Ta (°C)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
75
100
Manual Reset Threshold Voltage, VTHMR (V)
Supply Current, IDD33 (μA)
10
4
3
2
VIH_RST
1
VIL_RST
VIH_SWG
VIL_SWG
0
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Page 21 of 29
RNA50C27A
Preliminary
Figure 3-7.
Internal Pulled-up Resistor vs. Ambient Temperature
Resistance Value, RMR (MΩ)
5
4
3
2
1
0
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Figure 3-8.
RESP Output Leakage Current vs. Ambient Temperature
Figure 3-9.
RESP Output Current vs. Ambient Temperature
0.000
VDD33 = 3.3 V, VDD18 = 1.8 V, Vo = 0 V
VDD33 = 3.3 V, VDD18 = 1.8 V, VOH = 2.8 V
Output Current, IOH (A)
Output Leakage Current, IoLEAK (A)
1.0E–08
5.0E–09
0.0E+00
–5.0E–09
–1.0E–08
–50
–25
0
25
50
75
–0.010
–0.015
–0.020
–50
100
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Ambient Temperature, Ta (°C)
Figure 3-10.
RESN Output Current vs. Ambient Temperature
Figure 3-11.
RESN Output Leakage Current vs. Ambient Temperature
1.0E–08
0.05
Output Leakage Current, IoLEAK (A)
VDD33 = 3.3 V, VDD18 = 1.8 V, VOL = 0.5 V
Output Current, IOL (A)
–0.005
0.04
0.03
0.02
5.0E–09
0.0E+00
–5.0E–09
0.01
0.00
–50
VDD33 = 3.3 V, VDD18 = 1.8 V, VOL = 3.3 V
–25
0
25
50
Ambient Temperature, Ta (°C)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
75
100
–1.0E–08
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Page 22 of 29
RNA50C27A
Preliminary
Figure 3-12.
SWG Output Current vs. Ambient Temperature
Figure 3-13.
SWG Output Current vs. Ambient Temperature
1.0E–03
0.000
VDD33 = 3.3 V, VDD18 = 1.8 V, VOL = 1.3 V
8.0E–04
Output Current, IOH (A)
Output Current, IOL (A)
VDD33 = 3.3 V, VDD18 = 1.8 V, VOL = 0.5 V
6.0E–04
4.0E–04
2.0E–04
–25
0
25
50
75
–0.006
–0.008
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Ambient Temperature, Ta (°C)
Figure 3-14.
RESP Output Rising Propagation Delay Time
vs. Ambient Temperature
Figure 3-15.
RESP Output Falling Propagation Delay Time
vs. Ambient Temperature
200
150
100
50
0
–50
–25
0
25
50
75
100
8
6
4
2
0
–50
–25
0
25
50
75
Ambient Temperature, Ta (°C)
Figure 3-16.
RESP Output Rising Response Time
vs. Ambient Temperature
Figure 3-17.
RESP Output Falling Response Time
vs. Ambient Temperature
100
20
Falling Response Time, tf (ns)
15
10
5
0
–50
10
Ambient Temperature, Ta (°C)
20
Rising Response Time, tr (ns)
–0.004
–0.010
–50
100
Falling Propagation Delay Time, tpHL (ns)
Rising Propagation Delay Time, tpLH (μs)
0.0E+00
–50
–0.002
–25
0
25
50
Ambient Temperature, Ta (°C)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
75
100
15
10
5
0
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Page 23 of 29
RNA50C27A
Preliminary
200
150
100
50
0
–50
Figure 3-19.
RESN Output Falling Propagation Delay Time
vs. Ambient Temperature
Falling Propagation Delay Time, tpHL (ns)
Rising Propagation Delay Time, tpLH (μs)
Figure 3-18.
RESN Output Rising Propagation Delay Time
vs. Ambient Temperature
–25
0
25
50
75
100
6
4
2
0
–50
–25
0
25
50
75
Ambient Temperature, Ta (°C)
Figure 3-20.
RESN Output Rising Response Time
vs. Ambient Temperature
Figure 3-21.
RESN Output Falling Response Time
vs. Ambient Temperature
100
Falling Response Time, tf (ns)
50
40
30
20
10
0
–50
–25
0
25
50
75
40
30
20
10
0
–50
100
–25
0
25
50
75
Ambient Temperature, Ta (°C)
Ambient Temperature, Ta (°C)
Figure 3-22.
SWG Output Falling Propagation Delay Time
vs. Ambient Temperature
Figure 3-23.
SWG Output Rising Propagation Delay Time
vs. Ambient Temperature
200
Rising Propagation Delay Time, tpLH (μs)
Rising Response Time, tr (ns)
8
Ambient Temperature, Ta (°C)
50
Falling Propagation Delay Time, tpHL (μs)
10
150
100
50
0
–50
–25
0
25
50
Ambient Temperature, Ta (°C)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
75
100
100
10
8
6
4
2
0
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Page 24 of 29
RNA50C27A
Preliminary
Figure 3-25.
SWG Output Rising Response Time
vs. Ambient Temperature
Figure 3-24.
SWG Output Falling Response Time
vs. Ambient Temperature
10
Rising Response Time, tr (μs)
Falling Response Time, tf (μs)
50
40
30
20
10
0
–50
–25
0
25
50
75
8
6
4
2
0
–50
100
Ambient Temperature, Ta (°C)
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Figure 3-26.
Reset Output Delay Time vs. Ambient Temperature
Delay Time, tDLY (ms)
200
150
100
50
0
–50
–25
0
25
50
75
100
Ambient Temperature, Ta (°C)
Figure 4-1.
Reset Output Delay Time vs. External Resistor
1000
0.33 μF
0.1 μF
0.033 μF
100
10
1
0.1
1
1 MΩ
10 MΩ
Delay Time, tDLY (ms)
Delay Time, tDLY (ms)
1000
Figure 4-2.
Reset Output Delay Time vs. External Capacitance
10
100
External Resistor, Rext (kΩ)
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
1000
100 kΩ
100
10
1
0.1
0.001
0.010
0.100
1.000
External Capacitance, Cext (μF)
Page 25 of 29
RNA50C27A
Preliminary
Package Dimensions
RNA50C27AUS
JEITA Package Code
P-VSSOP8-2.3x2-0.50
RENESAS Code
PVSP0008KA-A
Previous Code
TTP-8DB/TTP-8DBV
MASS[Typ.]
0.010g
D
F
1.5 ±0.2
8
5
bp
c
HE
E
c1
b1
Terminal cross section
Min Nom Max
D
1.8 2.0 2.2
E
2.2 2.3 2.4
A2 0.6 0.7 0.8
A1
0.1
0
A
bp 0.15 0.22 0.3
b1
0.20
c
0.08 0.13 0.23
c1
0.11
θ
HE 2.8 3.1 3.4
e
(0.5)
x
y
Z
L
L1
(0.4)
bp
A1
A2
( 0.17 )
e
Reference Dimension in Millimeters
Symbol
L1
4
1
Detail F
0.5
Unit: mm
0.3
0.2
0.4
0.1
3.1
0.5
2.3
0.5
SSOP-8 Footprint Example
Note: These numbers on the diagram are reference values.
Please adjust size, space, and other area of footprint as needed.
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 26 of 29
RNA50C27A
Preliminary
RNA50C27AMM
Package Name
MMPAK-8
JEITA Package Code
P-LSOP8-2.8 x 2.95 - 0.65
RENESAS Code
PLSP0008JC-A
Previous Code
⎯
MASS[Typ.]
0.02 g
Unit: mm
0.13 +0.12
-0.03
2.8 ± 0.1
4.0 ± 0.3
2.95 ± 0.2
0.6
0 to 0.1
0.65
0.1 M
0.2
+0.1
-0.05
0.3
1.1 ± 0.1
1.95
0.1
4.7
0.75
3.2
0.75
Unit: mm
0.35
0.65
MMPAK-8 Footprint Example
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 27 of 29
RNA50C27A
Preliminary
Taping and Reel Specifications
4
1.75
SSOP-8
φ1.5
2
Unit: mm
8
3.4
3.5
1.0
2.25
0.3
φ1.05
4
Reel type: C
4 ± 0.5
0°
2.0 ± 0.5
φ178 ± 2
12
φ13 ± 0.5
13.0
Maximum storage No.:
3000 pcs./Reel
9.0
4
1.75
MMPAK-8
φ1.55
2
Unit: mm
12.0
4.5
5.5
1.0
3.35
0.3
φ1.05
4
Reel type: C
4 ± 0.5
0°
13.0
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
φ178 ± 2
12
2.0 ± 0.5
φ13 ± 0.5
17.0
Maximum storage No.:
3000 pcs./Reel
Page 28 of 29
RNA50C27A
Preliminary
Mark Indication
RNA50C27AUS
(1)
Year code
(2)
(3)
Month code
Week code
RNA50C27AMM
(1) (2) (3)
R 0
2
N 0 1
(1)
(3)
(2)
The last digit of year
Starting in January "A","B","C","D","E","F","G","H","J","K","L","M"
View Week of month, 1 week  "1"
R03DS0064EJ0100 Rev.1.00
Aug 03, 2012
Page 29 of 29
Notice
1.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2.
Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
3.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
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the product's quality grade, as indicated below.
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equipment; and industrial robots etc.
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Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
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6.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
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Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
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Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
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development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
http://www.renesas.com
SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
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