Download FDT457N N-Channel Enhancement Mode Field Effect Transistor August 1998

August 1998
FDT457N
N-Channel Enhancement Mode Field Effect Transistor
General Description
Features
5 A, 30 V. RDS(ON) = 0.06 Ω @ VGS = 10 V
RDS(ON) = 0.090 Ω @ VGS = 4.5 V.
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance. These products are
well suited to low voltage, low current applications such as
notebook computer power management, battery powered
circuits, and DC motor control.
SuperSOTTM-3
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
SuperSOTTM-8
SuperSOTTM-6
SO-8
D
D
D
D
S
S
D
SOT-223
D
G
G
S
SOT-223*
G
G
S
(J23Z)
Absolute Maximum Ratings
TA = 25oC unless otherwise noted
Symbol
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
ID
Maximum Drain Current - Continuous
PD
Maximum Power Dissipation
(Note 1a)
- Pulsed
TJ,TSTG
SOIC-16
SOT-223
FDT457N
Units
30
V
±20
V
5
A
16
(Note 1a)
3
(Note 1b)
1.3
(Note 1c)
1.1
Operating and Storage Temperature Range
W
-65 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
42
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
12
°C/W
* Order option J23Z for cropped center drain lead.
© 1998 Fairchild Semiconductor Corporation
FDT457N Rev.C
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
30
V
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25 C
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS = 0 V
-100
nA
o
35
TJ =55°C
ON CHARACTERISTICS
o
mV/ C
1
µA
10
µA
100
nA
(Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp.Coefficient
ID = 250 µA, Referenced to 25 oC
1
RDS(ON)
Static Drain-Source On-Resistance
VGS = 10 V, ID = 5 A
TJ =125°C
VGS = 4.5 V, ID = 3.8 A
ID(ON)
On-State Drain Current
VGS = 10 V, VDS = 5 V
gFS
Forward Transconductance
VDS = 10 V, ID = 5 A
1.6
3
V
mV/ oC
-4.2
0.043
0.06
0.065
0.1
0.071
0.09
5
Ω
A
5
S
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
235
pF
145
pF
50
pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
5
10
ns
12
22
ns
tD(off)
tf
Turn - Off Delay Time
12
22
ns
Turn - Off Fall Time
3
8
ns
4.2
5.9
nC
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 10 V, ID = 1 A,
VGS = 10 V, RGEN = 6 Ω
VDS = 10 V, ID = 5 A,
VGS = 5 V
1.3
nC
1.7
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 2.5 A
(Note 2)
0.85
2.5
A
1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is
guaranteed by design while RθCA is determined by the user's board design.
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu.
b. 95oC/W when mounted on a
2
0.066 in pad of 2oz Cu.
c. 110oC/W when mounted on a 0.00123
in2 pad of 2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDT457N Rev.C
Typical Electrical Characteristics
10
R DS(ON), NORMALIZED
I D , DRAIN-SOURCE CURRENT (A)
6
3.5
4
3.0
2
0
0
0.5
1
1.5
2
2.5
DRAIN-SOURCE ON-RESISTANCE
2.5
VGS = 10V 6.0
5.0
8
4.5
4.0
3
VGS =3.5V
2
4.0
4.5
1.5
5.0
6.0
7.0
10
1
0
2
4
VDS , DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
VGS = 10V
1.2
1
0.8
-25
0
25
50
75
100
T , JUNCTION TEMPERATURE (°C)
125
150
RDS(ON), DRAIN-SOURCE ON-RESISTANCE
R DS(ON) , NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
ID = 5 A
0.6
-50
I D = 2A
0.2
0.15
0.1
TA = 125°C
0.05
TA = 25°C
0
2
4
6
8
10
VGS ,GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
Figure 3. On-Resistance Variation
with Temperature.
I S , REVERSE DRAIN CURRENT (A)
10
14
TA = -55°C
VDS = 10V
12
I D , DRAIN CURRENT (A)
10
0.25
J
25°C
10
125°C
8
6
4
2
0
8
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
1.6
1.4
6
I D , DRAIN CURRENT (A)
1
2
3
4
5
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
6
VGS = 0V
1
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
V SD , BODY DIODE FORWARD VOLTAGE (V)
1.2
Figure 6. Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDT457N Rev.C
Typical Electrical Characteristics
1000
I D = 4A
VDS = 5V
10V
15V
8
CAPACITANCE (pF)
V GS , GATE-SOURCE VOLTAGE (V)
10
6
4
400
Ciss
200
Coss
100
50
0
0
2
4
Q
g
6
30
0.1
8
0.1
0.01
0.1
10
30
200
POWER (W)
120
V GS = 10V
SINGLE PULSE
RθJA = 110°C/W
T
A A = 25°C
0.2
0.5
V
80
40
1
DS
SINGLE PULSE
RθJA =110°C
TA = 25°C
160
100
ms
1s
10s
DC
0.5
0.05
3
Figure 8. Capacitance Characteristics.
100
1m µs
s
10m
s
IT
LIM
N)
(O
S
RD
1
2
5
10
20
0
0.001
50
0.01
0.1
1
10
100
300
SINGLE PULSE TIME (SEC)
, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
I D , DRAIN CURRENT (A)
5
1
VDS , DRAIN TO SOURCE VOLTAGE (V)
50
10
0.3
, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics.
20
Crss
f = 1 MHz
VGS = 0 V
2
Figure 10. Single Pulse Maximum Power
Dissipation.
1
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
0.005
R θJA (t) = r(t) * R θJA
R θJA = 110 °C/W
0.1
0.05
P(pk)
0.02
0.01
t1
Single Pulse
0.002
0.001
0.0001
t2
TJ - TA = P * R JA (t)
θ
Duty Cycle, D = t 1/ t 2
0.001
0.01
0.1
1
10
100
300
t1 , TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1c.
Transient thermal response will change depending on the circuit board design.
FDT457N Rev.C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
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DOME™
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E2CMOSTM
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FAST 
FASTr™
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STAR*POWER™
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SuperSOT™-3
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
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As used herein:
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2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4