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Switched Capacitor Circuits for
DC-DC Conversion
Chi Law
Matthew Senesky
Nov. 25, 2003
1
Motivation
• Pro
– No magnetic elements
– Possible IC implementation
• Con
– Control difficult
– Lower power applications
• More info in Bill and Eddie’s talk
2
Switched Cap Basics
• Global assumptions (for this presentation)
– Circuits are made exclusively from caps,
simple switches and sources
– Two phase operation with D=0.5
– Constant frequency
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Fibonacci 5:1 Converter
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Ideal Capacitor Voltages
• No-load analysis
• Goal is to find a consistent set of cap
voltages, determine ideal conversion
ratio, understand operation
• In steady-state, no current flow, so
voltages are constant
• Resistance of switches (transistors) is not
considered in this part of analysis
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Conversion Ratio Analysis
Phase 1:
VC2, VC4: Since VC4 || VC2
in Phase 2, VC4=VC2=Vout
VC3: By looking at Phase 1,
VC3 = VC2 + VC4 = 2Vout
VC1: By looking at Phase 2,
VC1 = VC2 + VC3 = 3Vout
Phase 2:
Vg: By looking at Phase 1,
Vg = VC1 + VC3 =5Vout
Thus conversion ratio is 5:1
Note that we have a
descending order of
Fibonacci number
conversion ratio
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Ideal Currents
• “Piecewise constant” model
• Assume:
– Current source load
– Periodic steady-state operation
– Average power balance at input and output
(100% efficiency)
– Large caps, so approximately constant
voltages
– Must maintain charge balance
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Current Analysis
Phase 1:
Phase 2:
IC1: Assume power
balance between input
and output. Since C1 is
not connected to the
source in Phase 2
IC1 = 2Iin in Phase 1.
IC3: IC3 = IC1 = 2Iin in
Phase 2.
IC2: Apply KCL to Phase
1, IC2 = IC1 + IC3 = 4Iin
IC4: Need It=5Iin. By
KCL on both phases IC4
= Iin
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Output Resistance
• Need to determine output resistance of
circuit to find output voltage and
efficiency
• Case 1: fast switching, only R’s matter
– Currents are piecewise DC
• Case 2: slow switching, only C’s matter
– Currents are impulses, get step V changes
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Fast vs. Slow Switching
vo due to currents
iR
v2
v1
iC
io
vo
Currents
io
10
Fast Switching
vo due to currents
As iR approaches io, output
resistance approaches R
iR
v2
v1
iC
io
vo
Currents
io
11
Slow Switching
vo due to currents
As iC approaches io, output
resistance approaches 0.25T/C
iR
v2
v1
iC
io
vo
Currents
io
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Fibonacci 5:1 Converter
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Fibonacci ROC Analysis
Phase 1:
Assuming the output
impedance is dominated
by capacitors,
CΦ1=((C1+C3)||C2)+C4
CΦ2=((C1||C3)+C2)+C4
Phase 2:
The total capacitance is
the average of the two
phases,
Ct= (CΦ1+CΦ2)/2
ROC = 0.25T/Ct
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Fibonacci ROR Analysis
Phase 1:
Assuming the output
impedance is dominated by
resistors,
ROR_Φ1:
((R1+R2)||R3+R4+R5)||R6
Phase 2:
ROR_Φ2:
((R1+R2+R3)||R4)+R5
The total output impedance
is the average of the two
phases,
ROR = (ROR_Φ1+ROR_Φ2)/2
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Fibonacci Results
• Assume all switch R’s
are equal, all C’s are
equal
• ROC=0.25T/(2.08C)
• ROR=2.2R
• Results for R=1Ω,
C=1μF, ƒsw=5 kHz
(slow), 500kHz (fast)
Simulation
Hand calculation
Slow switching
Fast switching
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Design Strategy
• Optimize ROC and ROR independently for a given
area to find component ratios
• Optimize ROC+ROR for a given area to find ratio of
R to C
• Choose switching frequency where ROR=ROC
Rout
Simulation
Hand calculation
fsw
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