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Transcript
SN74LVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS316B – NOVEMBER 1993 – REVISED MARCH 2005
FEATURES
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 16-bit edge-triggered D-type flip-flop is designed
for 2.7-V to 3.6-V VCC operation.
The SN74LVC16374 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. It can be used as
two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q
outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
P LD RO GGD
EGAKCA
)WEIVTP( O
EO1
1Q1
2Q1
DNG
3Q1
4Q1
V CC
5Q1
6Q1
DNG
7Q1
8Q1
1Q2
2Q2
DNG
3Q2
4Q2
V CC
5Q2
6Q2
DNG
7Q2
8Q2
EO2
1
84
KLC1
2
74 1D1
3
64 2D1
4
54DNG
5
44 3D1
6
34 4D1
7
24
8
14 5D1
9
04 6D1
01
93DNG
11
V CC
83 7D1
21
73 8D1
31
63 1D2
41
53 2D2
51
43DNG
61
33 3D2
71
23 4D2
81
13
91
03 5D2
02
92 6D2
12
82DNG
22
72 7D2
32
62 8D2
42
52
KLC2
V CC
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC are trademarks of Texas Instruments.
www.BDTIC.com/TI
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74LVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS316B – NOVEMBER 1993 – REVISED MARCH 2005
FUNCTION TABLE (EACH FLIP-FLOP)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
LOGIC SYMBOL(1)
1OE
1CLK
2OE
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1EN
C1
1CLK
C1
C2
1D
1D1 47
2
1
3
44
5
43
6
41
8
40
9
38
11
37
12
35
33
48
2EN
46
36
1
2D
13
2
14
16
32
17
30
19
29
20
27
22
26
23
1Q1
1Q1
1Q2
1Q3
1Q4
To Seven Other Channels
1Q5
1Q6
1Q7
2OE
24
1Q8
2Q1
2CLK
25
2Q2
2Q3
C1
2D1
36
1D
2Q4
2Q5
2Q6
2Q7
2Q8
To Seven Other Channels
(1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
2
2
1D
www.BDTIC.com/TI
13
2Q1
SN74LVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS316B – NOVEMBER 1993 – REVISED MARCH 2005
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
VCC + 0.5
range (2) (3)
UNIT
VO
Output voltage
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
VO = 0 to VCC
±50
mA
±100
mA
Continuous current through VCC or GND
Maximum power dissipation at TA = 55°C (in still air) (4)
Tstg
(1)
(2)
(3)
(4)
DGG package
0.85
DL package
Storage temperature range
V
W
1.2
–65
°C
150
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For
more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002B.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
MIN
MAX
2.7
3.6
2
UNIT
V
V
0.8
V
0
VCC
V
0
VCC
V
VCC = 2.7 V
–12
VCC = 3 V
–24
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
0
10
ns/V
TA
Operating free-air temperature
–40
85
°C
(1)
VCC = 2.7 V
12
VCC = 3 V
24
mA
mA
Unused control inputs must be held high or low to prevent them from floating.
www.BDTIC.com/TI
3
SN74LVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS316B – NOVEMBER 1993 – REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC (1)
TEST CONDITIONS
IOH = –100 µA
VOH
MIN to MAX
II
3V
2.4
IOH = –24 mA
3V
2
IOL = 100 µA
MIN to MAX
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
Data inputs
V
0.2
±5
3.6 V
VI = 0.8 V
V
µA
75
3V
VI = 2 V
UNIT
VCC – 0.2
2.2
VI = VCC or GND
II(hold)
TYP (2) MAX
2.7 V
IOH = –12 mA
VOL
MIN
µA
–75
VI = 0 to 3.6 V
3.6 V
±500
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
3.6 V
40
µA
∆ICC
One input at VCC – 0.6 V, Other inputs at VCC or GND
3 V to 3.6 V
500
µA
Ci
VI = VCC or GND
3.3 V
3.5
pF
Co
VO = VCC or GND
3.3 V
7
pF
(1)
(2)
IO = 0
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
100
0
80
fclock
Clock frequency
0
tw
Pulse duration, CLK high or low
4
4
MHz
ns
tsu
Setup time, data before CLK↑
High or low
2
3
ns
th
Hold time, data after CLK↑
High or low
1.5
1.5
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
fmax
VCC = 3.3 V
± 0.3 V
MIN
VCC = 2.7 V
MAX
100
MIN
UNIT
MAX
80
MHz
tpd
CLK
Q
1.5
7.5
1.5
8.5
ns
ten
OE
Q
1.5
7.5
1.5
8.5
ns
tdis
OE
Q
1.5
7
1.5
8
ns
Operating Characteristics
VCC = 3.3 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance per flip-flop
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 50 pF, f = 10 MHz
www.BDTIC.com/TI
TYP
22
9
UNIT
pF
SN74LVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS316B – NOVEMBER 1993 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V6
tuptuO morF
T rednU
Ω
005
1S
TSET
nepO
tse
DNG
Fp C05L =
)A etoN ees(
005
1S
tpd
tP LZt/ P ZL
tPH Zt/ P ZH
Ω
nepO
V6
DNG
V 7.2
STUPTUO ROF TIUCRIC DAOL
V 5.1
tupnI gniT
mi
V0
tw
tsu
V 7.2
tupnI
V 5.1
V 5.1
th
V 7.2
V 5.1
tupnI ataD
V 5.1
V0
LOW
V EGTSAMROFA
EV
ARUD ESLUP
NOIT
LOW
V EGTSAMROFA
EV
SEMIT DLOH DNA PUTES
V 7.2
tupnI
V 5.1
V0
V 5.1
V0
tPH L
tP LH
V 7.2
tuptuO
lortnoC
V 5.1
V 5.1
V0
tP ZL
tuptuO
1 mrofW
eva
V
6
t
a 1S
VO L
)B etoN ees(
tP LZ
V3
VO H
V 5.1
tuptuO
V 5.1
tPH L
V 5.1
LOW
V EGTSAMROFA
EV
PORPALAEGDANOIT SEMIT Y
tuptuO
VO H
2 mrofW
eva
DNG ta 1S
VO)LB etoN ees(
VO L
tPH Z
VV
3.O0H−
V 5.1
VO H
V 0
LOW
V EGTSAMROFA
EV
SEMIT ELBASID DNA ELBANE
GNILBANE LEVEL-HG
WIH
OLDNA -
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naticap:aScEgTijOdN
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oc lanretni htiw tuptuo na rof 2si
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eno derusaem era stuptu.D
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nZaas ehtPeHrZa
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edm
nLaas ehtPeZH
ra
Z
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nHaas ehtPeHrLa
V3
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tP ZH
tP LH
V 5.1
tuptuO
V 5.1
W .lortnoc tuptuo eht yb delbasid nehw tpecxe ,
Z ,zHM ≤01
mrofeva
05O=
t
,stn, 5r.≤2
.sn f5
≤.2
d si .
en .
pd .
Figure 1. Load Circuit and Voltage Waveforms
www.BDTIC.com/TI
5
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