Download PS12013-A

MITSUBISHI
MITSUBISHI
SEMICONDUCTOR
SEMICONDUCTOR
<Application
<Application
Specific
Specific
Intelligent
Intelligent
Power
Power
Module>
Module>
PS12013-A
PS12013-A
FLAT-BASE
FLAT-BASE
TYPE
TYPE
INSULATED
INSULATED
TYPE
TYPE
PS12013-A
INTEGRATED FUNCTIONS AND FEATURES
• 3-Phase IGBT inverter bridge configured by the latest 3rd.
generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability Io (Note 1) :
Type Name
PS12013-A
100% load
1.8A (rms)
150% over load
2.7A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the
above loading cases is defined as : Iop = Io ✕ √2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs : Drive circuit, High-speed photo-couplers, Short circuit protection (SC),
Bootstrap circuit supply scheme (Single drive power supply ) and Under-voltage protection (UV).
• For N-Side IGBTs : Drive circuit, Short-circuit protection (SC), Control supply Under voltage and Over voltage protection (OV/UV),
System Over temperature protection (OT), Fault output signaling circuit (Fo), and Current-Limit warning signal output (CL).
• For Brake circuit IGBT : Drive circuit.
• Warning and Fault signaling :
FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through.
FO2 : N-side control supply abnormality locking (OV/UV)
FO3 : System over-temperature protection (OT).
CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase current (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
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APPLICATION
Acoustic noise-less 0.4kW/AC400V Class 3 Phase inverter and other motor control applications.
PACKAGE OUTLINES
80.5 ± 1
71.5 ± 0.5
4-φ4
20.4 ± 1
0.5
23
2 ± 0.3
0.5
1
6 ± 0.3
56 ± 0.8
(7.75)
78.75
92.5 ± 1
83.5 ± 0.5
5
2.5
1.2
31
(10.35)
0.6
2.45 ± 0.3
76.5 ± 1
32 33 34
10.16 ± 0.3
50.8 ± 0.8
35
36
4-R4
8.5
13
27 ± 1
Terminals Assignment:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CBU+
CBU–
CBV+
CBV–
CBW+
CBW–
GND
VDL
VDH
CL
FO1
FO2
FO3
CU
CV
CW
UP
VP
WP
UN
VN
WN
Br
31
32
33
34
35
36
P
B
N
U
V
W
LABEL
(Fig. 1)
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
Protection
Circuit
CBW+
CBW–
CBV+
CBV–
Application Specific Intelligent
Power Module
CBU+
INTERNAL FUNCTIONS BLOCK DIAGRAM
CBU–
FLAT-BASE TYPE
INSULATED TYPE
Input Circuit
Drive Circuit
P
Brake resistor connection,
Inrush prevention circuit,
etc.
Photo
Coupler
AC 400V class line input
B
R
U
V
W
S
T
Z
M
AC 400V class
line output
C
T
S
N
Z : Surge absorber.
C : AC filter (Ceramic condenser 2.2~6.5nF)
[Note : Additionally an appropriate Line-to line
surge absorber circuit may become necessary
depending on the application environment].
Current sensing
circuit
Drive Circuit
Input signal conditioning
CU CV CW
UP VP WP UN VN WN Br
Fo Logic
Protection
circuit
Control supply
fault sense
CL,FO1,FO2,FO3
GND
VDL VDH
Analogue signal output corresponding to
PWM input
Fault output
each phase current (5V line) Note 1) (5V line) Note 2)
(5V line) Note 3)
Note 1) To prevent chances of signal oscillation, a series resistor (1kΩ) coupling at each output is recommended.
Note 2) By virtue of integrating a photo-coupler inside the module, direct coupling to CPU, without any extemal opto or transformer isolation is possible.
Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance.
Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage.
For extra precaution, a small film snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins.
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(Fig. 2)
MAXIMUM RATINGS (Tj = 25°C)
INVERTER PART (Including Brake Part)
Symbol
VCC
VCC(surge)
VP or VN
VP(S) or
VN(S)
±Ic(±Icp)
Ic(Icp)
IF(IFP)
Condition
Item
Applied between P-N
Supply voltage
Applied between P-N, Surge-value
Supply voltage (surge)
Each output IGBT collector-emitter static voltage Applied between P-U, V, W, Br or U, V, W, Br-N
Ratings
Unit
900
V
1000
1200
V
V
1200
V
±5 (±10)
5 (10)
5 (10)
A
A
A
Condition
Applied between VDH-GND, CBU+-CBU–,
CBV+-CBV–, CBW+-CBW–
Applied between VDL-GND
Ratings
Unit
20
V
7
V
Applied between UP · VP · WP · UN · VN ·
WN · Br-GND
Applied between FO1 · FO2 · FO3-GND
Sink current of FO1 · FO2 · FO3
Applied between CL-GND
Sink current of CL
–0.5 ~ VDL+0.5
V
–0.5 ~ 7
15
–0.5 ~ 7
15
V
mA
Each output IGBT collector-emitter surge voltage Applied between P-U, V, W, Br or U, V, W, Br-N
Each output IGBT collector current
Brake IGBT collector current
TC = 25°C
Brake diode anode current
Note : “(
)” means IC peak value
CONTROL PART
Symbol
Item
VDH, VDB
Supply voltage
VDL
Supply voltage
VCIN
Input signal voltage
VFO
IFO
VCL
ICL
Fault output supply voltage
Fault output current
ICO
Current-limit warning output voltage
CL output current
Analogue-current-signal output current
Sink current of CU · CV · CW
±1
V
mA
mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
FLAT-BASE TYPE
INSULATED TYPE
TOTAL SYSTEM
Symbol
Tj
Tstg
TC
VISO
Condition
Item
Junction temperature
(Note 2)
—
Storage temperature
Module case operating temperature
Isolation voltage
(Fig. 3)
Ratings
Unit
–20 ~ +125
–40 ~ +125
–20 ~ +100
°C
°C
°C
2500
Vrms
60 Hz sinusoidal AC for 1 minute, between all terminals
and base plate.
—
Mounting screw: M3.5
Mounting torque
0.78 ~ 1.27
N·m
Note 2) : The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation.
However, these power elements can endure instantaneous junction temperature as high as 150°C. To make use of this additional
temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is
to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
TC
(Fig. 3)
THERMAL RESISTANCE
Symbol
Item
Condition
Ratings
Min.
—
—
—
—
—
Typ.
—
—
—
—
—
Max.
3.0
7.3
3.0
7.3
0.040
Unit
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Rth(jc)Q
Rth(jc)F
Rth(jc)QB
Junction to case Thermal
Resistance
Rth(jc)FB
Rth(c-f)
Contact Thermal Resistance
Inverter IGBT (1/6)
Inverter FWDi (1/6)
Brake IGBT
Brake FWDi
Case to fin, thermal grease applied (1 Module)
°C/W
°C/W
°C/W
°C/W
°C/W
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V , VDB = 15V, VDL = 5V unless otherwise noted)
Symbol
VCE(sat)
VEC
VCE(sat)Br
VFBr
ton
tc(on)
toff
tc(off)
trr
Item
Collector-emitter saturation
voltage
FWDi forward voltage
Brake IGBT
Collector-emitter saturation voltage
Brake diode forward voltage
Switching times
FWD reverse recovery time
Condition
IDL
Vth(on)
Vth(off)
Ri
VDH Circuit Current
VDL Circuit Current
Input on threshold voltage
Input off threshold voltage
Input pull-up resistor
Unit
Typ.
Max.
VDL = 5V, VDH = VDB = 15V Input = ON,
Tj = 25°C, Ic = 5A
—
—
3.6
V
Tj = 25°C, Ic = –5A, Input = OFF
—
—
3.5
V
VDL = 5V, VDH = 15V Input = ON, Tj = 25°C, Ic = 5A
—
—
3.6
V
Tj = 25°C, IF = 5A, Input = OFF
—
1/2 Bridge inductive, Input = ON
VCC = 600V, Ic = 5A, Tj = 125°C
VDL = 5V, VDH = 15V, VDB = 15V
Note : ton, toff include delay time of the internal control
circuit.
0.3
—
—
—
—
—
1.2
3.5
2.0
V
µs
0.5
2.2
0.9
1.4
4.0
1.6
µs
µs
µs
0.2
—
µs
VCC ≤ 800V, Input = ON (One-Shot)
Short circuit endurance
(Output, Arm, and Load, Short Tj = 125°C start
Circuit Modes)
13.5V ≤ VDH = VDB = ≤ 16.5V
VCC ≤ 800V, Tj ≤ 125°C,
Switching SOA
Ic < IOL(CL) operation level, Input = ON,
IDH
Ratings
Min.
13.5V ≤ VDH = VDB = ≤ 16.5V
VDL = 5V, VDH = 15V, VCIN = 5V
VDL = 5V, VDH = 15V, VCIN = 5V
Integrated between input terminal-VDH
• No destruction
• FO output by protection operation
• No destruction
• No protecting operation
• No FO output
—
—
150
—
—
50
0.8
1.4
2.0
2.5
3.0
4.0
—
—
150
mA
mA
V
V
kΩ
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
FLAT-BASE TYPE
INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, V DB = 15V, V DL = 5V unless otherwise noted)
Symbol
fPWM
txx
tdead
Max.
2
Ratings
Typ.
—
15
kHz
2
—
500
µs
4.0
—
—
µs
—
1.87
65
2.27
100
2.57
ns
0.77
2.97
1.17
3.37
1.47
3.67
—
15
—
—
4.0
—
—
0.7
—
|VCO-VC±(200%)|
—
1.1
—
V
Correspond to max. 500µs data hold period only,
(Fig. 5)
Ic = IOP(200%)
–5
—
5
%
After input signal trigger point
—
3
—
µs
—
—
—
1
1
—
µA
mA
4.84
5.85
7.38
A
8.2
100
—
14.4
110
90
20.9
120
—
A
°C
10.0
10.5
11.05
11.55
11.0
11.5
12.00
12.50
12.0
12.5
12.75
18.00
16.50
—
—
19.20
17.50
10
—
—
1
Item
Condition
PWM input frequency
Allowable input on-pulse width
TC ≤ 100°C, Tj ≤ 125°C
Note 3)
VDH = 15V, VDL = 5V, T C = –20°C ~ +100°C
Relates to corresponding inputs (Except brake part)
TC = –20°C ~ +100°C
Relates to corresponding inputs (Except brake part)
Ic = 0A
VDH = 15V
Ic = IOP(200%)
Ic = –IOP(200%)
Allowable input signal dead time
for blocking arm shoot-through
Min.
t int
VCO
Input inter-lock sensing
VC+(200%)
VC–(200%)
Analogue signal linearity with
output current
|∆V CO|
Offset change area vs temperature VDH = 15V, VDL = 5V, TC = –20 ~ 100°C
VC+
VC–
Analogue signal output voltage limit
Analogue signal overall linear
∆VC (200%)
variation
Analogue signal data hold
rCH
accuracy
td(read)
ICL(H)
ICL(L)
Analogue signal reading time
Signal output current of CL operation
Idle
Active
±IOL
CL warning operation level
SC
Short circuit current trip level
OT
OTr
UVDB
Over tenperature
protection
Trip level
Reset level
Trip level
VDL = 5V
TC = –20 ~ 100°C
(Fig.4)
Ic > IOP(200%), VDH = 15V,
VDL = 5V
(Fig. 4)
(Fig. 8)
Open collector onput
VDL = 5V, VDH = 15V, TC = –20 ~ 100°C
(Note 4)
(Fig. 7), (Note 5)
Tj = 25°C
VDL = 5V, VDH = 15V
Unit
V
V
V
mV
V
V
°C
V
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UVDBr
UVDH
UVDHr
OVDH
OVDHr
tdv
IFO(H)
IFO(L)
Supply circuit
under and
over voltage
protection
Reset level
Trip level
Reset level
Trip level
TC = –20°C ~ +100°C
Tj ≤ 125°C
Reset level
Filter time
Fault output current
Idle
Active
Open collector output
13.25
20.15
18.65
—
1
—
V
V
V
V
V
µs
µA
mA
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F O1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol
VCC
Item
Supply voltage
Condition
VDH , VDB
Control supply voltage
Applied between P-N
Applied between VDH -GND, CBU+-CBU– , CBV+-CBV–,
CBW+-CBW–
VDL
Control supply voltage
Applied between VDL -GND
∆VDH, ∆VDB ,
Supply voltage ripple
∆VDL
VCIN(on)
Input ON voltage
VCIN(off)
Input OFF voltage
fPWM
tdead
PWM Input frequency
Arm shoot-through blocking time
Using application circuit
Using application circuit
Ratings
Max.
800
Unit
Min.
—
Typ.
600
13.5
15.0
16.5
V
4.8
5.0
5.2
V
–1
—
+1
V/µs
—
4.8
—
—
0.3
—
V
V
2
4.0
10
—
15
—
kHz
µs
V
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
5
VC
VC–
4 min
VDH=15V
VDL=5V
TC= –20~100˚C
max
500µs
VC–(200%)
3
0V
VCH(5µs)
VC(V)
VC0
2
rCH=
VC+(200%)
VCH(505µs)
VCH(505µs)-VCH(5µs)
VCH(5µs)
1
Analogue output signal
data hold range
0
–400 –300 –200 –100
0
VC+
100 200 300 400
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
Real load current peak value.(%)(Ic=Io✕ 2)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm
0V
Input signal VCIN(n) of each phase lower arm
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0V
Gate signal Vo(p) of each phase upper arm
(ASIPM internal)
0V
Gate signal Vo(n) of each phase upper arm
(ASIPM internal)
0V
Error output FO1
0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O” signal is outputted. After an “input
interlock” operation the circuit is latched. The “FO” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase
upper arm
0V
Short circuit sensing signal VS
0V
Gate signal Vo of each phase
upper arm(ASIPM internal)
Error output FO1
SC delay time
0V
0V
Note : Shor t circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
Jan. 2000
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS12013-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
N-side IGBT Current
N-side FWDi Current
off
VCIN
on
on
V(hold)
off
IC
0
+ICL
(VS)
0
–ICL
t(hold)
VC
Ref
0
off
VCL
on
Delay time
td(read)
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Fig. 9 START-UP SEQUENCE
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
Normally at start-up, Fo and CL output signals will be pulled-up
High to VDL voltage (OFF level); however, FO1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. FO1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
VDL(5V)
5.1kΩ
ASIPM
R
UP,VP,WP,UN,VN,WN,Br
DC-Bus voltage
Control voltage supply
Boot-strap voltage
VPN 0
PWM starts
a)
VDH, DL 0
VDB
R
FO1,FO2,FO3,CL
CPU
10kΩ
CU,CV,CW
0
N-Side input signal
VCIN(N)
P-Side input signal
VCIN(P) on
Brake input signal
VCIN(Br) on
FO1 output signal
FOI
on
b)
0.1nF
0.1nF
GND(Logic)
on
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 depending on the boot-strap capacitor size)
b) FO1 resetting sequence:
Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order.
Jan. 2000