Download Programming the NUN Procedure Using the Negative Binomial Yield Model for ASIC Semiconductors

Programming the NUN Procedure Using the
Negative Binomial Yield Model for ASIC Semiconductors
Jon A. Patrick
IBM Microelectronics Division, Essex Junction, VT 05452
Abstract
Tbis presentation will sbow bow easily tbe negative
binomial yield model is programmed using tbe
SAS® NLIN procedure, and describe tbe cbaracteristics of tbe output parameters: alpba - tbe cluster
parameter, lambda - tbe average fault density, and
y. - tbe gross yield. Tbe predicted output will be
overlaid witb tbe actual data and plotted witb
SAS/G RAPH®. Tbe benefits to tbis metbod of
cbaracterization are:
sistors per die, but tbis is bard to obtain for each
ASIC. In general, the industry assumes fully populated ASICs, therefore, tbis analysis models yield
based on die area in sq mm.
Negative Binomial Yield Model
Tbe negative binomial model takes tbe form of
Maverick product is easily identified.
[ 1]
Yield projections on new, larger size die can
be easily determined.
Introduction
Tbe SAS NLIN (NonLiNear regression) procedure
is a very useful tool for analyzing wafer final test
yield of application specific integrated circuit
(ASIC) semiconductors. Tbe IBM Microelectronics Division fabricators in Essex Junction,
Vermont, manufacture a wide range of OEM and
internal ASICs with different chip or die areas.
Tbe overall area of a die is mostly a function of
bow many lIOs are necessary to perform the
ASIC's particular function and is not always tbe
most descrete variable to model. A finer measurement would be tbe number oflogic circuits or tran-
Yield
= Yo x
"-
[1
+ a]
-ct
.
The model is used throughout IBM to project
semiconductor yields and bas been written about
extensively by Dr. C. H. Stapper. 1.2 Before
looking at tbe results of the model, tbe parameters
must be brielly described. Y. is tbe y intercept or
the maximum yield your fab is producing at the
time your data are analyzed. It's effect is to lower
the predicted yield, and is referred to as a gross
yield parameter. One way to determine y., on a
mature process line, is by plotting the mean die
yield across 15-20 batcbes of a particular ASIC as a
function of the distance from tbe edge of the wafer
(Figure 1). Each point on the plot is a single die
averaged across all wafers in the sample and Yo is
the ratio of the overall yield across tbe entire
® SAS and SAS/G RAPH is a registered trademark of SAS Institute Inc., in the USA and other countries.
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sample divided by tbe bigher yield of die greater
tben 6-7mm from tbe wafer's edge. Tbis edge loss
is usually related to extra bandling damage,
increased tbickness of spun-on materials such as
resist or polyimide, or loss of parametric control
across 100% oftbe wafer. Typical values for Yo on
a mature process line range between .94 -to- 1.0,
wbicb are good starting values for Yo wben beginning the NUN procedure. .
0
i
e
••
II ....
y
i
•
YO = .97
Die Size = 88,4 sq mm
II
II
e
.. •••• if
I
d
o
5
10 15 20 25 30 35 40 45 50
OIlIIance FrDm _
.. EdGe (mm)
Figure 1. Plot of die yield as a function of distance to
edge of water (mm)
Lambda, tbe average fault density per die, is
expressed as
[2]
mm 2
faults
A.= Na(-d' )x"-a(--2-)'
Ie
mm
where N. is die area in sq mm and It. is the average
number of faults per sq mm. The NUN procedure
is coded using tbe expression N. x A.. so the units
of the parameter estimate, It., are in faults per sq
mm. If you have available the number of circuits
per die this can be substituted for N .. whicb
cbanges tbe units of lambda to faults per circuit.
Good starting values for lambda range between
.001 -to- .010 faults per sq mm.
The term "alpba" is considered a defect cluster
parameter or a measure of how defects tend to con-
centrate in close proximity of one anotber. Tbe
higher tbe alpha tbe more random the defect distribution across a wafer and tbe lower the wafer
yield. Low values of alpba indicate higb clustering
and higher yield since multiple defects will destroy
the same die. Good starting values for alpha range
between .2 -to- 2.5, with the typical value for alpba
being 2.0. When modeling yields in the bigb 80's
and low 90's, expect a lower value for alpha.
Wben projecting yields on larger area die be slightly
conservative and restrict alpha's range with the
BOUNDS statement to a value close to 2.0. This
effect will lower the predicted yield on the large
area die your fabricator plans to build.
Getting Started
The input data to the model are yield and area,
wbile tbe results or parameter estimates are )10,
lambda and alpba, wbich provide the best fit to the
data. The SAS NLIN procedure has five different
techniques for initiating the analysis. Tbe DUD
metbod is tbe easiest to program because no derivatives are necessary. Tbemodified Gauss-Newton
method requires derivatives for eacb of the variables, whicb are provided in the code following tbis
text. As witb any regression analysis, the first step
is to look at tbe data. Critical data are individual
batch yields and sample size witbin each batch.
Concentrate on fixing problems that are systematic
across all batches of a particular ASIC. Don't
include yield results for a poorly processed batch if
the mode of tbe yield distribution for tbat ASIC is
significantly bigber. Data should be screened to the
latest six montbs of process bistory. When ready
to average data across an ASIC, reflect the weight a
particular batcb has on tbe overall mean by the
number of wafers within each batcb or, simply, the
total number of good die divided by the total
number of die tested for each ASIC. By using
PROC MEANS; BY ASIC; tbe result gives equal
weight per batch, regardless if one batch bas 48
wafers and tbe otber only 8 wafers. Another way
to give equal weigbt per batcb is using tbe FREQ
X statement witbin PROC MEANS, were X
equals the number of wafers per batch.
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Output
The most important part of the NLiN output is
whether or not convergence was met. If NLiN fails
to converge, the asymptotic standard error is set to
zero and the upper and lower 95% confidence
intervals are equal, resulting in unreliable parameter
estimates. If convergence is not met, expand the
starting values in the PARM S statement; however,
avoid using too small a increment in the grid of
starting values because the job may exceed the time
allotted trying to converge. Tbe BOUNDS statement should also be used to prevent the possibility
of alpha becoming negative. Tbe output dataset
contains ybat - tbe predicted yield, yresid- the residual yield, and tbe parameter estimates, Yo, lambda,
and alpba. Always output the residuals and review
them, as one or two observations witb high positive
residuals may have been coded with the wrong die
area. The parameter estimates are placed into
macro variables so they can be printed in the title
of the grapb. This helps keep track of parameter
estimates after changes have been made. ASIC's
with high negative residuals should be the focus of
your analysis. This is the case in Fignre 2, where
the maverick ASIC clearly stands out from other
ASICs of tbe same die size. Figure 3 shows the
same data, only the mean yield across all ASICs of
the same die size are plotted. This results in more
accurate parameter estimates because tbe
asymptotic 95% confidence intervals are tighter and
the error associated with each lower.
(Idd) is the flfst step. Previous analysis found that
a particular maverick ASIC bad 20-25% of tbe die
failing Idd (and only Idd) wbile passing all other
logic pattern tests. The background level of these
fails was 4-9% , depending on die size. This failure
analysis information was used to start a major
process change at polysilicon which reduced our
across-cbip line variation (ACLV) by 3x, thereby
virtually eliminating all but I % of Idd-only loss.
A
8
i
c
Parameter Estimates
YO-O.95
Alpha-l.ll
Lambda=O.0021
y
i
e
I
d
Die Size (sq mm)
Figure 2. Plot of actual ASIC yield as a function of die
size
A
s
i
c
Parameter Estimates
YO-O.98
Alpha-O.73
Lambda=O.0029
y
I
e
I
Conclusion
The SAS NLiN procedure is a useful tool in semiconductor yield analysis. Results can be plotted
and maverick ASICs can be easily identified, which
helps define and focus work on low yield product.
Dissecting the test yield into individual components, especially, the total static leakage current
d
Die Size (sq mm)
Figure 3. Plot of average ASIC yield as a function of
die size
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References
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PIt((
1. C. H. Stapper, ''Modeling ofIntegrated Circuit
Defect Sensitivities," IBM Journal of Research
and Development. November 1983, Volume
27, Number 6.
on ~ W{I.O/en·O + (IIEA"I../Al.PW\)-ALPHA):
arr-a P-YIKT R-'I'RfSlD PMIS-AU'tI' YO l:
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2. C. H. Stapper, J. A. Patrick, R. J. Rosner
"Y ield Model for ASIC and Processor Chips,"
"International Workshop on pefect and Fault
Tolerance in VLSI Systems." October, 1993
The author may be contacted on Internet:
JON][email protected]
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