Survey
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project
* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project
Analog Multi-Tone Signaling for High-Speed g p Backplane p Electrical Links A. Amirkhany1, A. Abbasfar2, V. Stojanovic3, and M. Horowitz1,2 1Stanford St f d University U i it 2Rambus 3Massachusetts Inc Institute of Technology High-Speed g p Link 0 Frequency Response 3" TOP dB -20 20 -40 -60 60 3" BUTTOM -80 20" TOP -100 0 5 10 GHz 15 20 • Multi Gb/sec chip chip-to-chip to chip communication over PCB traces traces. • Routers, XAUI, PCI express 7/2/2008 Slide 2 Channel State of the Art Links Rx W1 W2 W3 W4 Line Driver T Tx Wb1 Wb2 Wbk • Baseband 2PAM or 4PAM • 4-5 tap discrete linear transmit equalizer p (predictive (p or partial p response) p ) DFE • 5-20 tap • Designed for BER of 10-15 • No error detection/correction coding 7/2/2008 Slide 3 dB Potential ote t a o of Multi-Tone ut o e S21 (dB) • Better power allocation over channels with a notch f (GHz) • Parallelized data stream in frequency leading to implementation advantages 7/2/2008 Slide 4 Design g Considerations • Power efficiency is the main constraint • Cannot afford high-resolution ADC • Limits signal processing • Rules out DMT techniques • A customized MT architecture is required i d • Few sub-channels can create close to optimum transmit spectrum 7/2/2008 Slide 5 dB Analog g Multi-Tone ((AMT)) • A bank of parallel links on different carrier frequencies • Sub-channels not independent • Inter-channel I t h l interference i t f (ICI) exists 7/2/2008 Slide 6 C Conceptual t l Practical Architecture • N-times over-sampled equalizers per sub-channel • Tx power equal to a BB covering same BW • Receive filters are integrators • MIMO DFE in the receiver • DFE power equal to a BB covering same BW 7/2/2008 Slide 7 Analysis a ys s Framework a e o (Co (Convex e - SOC SOCP)) • Find Tx equalizer and Rx DFE taps that • Minimize transmit voltage (power) • Meet BER constraint per sub-channel ( 2 1− 2 −bk )Q( 0.5d mink − offsetk σ noise ) ≤ Pe • offsetk: Receiver sampler dead-band (fixed) • dmin: Minimum distance at Rx (linear) • σnoise: Sigma residual interf. and thermal (norm-2) SOCP: Minimize VPeak (Tx Peak Voltage) Subject to : BERk < Pe VTxi _ Max < VPeak 7/2/2008 Slide 8 for k = 1, 2, ..., N for i = 1, 2, ..., N ZFE with BER Constrained Power Allocation • Step 1: Independent sub-channel tap optimization ti i ti (ZFE) • Minimize interference power from one transmitter to all receivers (find WTx,k and WFB,km) • Independent of sub-channel transmitter power 7/2/2008 Slide 9 ZFE with BER Constrained Power Allocation • Step 2: Joint power allocation (BER constrained) • Assume Tx voltage of gk for each sub-channel • Model interference as peak distortion • BER constraint per sub-channel is linear in gk • SOCP reduces to an LP in vector g Minimize VPeak (Tx Peak Voltage) Subject to : Bg > b ( BER Const) Ag < VPeak 1 (Peak Voltage Const) 7/2/2008 Slide 10 • A,B fixed since taps are fixed • Solution is g = B-1b Closed From Jitter Modeling g Tx Jitter xN-1 W(N-1) CN-1 N1 (n) y Rx Jitter s=[1 -1] h x1 W1 C1 x0 W0 C0 rN-1 r1 r0 Variance at kth Rx output σ N −1 2 TX _ jitterk 7/2/2008 = ∑ w S ( H H k • R Φ )Sw m σ m =0 Slide 11 T m T T k 2 RX _ jitterk ⎛ N −1 T T T ⎞ = σ φk ⎜ ∑ w m S H k H k Sw m ⎟ ⎝ m =0 ⎠ 2 Performance on a Channel with Notch Sub-channel Response at Rx Output Equalized Frequency Response CHANNEL -20 4PAM 2PAM MT-2nd MT-3rd dB B -40 MT-1st MT: 12Gbps 4PAM: 5Gbps 2PAM: 2.5Gbps -60 -80 -100 100 7/2/2008 Slide 12 2 4 Frequency (GHz) 6 Performance on a Smooth Channel Frequency Response 0 Peak k Voltage (V V) 2 PAM 5.0mV Deadband dB -20 -40 FR4 -60 -80 0 2 4 6 Frequency (GHz) 8 10 10 0 4 PAM 5.0mV 5 0mV Deadband AMT (4P,2P,2P) 2.5mV Deadband 10 -1 6 8 10 12 Data Rate (Gbps) 14 • Comparable hardware complexity • For same VPeak (transmit voltage) • AMT can achieve higher rates • Needs N d better b tt Rx R precision i i att lower l rates t • Possible since AMT samplers operate at half BB (4PAM) rate 7/2/2008 Slide 13 Conclusion • Power efficiency in links requires customized MT architectures • The AMT architecture has comparable y with BB complexity • AMT has as c clear ea ad advantage a tage o over e c channels a e s with t a notch • Comparable performance over smooth channels 7/2/2008 Slide 14