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TuC3 (Oral)
14:15 – 14:30
Integrated Microring Tuning in Deep-Trench Bulk CMOS
Chen Sun, Erman Timurdogan, Michael R. Watts, Vladimir Stojanović
Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA 02139, USA
{sunchen, ermant, mwatts, vlada}@mit.edu
Abstract: An all-digital Δ∑-based heater driver and a 6-μm diameter microring resonator are monolithicallyintegrated in deep-trench bulk CMOS. With clock scaling and 2.5V supply voltage, the system demonstrates
a 350GHz tuning range and 10-15μW/GHz tuning efficiencies.
1. Introduction
Wavelength-division multiplexed (WDM) silicon-photonic links form a promising alternative to tradional electrical
interconnects. However, the essential component of these WDM networks, the microring resonator, suffers from
resonance drifts due to either static process variations or dynamic temperature fluctuations, necessitating methods
for active resonance tuning [1]. Thermooptic tuning can be accomplished through over-clad heaters [4,7,8] or silicon
heaters directly integrated into adiabatic resonator microrings (ARM) [1,3,5,6]. Unfortunately, thermal tuning can
consume a significant portion of the overall link power budget [2], motivating device and system design to
characterize and improve thermal tuning efficiency. To date, this concept has been demonstrated and characterized
for devices built on thick SOI with and without localized substrate removal (undercut) [3-5], in thin SOI with
silicon-carbide substrate transfer [7], and in bulk CMOS with localized substrate removal under shallow-trench
isolation (STI) [8].
In this work, we demonstrate a heater driver system for microring resonators consisting of a fully-digital Δ∑based heater driver circuit and an ARM filter (Fig. 1, left), both monolithically integrated in a commercial 0.25 µmequivalent bulk CMOS process with deep-trench isolation capability. Integration of the heater driver alongside the
integrated heater minimizes the parasitic resistance from driver to the heater, provides a digital heater control
interface through which multiple rings can be controlled on-chip, and eliminates the dedicated pads for external
heater control used in the majority of previous work. Using a process-compatible supply voltage of 2.5V, the system
is able to tune the resonance of an ARM filter by 350GHz, with an efficiency of 10-15µW/GHz.
2. System Overview
The driver circuit consists of a synthesized pipelined accumulator and a custom one-transistor driver head (Fig. 2,
right). The circuit utilizes pulse density modulation (PDM) to output a heater drive waveform consisting of a digital
pulse train, with a duty-cycle corresponding to an 8-bit digital input setting. The slow thermal response of the ring
heater smoothens ripples in temperature and transmission introduced by the digital nature of the drive waveform,
provided that the driver’s clock frequency (and hence the PDM’s oversampling ratio) is set significantly higher than
the thermal time constant. Since power consumption of the circuit scales with the clock frequency, driver power can
be optimized by fine-tuning the oversampling ratio of the PDM. The duty-cycled nature of the driver guarantees a
monotonic and linear relationship between heater power and input setting, as well as constant step size. The
implementation in this work is aggressively pipelined to hit frequency targets >400MHz and sized to drive >5mA of
current. Design constraints can be relaxed to lower driver power and area.
Figure 1 – Layout of the integrated heater driver connected to the ARM filter, both integrated in a deep trench CMOS process (left). Block
diagram of the Δ∑-based heater driver with SEM of the connected ARM filter (right). The ARM filter, 8-bit accumulator, and driver head
occupy 28μm2, 1500um2, and 2500 um2 of area, respectively, including area used for decoupling capacitances and fill cells.
978-1-4673-5063-1/13/$31.00 ©2013 IEEE
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Total Power (mW)
4.0
3.0
2.0
1.0
500 kHz
100 MHz
20 MHz
200 MHz
0.0
0
50
100
150
200
8-bit Heater Driver Strength Setting
250
Figure 2 – Optical transmission vs. wavelength when driver is off and at max power (left) and total power consumed at various driver power
settings (right). For reference, off corresponds to a driver strength setting of 0, max corresponds to a strength setting of 255.
Tuning Cost [µW/GHz]
The ring and circuit are integrated in a deep-trench bulk CMOS process (equivalent to a DRAM periphery process),
with Poly-Si waveguides above deep oxide trenches (Fig. 1, left). The 6-μm diameter ARM filter [6] is designed to
work at a wavelength of λ~1290nm with a deep-trench. The single-mode waveguide width is 280nm in the coupling
region and adiabatically tapered to 600nm to allow contacts to the adiabatic region. Single radial mode propogation
is preserved through the adiabatic region, achieving an uncorrupted free spectral range (FSR) of 3.7THz (Fig. 2, left).
The integrated heater with a resistance of ~1.7kΩ is formed by n type doping in the adiabatic region and the Sitethers are doped n+ with silicide to minimize contact resistance and to insulate the tethers (Fig. 1, right-inset).
60.0
50.0
40.0
500 kHz
20 MHz
100 MHz
200 MHz
Process
Bulk deep trench
(this work)
30.0
20.0
Raw Cost
FSR
Normalized
10 µW/GHz
3.7 THz
37.0mW/2π
Thick SOI [3]
42.2 µW/GHz
1.6 THz
67.4mW/2π
Thick SOI with
undercut [4]
1.67 µW/GHz
1.4 THz
2.34mW/2π
Thick SOI [5]
10.0
0.0
0
50
100
150
200
250
300
350
Tuning Offset (GHz)
Figure 3 – Tuning cost per gigahertz, with driver cost included, to reach a
specific tuning offset
Thin SOI with
substrate transfer [7]
Bulk shallow-trench
with undercut [8]
4.4 µW/GHz
5.6 THz
24.6mW/2π
14.3 µW/GHz
2.04 THz
29.2mW/2π
2.9 µW/GHz
4.0 THz
11.6mW/2π
Table 1 – Comparison of the tuning costs between this work at 20
MHz in the high power regime and other works. The normalized
cost is calculated as (Raw Cost) × (FSR/2π).
3. Measurement Results
The heater output power is 3.5mW at the max power setting, limited by supply voltage (2.5V) and heater resistance
(1.7kΩ). We achieve a maximum resonance shift of 350GHz (Fig. 2, left), corresponding to a step size of ~1.37GHz
for an 8-bit input. Compared to the power delivered to the ARM’s heater, the power overhead for the driver circuit is
negligible at a clock frequency of 500kHz but substantial at 200MHz (Fig. 2, right). The tuning cost of the system
improves with higher tuning offsets (Fig. 3), as the relative power overhead of the driver circuit shrinks compared to
the power going to the heater. For the fabricated ARM filter, a clock frequency of 20MHz provided sufficient
oversampling to minimize the transmission ripples, leading to a tuning cost between 10-15μW/GHz.
3. Conclusion
We demonstrated a monolithically-integrated heater driver system in a commercial bulk CMOS deep-trench process.
We achieved a 350GHz thermal tuning range and 10-15µW/GHz tuning for an ARM. To the best of our knowledge,
this is the first demonstration of ring thermal tuning and efficiency optimization in a deep-trench bulk process.
This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office’s (MTO) POEM
program, contract HR0011-11-C-0100 and NSF CAREER award EECS-0844994. We gratefully acknowledge the help of Jason Orcutt and Yu-Hsin Chen
of MIT and fabrication support of Micron Technology Inc., specifically Roy Meade, Zvi Sternberg, Ofer Tehar-Zahav, Reha Bafrali, Emanuele Baracchi,
Miri Baruch, Erez Conforti, Paul Daley, Eyal Friedman, Harel Frish, Dana Haran, Lilach Makrabi, Maxim Rabinovitch, Matt Ross, and Yoel Shetrit.
4. References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
E. Timurdogan, et al., "Automated Wavelength Recovery for Microring Resonators," CLEO, 2012
M. Georgas, et al., “Addressing link-level design tradeoffs for integrated photonic interconnects,” Custom Integrated Circuits Conf., 2011
G. Li et al., “25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning,” Optics Express, Vol. 19, Issue 21, 2011
P. Dong et al., “Thermally tunable silicon racetrack resonators with ultralow tuning power,” Optics Express, Vol. 18, Issue 19, 2010
M. R. Watts et al., “Adiabatic Resonant Microrings (ARMs) with directly integrated Thermal Microphotonics,” CLEO, 2012.
M. R. Watts, “Adiabatic Microring-Resonators,” Optics Letters, Vol. 35, Issue 19, 2010.
J. S. Orcutt et al., “Open foundry platform for high-performance electronic-photonic integration,” Optics Express, Vol. 20, Issue 11, 2012
J. S. Orcutt, et al., “Nanophotonic integration in state-of-the-art CMOS foundries,” Optics Express, Vol. 19, Issue 3, 2011
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