Download STL7NM60N

STL7NM60N
N-channel 600 V, 0.805 Ω, 5.8 A PowerFLAT™ 5x5
MDmesh™ II Power MOSFET
Features
Order code
VDSS @
TJMAX
RDS(on)
max.
ID
STL7NM60N
650 V
< 0.90 Ω
5.8 A(1)
8
7
5
11
4
1. The value is rated according Rthj-case
12
■
100% avalanche tested
■
Low input capacitance and gate charge
■
Low gate input resistance
1
14
PowerFLAT™ 5x5
Application
■
Switching applications
Description
Figure 1.
This device is an N-channel Power MOSFET
developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
efficiency converters.
Internal schematic diagram
D
D
D
14
13
12
Pin 1
11 G
(not connected)
S 2
10 S
S 3
9 S
Drain
S 4
5
6
7
D
D
D
8 S
Top view
Table 1.
Device summary
Order code
Marking
Package
Packaging
STL7NM60N
7NM60N
PowerFLAT™ 5x5
Tape and reel
November 2011
Doc ID 18348 Rev 2
1/13
www.st.com
www.bdtic.com/ST
13
Contents
STL7NM60N
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
.............................................. 8
Doc ID 18348 Rev 2
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STL7NM60N
1
Electrical ratings
Electrical ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage
600
V
VGS
Gate-source voltage
± 25
V
ID(1)
Drain current (continuous) at TC = 25 °C
5.8
A
ID (1)
Drain current (continuous) at TC=100 °C
3.7
A
ID
(2)
Drain current (continuous) at Tamb = 25 °C
1.4
A
ID
(2)
Drain current (continuous) at Tamb =100 °C
0.9
A
Drain current (pulsed)
5.6
A
4
W
68
W
2
A
119
mJ
15
V/ns
-55 to 150
°C
Value
Unit
Thermal resistance junction-case max.
1.85
°C/W
Thermal resistance junction-amb max.
31.3
°C/W
IDM
(2)(3)
PTOT (2)
Total dissipation at Tamb = 25 °C
PTOT(1)
Total dissipation at TC = 25 °C
Avalanche current, repetitive or not-repetitive
IAS
Single pulse avalanche energy
EAS
dv/dt (5)
TJ
(3)
(4)
Peak diode recovery voltage slope
Operating junction temperature
storage temperature
Tstg
1. The value is rated according Rthj-case.
2. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec
3. Pulse width limited by Tjmax
4. Starting Tj = 25 °C, ID= IAS, VDD = 50 V
5. ISD ≤ 5.8 A, dv/dt ≤ 400 A/µs,VDS peak ≤V(BR)DSS, VDD= 80% V(BR)DSS.
Table 3.
Thermal resistance
Symbol
Rthj-case
Rthj-amb
(1)
Parameter
1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec.
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3/13
Electrical characteristics
2
STL7NM60N
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Drain-source breakdown
voltage (VGS= 0)
ID = 1 mA
IDSS
Zero gate voltage drain
current (VGS = 0)
VDS = 600 V,
VDS = 600 V, Tc = 125 °C
1
100
µA
µA
IGSS
Gate body leakage current
(VDS = 0)
VGS = ± 25 V
100
nA
VGS(th)
Gate threshold voltage
VDS= VGS, ID = 250 µA
3
4
V
RDS(on)
Static drain-source on
resistance
VGS= 10 V, ID= 2.5 A
0.805
0.90
Ω
Min.
Typ.
Max.
Unit
V(BR)DSS
Table 5.
Symbol
600
V
2
Dynamic
Parameter
Test conditions
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 50V, f=1 MHz,
VGS=0
-
363
24.6
1.1
-
pF
pF
pF
(1)
Output equivalent
capacitance
VGS =0, VDS =0 to 480 V
-
130
-
pF
Rg
Gate input resistance
f=1 MHz gate DC bias=0
test signal level = 20 mV
open drain
-
5.4
-
Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD= 480 V, ID = 5 A
VGS =10 V
(see Figure 15)
-
14
2.7
2.7
-
nC
nC
nC
Ciss
Coss
Crss
Coss eq.
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDSS
Table 6.
Switching times
Symbol
Parameter
td(on)
tr
td(off)
tf
4/13
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Test conditions
Min.
VDD= 300 V, ID = 2.5 A,
RG= 4.7 Ω, VGS = 10 V
(see Figure 14)
Doc ID 18348 Rev 2
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Typ.
7
10
26
12
Max.
Unit
ns
ns
ns
ns
STL7NM60N
Electrical characteristics
Table 7.
Symbol
ISD
(3)
trr
Qrr
IRRM
trr
Qrr
IRRM
Parameter
Test conditions
Min
Typ.
Source-drain current
ISDM (1),(2)
VSD
Source drain diode
Max
Unit
5.8
A
23
A
1.3
V
Source-drain current (pulsed)
Forward on voltage
ISD= 5 A, VGS=0
-
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 5 A,
di/dt = 100 A/µs,
VDD = 60 V
(see Figure 16)
-
213
1.5
14
ns
nC
A
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD= 5 A,
di/dt = 100 A/µs,
VDD = 60 V, Tj= 150 °C
(see Figure 16)
-
265
1.8
14
ns
nC
A
1. Pulse width limited by safe operating area.
2. When mounted on FR-4 board of 1inch², 2 oz Cu.
3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
STL7NM60N
2.1
Electrical characteristics (curves)
Figure 2.
Safe operating area
Figure 3.
Thermal impedance
Figure 5.
Transfer characteristics
AM07211v1
ID
(A)
Tj=150°C
Tc=25°C
Single pulse
10
is
ea
ar (on)
DS
R
x
is
1
th
10µs
in a
ion y m
at
er d b
Op ite
Lim
100µs
0.1
1ms
10ms
0.01
0.001
0.1
10
1
Figure 4.
VDS(V)
100
Output characteristics
AM06477v1
AM06478v1
10
ID (A)
9
VGS=10V
8
7
7
6
6
ID
(A)
5
5
4
4
5V
3
3
2
2
1
1
0
0
Figure 6.
20
10
40
0
0
VDS(V)
Gate charge vs gate-source voltage Figure 7.
AM06479v1
VGS
(V)
VDD=480V
ID=5A
12
10
VDS=20V
9
6V
8
VDS
(V)
500
VDS
2
4
6
8
10
VGS(V)
Static drain-source on resistance
AM06480v1
RDS(on)
(Ohm)
VGS=10V
0.88
0.86
400
8
300
0.84
0.82
6
200
4
0.78
100
2
0
0
6/13
0.80
2
4
6
8
10 12
0
14 16 Qg(nC)
0.76
0.74
0
1
2
3
Doc ID 18348 Rev 2
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4
5
ID(A)
STL7NM60N
Figure 8.
Electrical characteristics
Capacitance variations
Figure 9.
AM06481v1
C
(pF)
Output capacitance stored energy
AM06482v1
Eoss
(µJ)
2.5
1000
Ciss
2.0
1.5
100
Coss
10
1.0
0.5
Crss
1
0.1
1
100
10
Figure 10. Normalized gate threshold voltage
vs temperature
AM06483v1
VGS(th)
0
0
VDS(V)
(norm)
100
400 500 600
200 300
VDS(V)
Figure 11. Normalized on resistance vs
temperature
AM06484v1
RDS(on)
(norm)
1.10
ID=2.5A
2.1
ID=250µA
1.9
1.00
1.7
1.5
1.3
0.90
1.1
0.9
0.80
0.7
0.70
-50
-25
0
25
50
75
100
TJ(°C)
Figure 12. Normalized BVDSS vs temperature
AM09028v1
VDS
(norm)
ID=1mA
1.10
0.5
-50 -25
0
25
50
75 100
TJ(°C)
Figure 13. Source-drain diode forward
characteristics
AM08913v1
VSD
(V)
1.2
TJ=-50°C
1.08
TJ=25°C
1.0
1.06
1.04
0.8
1.02
0.6
1.00
0.98
TJ=150°C
0.4
0.96
0.94
0.92
-50 -25
0.2
0
0
25
50
75 100
TJ(°C)
0
1
2
3
4
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5
6
7
ISD(A)
7/13
Test circuits
3
STL7NM60N
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
µF
2200
RL
µF
VGS
IG=CONST
VDD
100Ω
Vi=20V=VGMAX
VD
RG
2200
µF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
AM01469v1
Figure 16. Test circuit for inductive load
Figure 17. Unclamped inductive load test
switching and diode recovery times
circuit
A
A
D.U.T.
FAST
DIODE
B
B
L
A
D
G
VD
L=100µH
S
3.3
µF
B
25 Ω
1000
µF
D
VDD
2200
µF
3.3
µF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
Figure 18. Unclamped inductive waveform
AM01471v1
Figure 19. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDS
VDD
90%
VGS
AM01472v1
8/13
0
10%
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AM01473v1
STL7NM60N
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Package mechanical data
Table 8.
STL7NM60N
PowerFLAT™ 5x5 mechanical dimensions
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.0
A1
0
0.02
0.05
A3
0.24
D
4.90
5.0
5.10
E
4.90
5.0
5.10
E2
2.49
2.57
2.64
e
1.22
1.27
1.32
b
0.43
0.51
0.58
c
0.64
0.71
0.79
Figure 20. PowerFLAT™ 5x5 mechanical drawing
10/13
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STL7NM60N
Package mechanical data
Figure 21. PowerFLAT™ 5x5 recommended footprint (dimensions in mm)
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Revision history
5
STL7NM60N
Revision history
Table 9.
Document revision history
Date
Revision
18-Jan-2011
1
First release.
2
Updated Figure 1: Internal schematic diagram in cover page.
Updated Table 2: Absolute maximum ratings and Section 4:
Package mechanical data.
Minor text changes.
10-Nov-2011
12/13
Changes
Doc ID 18348 Rev 2
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STL7NM60N
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