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STripFET™ V New Low Voltage Power MOSFET technology Technical Marketing Engineer, Fabio Criscione, STMicroelectronics, Catania (Italy) Product & Application Engineer, Filadelfo Fusillo, STMicroelectronics, Catania (Italy) Senior Design Engineer, Domenico Repici, STMicroelectronics, Catania (Italy) Abstract STripFET V is the latest technology introduced, in the semiconductor market, by STMicroelectronics to fulfill the demand of more power per cubic inch of new dc-dc converters for desktop, server, notebook and telecom applications. The latest STripFET V technology takes advantage of the benefits of the planar technology versus the trench one, which includes the lowest gate charge (Qg) per area, and the lowest figure of merit (FOM). In this article will be emphasizing the main features of this new technology and will be showed a comparison versus the previous technology. 1 Introduction The ever increasing demand of high efficiency in motherboards for Desktop PC’s, Notebooks, Servers, Telecom and Communication systems, require synchronous buck converters used in VRM (Voltage Regulator Modules) and PoLs to have very high performances in terms of overall electrical behavior (during switching transients and ON state) and efficiency. In fact, this is a mandatory feature, as VRMs for the latest CPU generation have to manage high power with output currents (ILOAD) up to 110 A and VCORE approximately at 1 V. In order to be in line with the latest needs of high end customers, ST has introduced the 5th generation of design rules of ST’s proprietary STripFETTM technology. The main features of this new technology are listed below: • • • • quirements, in addition to using higher metal thickness than STripFET III technology, STripFET V uses the following integrated modules: • Drain engineering • Double gate oxide thickness • J-FET enrichment region • Vertical contact 2 STripFET V: main features 2.1 Higher metal thickness & J-FET enrichment region Breakdown voltage>25/30V High avalanche ruggedness On resistance < STripFET III Gate charge ≤ STripFET IV Basically, the STripFET V technology allows the achievement of the best trade-off between STripFET III (current technology dedicated to synchronous FET in the Buck-Converter) and STripFET IV (current technology dedicate to control FET in the Buck-Converter) performance in terms of lower on-Resistance and gate charge characteristics. In order to achieve these re- The RDSon, in a Planar Standard Power MOSFET, is given by the sum of many contributions, www.BDTIC.com/ST in particular the resistance due to the wires, metal, channel, J-FET region, epitaxial layer, substrate and back regions: which also means reducing the RJ-FET and so the RDSon, always maintaining the desidered breakdown voltage (BV). RDSon=RWIRES+RMET+RCH+RJFET+REPY+RSUB+RBACK The contribution due to the metal can be easily understood if you consider that the current coming in the silicon from the wires flows horizontally through the metal in order to reach every cell in the silicon. This means that the metal is itself a resistance that contributes on the RDSon growth. In order to reduce this contribution in the STripFET V technology, a metal layer that is 50% higher than STripFET III is used. This approach allows ~10% RDSon gain, due only to the larger metal layer, versus the previous technology. Another rate of the RDSon is produce by the JFET region, which is the N-region between the layer of the P-bodies. It is called the JFET region, because the P-body region acts like the gate region of a general JFET. In order to reduce this resistance, in the STripFET V, we are going to enrich the region between the P-body layers. 2.3 Double gate oxide thickness In order to reduce the gate charge (Qg),so that the switching performances may be improved, a double gate oxide is used only on the region between the P-body layers. The benefit of the double gate oxide thickness is easily understood if we consider the well-know laws: A & Qg α C ⋅ ∆V C =ε d The higher the oxide distance, the lower the capacitances and gate charge (Qg). In other words, thanks to the double gate oxide thickness we are going to reduce C & Qg and so improve the switching performances. 2.4 Vertical contact “µ_trench” In order to decrease the RDSon & Vfec values and improve the UIS ruggedness, a shallow trench is implemented to create a “good contact” between the front metal layer and the source/body regions. The depth of the shallow trench must be higher than the source, but lower than the body, in order to avoid a Source Drain short-circuit. In a generic Power MOSFET the Source must be short-circuited with the Body. This, in the previous technology is obtained by using a part of the silicon only for the body and the short-circuited one with the source which is guaranteed by the Metal, as shown in the picture below. In the graphic above, there is a comparison in terms of RDSon done between the same die size silicon with the JFET enrichment (in pink color) and without the JFET enrichment (in blue one). As you can see thanks at the JFET enrichment we have reduced the RDSon by~ 15%. 2.2 Drain engineering In order to optimize the trade off between breakdown voltage (BV) and on resistance (RDSon) the Drain engineering is used, which is a double layer of the body. Thanks to the Drain engineering we are going to increase the electrical field that can be supported between the P-body layers, which means, (according to Poisson’s law) that it can support more Voltage in this region. Therefore, with the same epitaxial thickness we will have a higher breakdown voltage, if we use the Drain engineering approach, or in other words we can reduce the epitaxial thickness, Instead, with the STripFET V technology, thanks at the vertical contact µ-trench, we are going to gain the part of the body silicon dedicated only to short-circuits. In fact, as you can see, we have the short-circuit for every cell thanks to the vertical contact µ-trench. Therefore, in this case we are gaining the part of the body silicon dedicated only to the short-circuit, so inside the same sili- www.BDTIC.com/ST con we will have more elementary cells, which means improving the RDSon value. Below a comparison is done using the vertical contact µtrench and without it, in the same die size silicon. As you can see, this approach allows ~15% gain in terms of RDSon. Another two benefits, obtained thanks to the vertical contact µ-trench are the forward voltage (Vfec) decrease and the avalanche ruggedness (UIS). In fact, thanks to it, we can dope the body region below the Source in an appropriate manner, through the vertical contact µ-trench. Instead, with the STripFET III technology this region isn’t accessible to any form of doping. Thanks to this kind of doping we can reduce the forward voltage (Vfec) of the diode body-drain internal to the MOSFET, in fact its value is inversely proportional to the dope. This parameter is very important, in particular in a synchronous dc-dc buck converter application. In fact, during the dead-time the current flows through the bodydrain diode internal to the MOSFET. Therefore, during the dead-time the losses are proportional to the losses inside the parasitic diode internal to the MOSFET, and so proportional to the Vfec. This means that the lower the Vfec, the lower the losses are in the synchronous dc-dc buck converter during the dead-time. As you can see in the comparison below, which is done between a distribution developed with STripFET III devices and another one obtained with STripFET V devices having the same size silicon, thanks to the doping of the body region through the vertical contact µ-trench, we get a tighter distribution and also ~20% lower Vfec. As stated above, another benefit of the vertical contact µ-trench is the improvement of the avalanche ruggedness (UIS). In fact, thanks to the doping of the body region below the source, we reduce the resistance inside the body (Rb), below the source. This will reduce the voltage drop across this resistance and so the possibility that the parasitic bipolar transistor is turned on, thus imparting increased dv/dt immunity. In order to understand what is mentioned above we can consider the equivalent circuit of an N-channel MOSFET. From this circuit it is easy to see that, in the off state, an unexpected increase in drain voltage changes the voltage across Cdb, and it develops current flowing through Rb. The higher dv/dt is, the higher the current is. When the voltage drop across the Rb, goes over VBEon(emitter-base forward bias voltage where the parasitic bipolar transistor is turned on, approximately 0.7[V]), the devices falls into an avalanche breakdown. The following equation shows the VBE capability: ic = CDB dvD dt vBE = Rb ⋅ CDB dvD dt From the equation above, it is easily understood that the lower Rb causes lower VBE, thus enhancing the avalanche ruggedness and dv/dt immunity of the device. Comparing the failure current distribution between the StripFET III and STripFET V, thanks to the doping of the body region, through the vertical contact µ-trench, we are improving the failure current by. ~20%. 3 Application section In order to demonstrate the benefits using this new technology, two tests were performed on the L6710 controller demoboard, which implements a two phase step-down controller with a 180º phase-shift between each phase. In the first test the same Low Side STD90N03L has been fixed and it is compared with the performance of two www.BDTIC.com/ST different High Sides, the first one is the STD60N3LH5, coming from the new STripFET V technology, and the second one is the STD50N03L, coming from the previous technology, with the same die size. Test conditions: Vin = 12V Iout max = 40A Vout = 1.5V fsw = 300 kHz Test conditions: Vin = 12V Iout max = 44A Vout = 1.5V fsw = 440 kHz STripFETIII STD60N3LH5 STripFET V Gain 19 13 42% 10 8 20% 20.7 13.5 35% 24 16 33% Qsw [nC] 7 4.4 37% Ciss [pF] 1434 1350 6% 7.1 5.3 25% 240 128 47% Parameters RDSon max@5V[mΩ] RDSon max@10V[mΩ] (RDSon -Rwires) x Act. Area 10V[mΩxmm2] Qg typ. @10V [nC] Qg/Act. Area [nC/mm2] 10V FOM @10V [RDSon max x Qg typ] STD50N3L As you can see in the graphic above, the STD60N3LH5 new STripFET V device has the highest efficiency ( about 2% at full load current) in the whole current range, due to the lowest RDS(on) and Qg. This allows the reduction of the switching and gate drive losses, together with an improvement of conduction losses (even if for a very short HS turn on). In the second test the same High Side STD50N03L is fixed and it is compared with the performance of two different Low Sides, the first one is the STD85N3LH5, coming from the new STripFET V technology, and the second one is the STD70N03L, coming from the previous technology, with the same die size. STD70N3L STripFET III STD85N3LH5 STripFET V Gain 13 6.5 50% 7.3 5 31.5% 21.7 14 35% 32 26 18.5% Ciss [pF] 2200 1870 15% VFEC max [V] 1.3 1.1 15% 7.1 5.95 16% 233.6 130 44% Parameters RDSon max@5V[mΩ] RDSon max@10V[mΩ] (RDSon -Rwires) x Act. Area 10V[mΩxmm2] Qg typ. @10V [nC] Qg/Act. Area [nC/mm2] 10V FOM @10V [RDSon max x Qg typ] Also in this case, it is easily understood that thanks to the STD85N3LH5’s better specification versus the STD70N03L’s (previous technology), we obtain a better efficiency in the overall current range. In particular, at low current, thanks to lower Qg and Vfec, and at high current due to lower RDSon and Vfec. In addition a comparison on the L6728 demo board has been performed, which implements a single phase step-down controller with 1xHS and 1xLS. In particular, two different HS and LS coming from the new technology and the previous ones with the same die-size have been contrasted, STD50N03L & STD70N03L (previous technology) Vs STD60N3LH5 & STD85N3LH5 (new STripFET V one). The main features of the devices used are mentioned above: Test conditions: Vin = 12V Iout max = 20A Vout = 1.25V fsw = 300 kHz www.BDTIC.com/ST As shown the new STripFET V devices achieve up to 3% of benefits in terms of efficiency, which means a gain of about 1W with a single phase synchronous dc-dc converter. In addition, below the best thermal behaviors obtained with the new technology are shown: The temperature measurements are made after 15 min of continuous running at 80 % of the load (16 A) with air flow by Flir System InfraCAM, and it shows the best thermal behavior obtained thanks to the new technology. 4 Conclusion In order to summarize what has been explained up to this point, if we compare the STripFET V technology to the previous one, (with the same silicon size) thanks to this new technology, we will obtain devices with better conduction losses, switching behavior and also avalanche ruggedness. In other words, we will have the same features obtained with the previous technology with a smaller silicon. Of course, the previously mentioned intrinsic Power MOSFET features allow a reduction in number of paralleled devices (shorter BOM list), higher power density with smaller board form factor and component cost savings. Furthermore, the lowest FOM and Qg allows designers to increase the switching frequency work to reduce the size of passive components (inductor) and to reduce the unwanted output voltage ripple. www.BDTIC.com/ST